CN109979828A - A kind of silicon carbide power device die bonding method - Google Patents

Abstract

The invention discloses a silicon carbide power device chip bonding method, which belongs to the technical field of microelectronic packaging. The bonding method of the present invention comprises the following steps: arranging a barrier layer and an adhesive layer on the passive surface of the silicon carbide power device wafer and the substrate panel respectively; and printing the nano-silver solder paste on the silicon carbide power device wafer with a uniform thickness. On the bonding layer with the substrate panel, pressureless sintering is performed to form a silver sintered layer; the silver sintered layer is oxidized and polished; cut to form separate silicon carbide power device chips and substrates; The silver sintered layer on the device chip is arranged face-to-face on the silver sintered layer on the substrate, and thermocompression bonding is performed to realize the bonding connection of the silicon carbide power device chip. The invention has the characteristics of simplicity, high reliability, high yield and high yield.

Description

A kind of silicon carbide power device chip bonding method

technical field

The invention relates to microelectronic packaging technology, in particular to silicon carbide power device chip packaging technology.

Background technique

The rapid development of aerospace, electric vehicles and new energy power generation technology has made the performance indicators of power electronic systems increasingly demanding. The development of high-power device chips used in extreme environments such as high temperature is the key direction of the current development of power electronics technology. Since the power device chips based on the first-generation semiconductor material silicon (Si) and the second-generation semiconductor material (GaAs) cannot work continuously in a high temperature environment above 200°C, the silicon carbide (SiC) material developed later The extreme operating temperature of the third-generation wide-bandgap semiconductor device chip represented by it can reach about 500 ℃ or even higher, which can better meet the development requirements of future power electronics technology. However, in such a high temperature environment, the existing die-bonding material, lead-free solder (Pb-free), will melt and cause connection failure, which is not suitable for die-bonding packaging of wide-bandgap devices such as silicon carbide (SiC). In recent years, low-temperature bonding technology represented by sintered nano-silver technology is the main trend of the development of power device chips towards high-temperature and high-reliability applications. The basic principle is to use the high surface energy and low melting point characteristics of nano-scale silver metal particles To achieve low-pressure low-temperature sintering bonding of chips and substrates. The formed silver sintered layer has excellent electrical and thermal properties, high melting point, and can withstand the highest working temperature of 710°C, which is an ideal structure for realizing chip bonding of silicon carbide power devices.

The silver sintered native layer has obvious porous features with pore sizes in the sub-micron to micron range. During the sintering process, pressure is required to form a relatively dense sintered layer with low porosity, which makes it difficult to accurately control the thickness of the sintered silver layer, and the thickness of the silver sintered layer is limited to several micrometers to tens of micrometers. If the thickness of the sintered silver layer is too thin, in a high temperature environment, due to the different coefficients of thermal expansion (CTE) of the package structure materials, excessive shear strain and stress concentration will occur, resulting in a serious decrease in the reliability of the sintered silver layer. At the same time, the growth of grains and pores will occur in the silver sintered layer in a high temperature environment, resulting in the coarsening of the microstructure and the constitutive degradation of the silver sintered layer, which is more prone to fatigue failure. In addition, if the size of the bonded chip is too large, the volatilization of the organic solvent in the silver solder paste will be hindered during sintering, and a large area of pore defects will be formed in the sintered layer, resulting in a significant decrease in the bonding strength, and it is difficult to achieve high-quality and high-yield sintering.

Therefore, in order to solve the above-mentioned reliability and yield problems faced by the sintered silver bonding of silicon carbide power device chips, it is urgent to propose a reasonable chip bonding method to effectively reduce the complexity of the sintered silver bonding process of silicon carbide power device chips. Difficulty, while improving the reliability, yield and yield of silicon carbide power device chip bonding.

SUMMARY OF THE INVENTION

The invention provides a simple, high-reliability, high-yield, and high-yield chip bonding method for power device chip packaging, especially silicon carbide power device chip sintered silver bonding packaging.

In order to achieve the above purpose, the present invention provides a silicon carbide power device chip bonding method, which mainly includes the following steps:

Step 1: A barrier layer and an adhesive layer are sequentially arranged on the passive surface of the silicon carbide power device wafer. The barrier layer and the adhesive layer are arranged in this order on the substrate panel. The configuration method can be, but is not limited to, sputtering, vacuum evaporation and electroless plating, preferably sputtering. The substrate panel can be, but is not limited to, a ceramic-based copper clad laminate, an organic substrate and a copper substrate, preferably a ceramic-based copper clad laminate. The barrier layer may be, but not limited to, titanium (Ti), tantalum (Ta), tungsten (W) and other metal materials, preferably titanium (Ti). The adhesive layer may be, but is not limited to, metal materials such as silver (Ag), nickel (Ni), and gold (Au), preferably silver (Ag). The thickness of the barrier layer ranges from 0.05 μm to 1.0 μm, preferably 0.1 μm. The thickness of the adhesive layer is in the range of 0.1 μm to 5.0 μm, preferably 1.0 μm.

Step 2: Print the nano-silver solder paste with a uniform thickness on the bonding layer of the silicon carbide power device wafer. The nano-silver solder paste is printed on the adhesive layer of the substrate panel with a uniform thickness. The printed silicon carbide power device wafer and substrate panel are placed on a heating table for pressureless sintering to form a silver sintered layer. The temperature range of the heating stage is set to 250°C-350°C, preferably 260°C. The sintering time ranges from 15 minutes to 60 minutes, preferably 30 minutes. After the sintering is completed, the thickness of the silver sintered layer ranges from 15 microns to 50 microns, preferably 25 microns.

Step 3: Oxidize the silver sintered layer on the silicon carbide power device wafer. The silver sintered layer on the substrate panel is oxidized. The oxidation treatment method can be, but is not limited to, water vapor oxidation and soaking hygroscopic oxidation, preferably water vapor oxidation.

Step 4: polishing the silver sintered layer on the silicon carbide power device wafer. Polish the silver sintered layer on the substrate panel. The polishing treatment method may be, but not limited to, mechanical chemical polishing. The thickness of the silver sintered layer after polishing is in the range of 10 micrometers to 40 micrometers, preferably 20 micrometers.

Step 5: Cutting the silicon carbide power device wafer to form separate single silicon carbide power device chips. The substrate panels are cut to form separate individual substrates. The cutting method may be, but is not limited to, blade cutting, laser cutting and water jet cutting methods.

Step 6: The silver sintered layer on the silicon carbide power device chip is arranged face-to-face on the silver sintered layer on the substrate by the surface mount method, and the configured silicon carbide power device chip and the substrate are placed on the heating table for hot pressing Bonding to realize the chip bonding connection of silicon carbide power devices. The temperature range of the heating stage is set to 250°C-350°C, preferably 300°C. The bonding time range is set to 15 minutes to 90 minutes, preferably 45 minutes. The bonding pressure range is set to 0.1MPa-10MPa, preferably 1MPa.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a silicon carbide power device die-bonding result completed by the manufacturing method of the present invention.

2A-2E are schematic diagrams of a manufacturing process of a silicon carbide power device chip bonding method according to an embodiment of the manufacturing method of the present invention, taking the silicon carbide power device chip bonding shown in FIG. 1 as an example.

In the above figure, 1 is the silicon carbide power device chip wafer, 2 is the substrate panel, 3 is the first barrier layer, 4 is the second barrier layer, 5 is the first adhesive layer, 6 is the second adhesive layer, 7 is the second adhesive layer. is the first silver sintering layer, 8 is the second silver sintering layer, 9 is the silicon carbide power device chip, and 10 is the substrate.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Please refer to FIG. 1 for the described silicon carbide power device chip bonding structure, in the structure from top to bottom the spatial orientation is as follows: silicon carbide power device chip 9, first barrier layer 3, first adhesive layer 5, first The silver sintered layer 7 , the second silver sintered layer 8 , the second barrier layer 4 , the second adhesive layer 6 and the substrate 10 . The substrate panel 2 can be, but is not limited to, a ceramic-based copper clad laminate, an organic substrate and a copper substrate, preferably a ceramic-based copper clad laminate. The first barrier layer 3 and the second barrier layer 4 may be, but are not limited to, metal materials such as titanium (Ti), tantalum (Ta), and tungsten (W), preferably titanium (Ti). The first adhesive layer 5 and the second adhesive layer 6 may be, but are not limited to, metal materials such as silver (Ag), nickel (Ni), and gold (Au), preferably silver (Ag). The thicknesses of the first barrier layer 3 and the second barrier layer 4 are in the range of 0.05 μm to 1.0 μm, preferably 0.1 μm. The thicknesses of the first adhesive layer 5 and the second adhesive layer 6 are in the range of 0.1 μm to 5.0 μm, preferably 1.0 μm. The thickness of the first silver sintered layer 7 and the second silver sintered layer 8 ranges from 10 micrometers to 40 micrometers, preferably 20 micrometers.

The silicon carbide power device chip bonding method includes the following steps:

Step 1: As shown in FIG. 2A , a first barrier layer 3 and a first adhesive layer 5 are sequentially arranged on the passive surface of the silicon carbide power device wafer 1 . The second barrier layer 4 and the second adhesive layer 6 are arranged in this order on the substrate panel 2 . The configuration method can be, but is not limited to, sputtering, vacuum evaporation and electroless plating, preferably sputtering. The substrate panel 2 can be, but is not limited to, a ceramic-based copper clad laminate, an organic substrate and a copper substrate, preferably a ceramic-based copper clad laminate. The first barrier layer 3 and the second barrier layer 4 may be, but are not limited to, metal materials such as titanium (Ti), tantalum (Ta), and tungsten (W), preferably titanium (Ti). The first adhesive layer 5 and the second adhesive layer 6 may be, but are not limited to, metal materials such as silver (Ag), nickel (Ni), and gold (Au), preferably silver (Ag). The thicknesses of the first barrier layer 3 and the second barrier layer 4 are in the range of 0.05 μm to 1.0 μm, preferably 0.1 μm. The thicknesses of the first adhesive layer 5 and the second adhesive layer 6 are in the range of 0.1 μm to 5.0 μm, preferably 1.0 μm.

Step 2: As shown in FIG. 2B , the nano-silver solder paste is printed on the first adhesive layer 5 of the silicon carbide power device wafer 1 with a uniform thickness. The nano-silver solder paste is printed on the second adhesive layer 6 of the substrate panel 2 with a uniform thickness. The printed silicon carbide power device wafer 1 and the substrate panel 2 are respectively placed on a heating table (not shown) for pressureless sintering to form a first silver sintered layer 7 and a second silver sintered layer 8 . The temperature range of the heating stage is set to 250°C-350°C, preferably 260°C. The sintering time ranges from 15 minutes to 60 minutes, preferably 30 minutes. After the sintering is completed, the thickness of the first silver sintered layer 7 and the second silver sintered layer 8 ranges from 15 μm to 50 μm, preferably 25 μm. After the sintering is completed, the thickness of the first silver sintered layer 7 and the second silver sintered layer 8 ranges from 15 μm to 50 μm, preferably 25 μm.

Step 3: Oxidize the first silver sintered layer 7 on the silicon carbide power device wafer 1 . The second silver sintered layer 8 on the substrate panel 2 is oxidized. The oxidation treatment method can be, but is not limited to, water vapor oxidation and soaking hygroscopic oxidation, preferably water vapor oxidation. Through the oxidation treatment, silver oxide thin films are formed on the surface of the inner holes of the first silver sintered layer 7 and the second silver sintered layer 8, which has an inhibitory effect on the coarsening of the microstructure and can be kept stable in a high temperature environment.

Step 4: As shown in FIG. 2C , after the oxidation treatment, the first silver sintered layer 7 on the silicon carbide power device wafer 1 is polished, and the second silver sintered layer 8 on the substrate panel 2 is polished. The polishing treatment method may be, but not limited to, mechanical chemical polishing. After polishing, the thickness of the first silver sintered layer 7 and the second silver sintered layer 8 ranges from 10 micrometers to 40 micrometers, preferably 20 micrometers. The purpose of polishing the first silver sintered layer 7 and the second silver sintered layer is to form a dense, flat and smooth surface, and to improve the quality of subsequent thermal compression bonding.

Step 5 : as shown in FIG. 2D , the silicon carbide power device wafer 1 is cut to form separate single silicon carbide power device chips 9 . The substrate panel 2 is cut to form separate individual substrates 10 . The cutting method may be, but is not limited to, blade cutting, laser cutting and water jet cutting methods.

Step 6: As shown in FIG. 2E, the first silver sintered layer 7 on the silicon carbide power device chip 9 is arranged face-to-face on the second silver sintered layer 8 on the substrate 10 by surface mounting, and the arranged silicon carbide The power device chip 9 and the substrate 10 are placed together on a heating table (not shown) for thermocompression bonding to realize bonding connection. The temperature range of the heating stage is set to 250°C-350°C, preferably 300°C. The bonding time range is set to 15 minutes to 90 minutes, preferably 45 minutes. The bonding pressure range is set to 0.1MPa-10MPa, preferably 1MPa. The purpose of the thermocompression bonding is to realize the bonding connection through atomic diffusion between the first silver sintered layer 7 and the second silver sintered layer 8 .

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (9)

1. a silicon carbide power device chip bonding method is characterized in that it mainly comprises the following steps: Step 1: Arrange the first barrier layer and the first adhesive layer in sequence on the passive surface of the silicon carbide power device wafer; Arrange the second barrier layer and the second adhesive layer in sequence on the substrate panel; Step 2: print the nano-silver solder paste on the first adhesive layer of the silicon carbide power device wafer with a uniform thickness; print the nano-silver solder paste on the second adhesive layer of the substrate panel with a uniform thickness; complete the printing The silicon carbide power device wafer and the substrate panel are respectively placed on the heating table for pressureless sintering to form a first silver sintered layer and a second silver sintered layer; Step 3: oxidizing the first silver sintered layer on the silicon carbide power device wafer; oxidizing the second silver sintering layer on the substrate panel; Step 4: polishing the first silver sintered layer on the silicon carbide power device wafer, and polishing the second silver sintered layer on the substrate panel; Step 5: cutting the silicon carbide power device wafer to form a separate single silicon carbide power device chip; cutting the substrate panel to form a separate single substrate; Step 6: The first silver sintered layer on the silicon carbide power device chip is arranged face-to-face on the second silver sintered layer on the substrate by surface mounting, and the configured silicon carbide power device chip and the substrate are placed on the heating table together Thermocompression bonding is carried out on the top to realize the bonding connection. 2 . The method for chip bonding of silicon carbide power devices according to claim 1 , wherein the configuration method in step 1 adopts sputtering, vacuum evaporation or chemical plating. 3 . 3 . The method for chip bonding of silicon carbide power devices according to claim 1 , wherein the substrate panel in step 1 adopts a ceramic-based copper clad laminate, an organic substrate or a copper substrate. 4 . 4 . The silicon carbide power device chip bonding method according to claim 1 , wherein the first barrier layer and the second barrier layer in step 1 can be selected from titanium (Ti), tantalum (Ta) or tungsten. 5 . (W) and other metal materials; the first adhesive layer and the second adhesive layer can choose metal materials such as silver (Ag), nickel (Ni) or gold (Au); the first barrier layer and the second barrier layer The thickness of the layers is in the range of 0.05 micrometers to 1.0 micrometers; the thicknesses of the first and second adhesive layers are in the range of 0.1 micrometers to 5.0 micrometers. 5 . The silicon carbide power device chip bonding method according to claim 1 , wherein the sintering temperature range in step 2 is set to 250°C-350°C; the sintering time range is set to 15 minutes-60 minutes; 6 . After the sintering is completed, the thickness of the first silver sintered layer and the second silver sintered layer ranges from 15 micrometers to 50 micrometers. 6 . The silicon carbide power device chip bonding method according to claim 1 , wherein the oxidation treatment method in step 3 adopts water vapor oxidation or soaking moisture absorption oxidation method. 7 . 7 . The silicon carbide power device chip bonding method according to claim 1 , wherein the polishing treatment method in step 4 is used in mechanical chemical polishing; after polishing treatment, the first silver sintered layer and the second The thickness of the silver sintered layer ranges from 10 microns to 40 microns. 8 . The method for chip bonding of silicon carbide power devices according to claim 1 , wherein the cutting method in step 5 adopts blade cutting, laser cutting or water jet cutting. 9 . 9 . The silicon carbide power device chip bonding method according to claim 1 , wherein the temperature range of the thermocompression bonding in step 6 is set to 250° C.-350° C., and the bonding time range is set to 15 minutes. 10 . -90 minutes; the bonding pressure range is set to 0.1MPa-10MPa.