CN1099118C - Semi-conductor memory device and it testing circuit, memory device system and data transmission system - Google Patents

Abstract

The semiconductor memory of the present invention can increase the data transfer speed of the memory without increasing the chip area. Memory cells 11 - 0 to 11 - 3 are arranged in a matrix on the memory chip 10 . The data input/output circuit 12 is arranged along one side of the memory chip 10 . The data bus 13 is provided between the memory cells and connected to the data input/output circuit 12 . In each memory unit, the cell array controller CAC and the row decoder RD are opposite to each other, and the column decoders CD0 and CD1 are opposite to the DQ buffer DQ. The local DQ line 18a is provided between the memory cell arrays CAL, CAR, and the global DQ line 18b is provided on the storage elements CAL, CAR. The direction in which the local DQ line 18a extends is perpendicular to the direction in which the global DQ line 18b extends.

Description

Semiconductor memory and its test circuit, memory system, and data transfer system

technical field

The present invention relates to a multi-bit semiconductor memory that simultaneously performs input and output of data of a plurality of bits.

Background technique

In a digital system having a semiconductor memory such as DRAM (Dynamic Random Access Memory), the following measures are taken to increase the data transfer speed.

The first method is to make the semiconductor memory a multi-bit type. A multi-bit (×2 ⁿ ) type semiconductor memory is generally configured such that 2 ⁿ (n is a natural number) bits of data can be input and output simultaneously.

The second method is to perform data input and output operations in synchronization with a high-frequency external clock output from a CPU (Central Processing Unit). In such a clock synchronous semiconductor memory (SDRAM, RDRAM, etc.), since the frequency of the external clock is higher, continuous data can be input and output at a higher speed, thereby improving the data transfer speed.

A third approach is to arrange a plurality of memory (bank) cells in one semiconductor memory (memory chip). The plurality of memory units are made to have the same elements, so that the plurality of memory units can independently perform data input and output operations. As a result, the time until the first data is accessed (latency time) can be shortened, and thus the data transfer speed can be increased.

FIG. 3 shows an outline of a chip layout of a conventional semiconductor memory.

This semiconductor memory has all three measures described above.

On one memory chip 10, four memory cells 11-0 to 11-3 are arranged. In each memory unit 11-0 to 11-3, a memory cell array and a cell array controller are formed, and a row decoder, a column decoder, and a DQ buffer (referred to as an output/input portion of the memory unit) are also formed. Buffer) and other peripheral circuits.

On the other hand, a data input/output area 12 is arranged on one memory chip 10 . A plurality of input/output circuits (I/O) are formed in the data input/output area 12, for example, 16 input/output circuits are formed when simultaneously inputting and outputting 16-bit (2 bytes) data.

A data bus 13 is disposed between the memory cells 11-0 to 11-3. The data bus 13 serves as a data path between the memory cells 11 - 0 to 11 - 3 and the data input/output area 12 . The data bus 13 is configured to transfer 16-bit data when simultaneously inputting and outputting 16-bit (2-byte) data, for example.

The data input/output operation of the semiconductor memory described above is performed as follows.

First, one memory cell is selected from the four memory cells 11-0 to 11-3. In a selected memory cell, the access operation of the storage element is performed according to the address signal, and the selected memory cell outputs 2 ⁿ bits (for example, 16 bits (2 bytes)) of data.

The ²ⁿ -bit data is introduced into the data input/output area 12 through the data bus 13, and output from the data input/output area 12 to the outside of the semiconductor memory (memory chip).

The problem that must be considered in the above-mentioned semiconductor memory is the ratio of the area of the data bus 13 in the entire area on a memory chip. That is, making the area of the data bus 13 as small as possible is very important to reduce the area of the chip.

However, as the number of bits for simultaneous input and output increases, the area of the data bus also increases.

That is to say, when the structure of the semiconductor memory is changed from 16-bit type (×16)→32-bit type (×32)→64-bit type (×64) to multi-bit, the storage chip The disadvantage of increased area.

Contents of the invention

The present invention aims to solve the above-mentioned disadvantages, and its object is to increase the data transfer speed without increasing the chip area in a multi-bit clock-synchronized memory cell type semiconductor memory.

To achieve the above object, the semiconductor memory of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of memory units arranged on the memory chip are used to store and output multi-bit data independently of each other, and each memory unit includes

A plurality of memory cell blocks, each memory cell block has 2 sub-blocks, sense amplifiers, word lines, data lines and column select lines, each of the sub-blocks is composed of 1 memory cell array, the sense amplifiers are located in the Between the two sub-blocks, the word lines, data lines and column selection lines are arranged on the memory cell arrays constituting the two sub-blocks, the memory cell blocks are separated along the columns of the memory cells, and the column selection lines and data lines and the sub-blocks are also spaced along the column of memory cells;

at least one column decoder, located at the first terminal of each column of memory cells, and connected to the column selection line;

a plurality of row decoders located at the first end of each row of memory cells, the word lines extending along the memory cells and connected to the word lines, each of the row decoders being provided to a block of memory cells ;

a plurality of DQ buffers located at end 2 of each row of memory cells; and

A cell array controller, located at the first end of each row of memory cells, for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip for receiving multi-bit data from an external device and outputting multi-bit data to an external device,

The data bus provided to the plurality of memory cells extends parallel to the columns of the memory cells for transferring multi-bit data between the plurality of memory cells and the data input/output area.

In addition, the semiconductor memory of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of main memory units arranged on the memory chip are used to store and output multi-bit data independently of each other, and each is composed of a plurality of sub-memory units, each including

A plurality of memory cell blocks, each memory cell block has 2 sub-blocks, sense amplifiers, word lines, data lines and column select lines, each of the sub-blocks is composed of 1 memory cell array, the sense amplifiers are located in the Between the two sub-blocks, the word lines, data lines and column selection lines are arranged on the memory cell arrays constituting the two sub-blocks, the memory cell blocks are separated along the columns of the memory cells, and the column selection lines and data lines and the sub-blocks are also spaced along the column of memory cells;

at least one column decoder, located at the first terminal of each column of memory cells, and connected to the column selection line;

a plurality of row decoders located at the first end of each row of memory cells, the word lines extending along the memory cells and connected to the word lines, each of the row decoders being provided to a block of memory cells ;

a plurality of DQ buffers located at end 2 of each row of memory cells; and

A cell array controller, located at the first end of each row of memory cells, for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip for receiving multi-bit data from an external device and outputting multi-bit data to an external device,

A plurality of data buses provided to at least two of the sub-blocks extend parallel to the row of the memory cells for transferring multi-bit data between the sub-memory cells and the data input/output area.

In addition, the semiconductor memory of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of main memory units arranged on the memory chip are used to store and output multi-bit data independently of each other, and each is composed of a plurality of sub-memory units, each including

A plurality of memory cell blocks, each memory cell block has 2 sub-blocks, sense amplifiers, word lines, data lines and column select lines, each of the sub-blocks is composed of 1 memory cell array, the sense amplifiers are located in the Between the two sub-blocks, the word lines, data lines and column selection lines are arranged on the memory cell arrays constituting the two sub-blocks, the memory cell blocks are separated along the columns of the memory cells, and the column selection lines and data lines and the sub-blocks are also spaced along the column of memory cells;

at least one column decoder, located at the first terminal of each column of memory cells, and connected to the column selection line;

a plurality of row decoders located at the first end of each row of memory cells, the word lines extending along the memory cells and connected to the word lines, each of the row decoders being provided to a block of memory cells ;

a plurality of DQ buffers located at end 2 of each row of memory cells, each of said DQ buffers serving a block of memory cells; and

A cell array controller, located at the first end of each row of memory cells, for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip for receiving multi-bit data from an external device and outputting multi-bit data to an external device,

a plurality of data buses provided to at least two of said sub-blocks, extending parallel to the rows of said memory cells, for transferring multi-bit data between said sub-memory cells and said data input and output regions,

Wherein, the input and output areas are separated along the rows of the memory units, the data bus is arranged on both sides of each of the input and output areas and separated along the columns of the memory units, and the sub memory units are arranged on both sides of each of the data buses.

In addition, the semiconductor memory of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of memory units arranged on the memory chip are used to read and write multi-bit data independently of each other, and each memory unit includes

A plurality of memory cell blocks, each memory cell block includes 2 sub-blocks, sense amplifiers and DQ lines, each of the sub-blocks includes a memory cell array, word lines and data lines, the word lines extend in the row direction, the The data line extends in the column direction, the sense amplifier and the DQ line are located between the two sub-blocks, the DQ line extends parallel to the word line, the DQ line is connected to the sense amplifier,

a column selection line provided on the plurality of memory cell blocks, the column selection line extending parallel to the data line,

column decoder, connected to the column select line,

row decoder, connected to the word line,

DQ buffer, connected to the DQ line,

a memory cell selector for selecting one of the plurality of memory cells,

a cell array controller for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip, and

a data bus provided between the plurality of memory units, connected to the plurality of memory units, extending parallel to the data line, for transferring one of the plurality of memory units to the data input-output area Multibit data between.

In addition, the semiconductor memory of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of memory units arranged on the memory chip are used to read and write multi-bit data independently of other memory units, and each memory unit includes

a plurality of memory cell blocks, each memory cell block includes a pair of sub-blocks, sense amplifiers and DQ lines corresponding to each pair of said sub-blocks, each of said sub-blocks includes a memory cell array, a word line and a data line, so The word line extends in the row direction, the data line extends in the column direction, the sense amplifier and the DQ line are located between the two sub-blocks, the DQ line extends parallel to the word line, and the DQ line connected to the sense amplifier,

a column selection line provided on the plurality of memory cell blocks, the column selection line extending parallel to the data line,

column decoder, connected to the column select line,

row decoder, connected to the word line,

DQ buffer, connected to the DQ line,

a memory cell selector for selecting one of the plurality of memory cells,

a cell array controller for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip, and

a data bus provided between the plurality of memory units, connected to the plurality of memory units, extending parallel to the data line, for transferring one of the plurality of memory units to the data input-output area Multibit data between.

In addition, a test circuit of the present invention for testing a semiconductor memory including a memory cell array having first and second memory cell blocks is characterized by comprising

registers for holding the 1st and 2nd test data,

a data writing circuit, simultaneously writing the first test data into the first memory cells in the first memory cell block and writing the second test data into the second memory cells in the second memory cell block,

a data read circuit for simultaneously reading the first read data stored in the first memory cell block and the second read data stored in the second memory cell block,

a comparison circuit, comparing the first read data with the first test data and outputting the first output data, and comparing the second read data with the second test data and outputting the second output data,

a decision circuit, based on the first and second output data to determine whether the first and second memory cells are defect-free, when at least one of said first and second output data indicates at least one of said first and second memory cells When the cell is defective, the decision circuit outputs 1-bit data indicating the defect,

Wherein, when at least one of the first and second output data indicates that at least one of the first and second memory units is defective, the output of the decision circuit indicates whether the first memory unit is a first memory unit that is not defective. The sum of the signals is a second signal indicating whether the second memory cell is defect-free.

Furthermore, a test circuit of the present invention for testing a semiconductor memory including a memory cell array having a plurality of memory cell blocks is characterized by comprising

registers for holding multiple test data,

a data writing circuit, simultaneously writing test data to the memory cells in the memory cell block,

a data read circuit simultaneously reads a plurality of read data stored in the memory cell block,

a comparison circuit that compares the read data with the test data and outputs a plurality of output data,

a decision circuit, which determines whether the memory cell is non-defective according to the output data, and when at least one of the output data indicates that at least one of the memory cells is defective, the output of the decision circuit indicates that the memory cell is defective 1 bit data,

Wherein, when at least one of the output data indicates that at least one of the memory cells is defective, the decision circuit outputs a signal indicating whether at least one of the memory cells is not defective.

In addition, the data transmission system of the present invention,

having a plurality of memory blocks arranged extending in the column direction,

Each memory block is composed of a switch array composed of a plurality of switches arranged in a matrix, a row decoder for selecting a row of the switch array arranged adjacent to an end of the switch array in a row direction, and a row decoder adjacent to the switch array. a local DQ line extending along the row direction arranged at the end of the column direction, and a data line connecting a plurality of switches of the switch array and guiding data to the local DQ line,

It is characterized in that,

a first end configured to extend along the column direction on the plurality of memory blocks is connected to a global DQ line of the local DQ line,

a column decoder for selecting a column of the switch array of the plurality of memory blocks arranged adjacent to ends in the column direction of the plurality of memory blocks, and

A data input/output circuit connected to the second end of the global DQ line and connected to the second end of the global DQ line, which is arranged adjacent to the ends in the column direction of the plurality of memory blocks, for inputting and outputting data.

In addition, the memory system of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized by including

A memory chip is provided, a plurality of main memory units composed of a plurality of sub-memory units arranged on the memory chip, and a data input and output of multi-bit data input and output performed synchronously with a clock on the memory chip area, two or more sub-memory units among all the sub-memory units constituting the plurality of main memory units are arranged in common and extend in the row direction, and the sub-memory units serving as the plurality of main memory units are connected to the data input and output a plurality of data buses of said multi-bit data path between regions, a CPU chip generating said clock signal, and an I/O line interconnecting said memory chip and said CPU chip,

The plurality of sub-memory chips include

It has two small memory blocks formed by memory cell arrays and arranged in the column direction, a sense amplifier arranged between the two small memory blocks, and word lines, data lines, and column selections arranged on the memory cell arrays. , a plurality of storage blocks arranged in the column direction,

a column decoder disposed at one of two ends in the column direction and connected to at least one of the column selection lines,

a row decoder connected to the word line arranged at one of the two ends in the row direction and provided in each of the middle memory blocks,

a DQ buffer disposed at the other of the two ends in the column direction, and

a cell array controller disposed at the other of the two ends in the row direction and controlling a read or write operation of the multi-bit data, and

Each of the plurality of sub-memory cells is configured to read or write the multi-bit data independently of each other.

In addition, the memory system of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of memory units arranged on the memory chip are used to independently store and output multi-bit data synchronized with a clock signal, and each memory unit includes

A plurality of memory cell blocks, each memory cell block has 2 sub-blocks, sense amplifiers, word lines, data lines and column select lines, each of the sub-blocks is composed of 1 memory cell array, the sense amplifiers are located in the Between the two sub-blocks, the word lines, data lines and column selection lines are arranged on the memory cell arrays constituting the two sub-blocks, the memory cell blocks are separated along the columns of the memory cells, and the column selection lines and data lines and the sub-blocks are also spaced along the column of memory cells;

at least one column decoder, located at the first terminal of each column of memory cells, and connected to the column selection line;

a plurality of row decoders located at the first end of each row of memory cells, the word lines extending along the memory cells and connected to the word lines, each of the row decoders being provided to a block of memory cells ;

a plurality of DQ buffers located at end 2 of each row of memory cells, each of said DQ buffers serving a block of memory cells; and

A cell array controller, located at the first end of each row of memory cells, for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip for receiving multi-bit data from an external device and outputting multi-bit data to an external device,

the data bus provided to the plurality of memory cells extends parallel to the columns of the memory cells for transferring multi-bit data between the plurality of memory cells and the data input-output area,

a CPU chip generating said clock signal,

an I/O bus connected between the memory chip and the CPU chip.

In addition, the memory system of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of main memory units arranged on the memory chip are used to independently store and output multi-bit data synchronized with a clock signal, each consisting of a plurality of sub-memory units, each comprising

A plurality of memory cell blocks, each memory cell block has 2 sub-blocks, sense amplifiers, word lines, data lines and column select lines, each of the sub-blocks is composed of 1 memory cell array, the sense amplifiers are located in the Between the two sub-blocks, the word lines, data lines and column selection lines are arranged on the memory cell arrays constituting the two sub-blocks, the memory cell blocks are separated along the columns of the memory cells, and the column selection lines and data lines and the sub-blocks are also spaced along the column of memory cells;

at least one column decoder, located at the first terminal of each column of memory cells, and connected to the column selection line;

a plurality of row decoders located at the first end of each row of memory cells, the word lines extending along the memory cells and connected to the word lines, each of the row decoders being provided to a block of memory cells ;

a plurality of DQ buffers located at end 2 of each row of memory cells, each of said DQ buffers serving a block of memory cells; and

A cell array controller, located at the first end of each row of memory cells, for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip for receiving multi-bit data from an external device and outputting multi-bit data to an external device,

a plurality of data buses provided to at least two of said sub-blocks, extending parallel to the rows of said memory cells, for transferring multi-bit data between said sub-memory cells and said data input and output regions,

a CPU chip generating said clock signal,

an I/O bus connected between the memory chip and the CPU chip.

In addition, the memory system of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of memory units arranged on the memory chip are used to independently store and output multi-bit data synchronized with a clock signal, and each memory unit includes

A plurality of memory cell blocks, each memory cell block has 2 sub-blocks, sense amplifiers, word lines, data lines and column select lines, each of the sub-blocks is composed of 1 memory cell array, the sense amplifiers are located in the Between the two sub-blocks, the word lines, data lines and column selection lines are arranged on the memory cell arrays constituting the two sub-blocks, the memory cell blocks are separated along the columns of the memory cells, and the column selection lines and data lines and the sub-blocks are also spaced along the column of memory cells;

at least one column decoder, located at the first terminal of each column of memory cells, and connected to the column selection line;

a plurality of row decoders located at the first end of each row of memory cells, the word lines extending along the memory cells and connected to the word lines, each of the row decoders being provided to a block of memory cells ;

a plurality of DQ buffers located at end 2 of each row of memory cells; and

A cell array controller, located at the first end of each row of memory cells, for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip for receiving multi-bit data from an external device and outputting multi-bit data to an external device,

the data bus provided to the plurality of memory cells extends parallel to the columns of the memory cells for transferring multi-bit data between the plurality of memory cells and the data input-output area,

a CPU chip generating said clock signal,

an I/O bus connected between the memory chip and the CPU chip.

In addition, the memory system of the present invention includes

memory chips,

a plurality of memory cells disposed on the memory chip,

a data input and output area for multi-bit data input and output is provided on the memory chip, and

a data bus provided between the plurality of memory units and the data input and output area,

It is characterized in that,

A plurality of main memory units arranged on the memory chip are used to independently store and output multi-bit data synchronized with a clock signal, each consisting of a plurality of sub-memory units, each comprising

A plurality of memory cell blocks, each memory cell block has 2 sub-blocks, sense amplifiers, word lines, data lines and column select lines, each of the sub-blocks is composed of 1 memory cell array, the sense amplifiers are located in the Between the two sub-blocks, the word lines, data lines and column selection lines are arranged on the memory cell arrays constituting the two sub-blocks, the memory cell blocks are separated along the columns of the memory cells, and the column selection lines and data lines and the sub-blocks are also spaced along the column of memory cells;

at least one column decoder, located at the first terminal of each column of memory cells, and connected to the column selection line;

a plurality of row decoders located at the first end of each row of memory cells, the word lines extending along the memory cells and connected to the word lines, each of the row decoders being provided to a block of memory cells ;

a plurality of DQ buffers located at end 2 of each row of memory cells, each of said DQ buffers serving a block of memory cells; and

A cell array controller, located at the first end of each row of memory cells, for controlling the reading and writing of the multi-bit data,

a data input and output area provided on the memory chip for receiving multi-bit data from an external device and outputting multi-bit data to an external device,

a plurality of data buses provided to at least two of said sub-blocks, extending parallel to the rows of said memory cells, for transferring multi-bit data between said sub-memory cells and said data input and output regions,

Wherein, the input and output areas are separated along the rows of the memory units, the data bus is arranged on both sides of each of the input and output areas and separated along the columns of the memory units, and the sub memory units are arranged On both sides of each of the data buses,

a CPU chip generating said clock signal,

an I/O bus connected between the memory chip and the CPU chip.

Description of drawings

1 is a diagram showing a chip layout of a semiconductor memory as a first reference example of the present invention;

FIG. 2 is a diagram showing in detail a chip layout in the memory cell of FIG. 1;

3 is a diagram showing a chip layout of a semiconductor memory as a second reference example of the present invention;

FIG. 4 is a diagram showing in detail a chip layout in the memory cell of FIG. 3;

Fig. 5 is a diagram schematically representing the chip layout of Fig. 1;

FIG. 6 is a diagram showing a chip layout as a modified example of the first reference example in FIG. 1;

FIG. 7 is a diagram showing in detail the chip layout of FIG. 6;

8 is a diagram showing a chip layout as a modified example of the first reference example in FIG. 1;

Fig. 9 is a diagram showing in detail the chip layout of Fig. 8;

10 is a diagram showing a chip layout of a semiconductor memory as a first embodiment of the present invention;

Fig. 11 is a diagram showing in detail the chip layout of the memory cell of Fig. 10;

Fig. 12 is a diagram showing an example of the switch structure of Fig. 11;

FIG. 13 is a diagram showing a structural example of a column decoder;

FIG. 14 is a diagram showing a structural example of a memory cell selection circuit;

Fig. 15 is a diagram showing an example of the structure of a data input and output circuit;

Fig. 16 is a diagram showing the main part of the test circuit structure;

Fig. 17 is a diagram showing the test circuit structure of Fig. 16 in detail;

FIG. 18 is a diagram showing a configuration example of a switching circuit for testing;

FIG. 19 is a diagram showing signal waveforms in a test mode;

FIG. 20 is a diagram showing signal waveforms in a test mode;

FIG. 21 is a diagram showing a chip layout as a second embodiment of the present invention;

Fig. 22 is a diagram schematically showing the chip layout of Fig. 10;

FIG. 23 is a diagram showing a first modified example of the chip layout of FIG. 22;

Fig. 24 is a diagram showing in detail the chip layout of Fig. 23;

Fig. 25 is a diagram representing a first modified example of the chip layout of Fig. 21;

FIG. 26 is a diagram showing a second modified example of the chip layout of FIG. 22;

Fig. 27 is a diagram showing in detail the chip layout of Fig. 26;

FIG. 28 is a diagram showing a second modified example of the chip layout in FIG. 21;

FIG. 29 is a diagram showing a third modified example of the chip layout of FIG. 22;

Fig. 30 is a diagram showing in detail the chip layout of Fig. 29;

FIG. 31 is a diagram showing a third modified example of the chip layout of FIG. 21;

FIG. 32 is a diagram showing a fourth modified example of the chip layout of FIG. 22;

Fig. 33 is a diagram showing in detail the chip layout of Fig. 32;

FIG. 34 is a diagram showing a fourth modified example of the chip layout of FIG. 21;

Fig. 35 is a diagram showing the data transmission system of the present invention;

Figure 36 is a diagram representing a memory system of the present invention; and

FIG. 37 is a diagram showing a chip layout of a conventional semiconductor memory.

Detailed ways

The semiconductor memory, its test circuit, and data transfer system of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a chip layout (design) of a semiconductor memory as a first reference example of the present invention. FIG. 2 shows in detail the layout design in one memory cell of FIG. 1. FIG.

With this reference example, a 16-bit type (×16) semiconductor memory capable of simultaneously inputting and outputting 16-bit data will be described.

Four memory cells 11 - 0 to 11 - 3 are arranged on one memory chip 10 . Each memory unit 11-0 to 11-3 is formed with a memory cell array CAL, CAR, and a cell array controller CAC, and also formed with a row decoder RD, a column decoder CD0, CD1, and a DQ buffer (referred to as a memory Peripheral circuits such as registers of unit input and output parts) DQ, etc.

The memory cell array in one memory cell is divided into four middle memory blocks BLa, BLb, BLc, and BLd. And each storage block is divided into two small storage blocks CAL, CAR. Thus, the array of storage elements in one memory cell consists of 8 memory blocks.

Row decoders RD are respectively provided in each of the four middle memory blocks BLa, BLb, BLc, and BLd. The row decoder RD selects one of the two small memory blocks CAL, CAR according to the row address signal, and selects one row (word line 17) from a plurality of rows in the selected one memory block.

Two column decoders CD0 and CD1 are provided in one memory cell. The column decoders CD0 and CD1 respectively select one or more columns of the memory cell arrays of the four memory blocks BLa, BLb, BLc and BLd according to the column address signals.

That is, after a certain column selection line 15-0, 15-1 is selected by the column decoder CD0, CD1, the column selection switch 16 connected to the certain column selection line 15-0, 15-1 becomes In the conduction state, the data of one data line pair 14 or the data of multiple data line pairs 14 just pass through the sense amplifier SA and the data line pair (this data line will be symmetrically referred to as DQ line pair below to distinguish it from the data line pair 14) 18 is directed to the DQ buffer DQ.

In this reference example, two columns are selected for one column decoder. In this case, since there are two column decoders, 4-bit data is input and output from each of the middle memory blocks BLa, BLb, BLc, and BLd. That is to say, 16 bits (2 bytes) of data are input and output from one memory unit. The 16-bit data is exchanged between one of the data units 11 - 0 - 11 - 3 and the data input/output area 12 through the data bus 13 .

The fetch amplifier SA and the column selection switch 16 are arranged between the small blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

Row decoder RD and DQ buffer DQ are arranged to face each other with memory cell arrays CAL, CAR interposed therebetween. The column decoder CD0 is arranged on the first end side of the two ends of the arrangement direction of the four memory blocks BLa, BLb, BLc and BLd, that is, the column direction (the direction in which the data line pair or the column selection line extends), On the other hand, the column decoder CD1 is provided on the second end side of the two end portions.

The cell array controller CAC is arranged adjacent to the row decoder RD. The cell array controller CAC performs input and output operations of data in memory cells.

A memory cell selector SEL for selecting a memory cell is usually arranged immediately after the DQ buffer DQ.

Data is directed to DQ line pair 18 after passing through data line pair 14 , sense amplifier SA and column select switch 16 . DQ line pairs 18 are arranged between the small memory blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

Therefore, data moves in a direction perpendicular to the direction (column direction) in which the memory blocks BLa, BLb, BLc, and BLd of the four memory cell arrays are arranged, that is, in the row direction (the direction in which the word line extends) through the DQ line pair 18. After that, it is output from the memory unit through the DQ buffer DQ.

The data bus 13 common to the four memory units is provided between the memory units 11-0, 11-1 and the memory units 11-2, 11-3, and blocks BLa, BLb, BLc, and The direction in which BLd is arranged, that is, extends in the column direction. The data bus 13 is a data input and output path between the memory units 11 - 0 to 11 - 3 and the data input and output area 12 .

In this reference example, since a 16-bit type semiconductor memory is assumed, the data bus 13 is configured to simultaneously input and output 16-bit (2-byte) data.

In the data input/output area 12 , 16 input/output circuits (I/O) are formed in order to simultaneously perform input and output of 16-bit (2-byte) data.

The data input and output operations of the semiconductor memory described above are performed as follows.

First, the memory cell selector SEL selects one memory cell from the four memory cells 11-0 to 11-3. The access operation of the storage element is performed in accordance with the address signal in a selected one of the memory cells.

In the case of data output (reading), data of 2 ⁿ bits (for example, 16 bits (2 bytes)) is output from the selected one memory cell through the DQ line pair 18 . The ²ⁿ -bit data output from this memory cell is led to the data input-output area 12 through the data bus 13, and is output from the data input-output area 12 to the outside of the semiconductor memory (memory chip).

In the case of data input (writing), 2 ⁿ bits (for example, 16 bits (2 bytes)) of data are input to the selected one memory cell through the data input/output area 12 and the data bus 13 . The ^2n- bit data input to the selected one memory cell is stored into the memory elements of the memory cell array through the DQ line pair 18 and the sense amplifier SA.

The chip layout design of the above-mentioned semiconductor memory has the following disadvantages.

First, the data bus 13 shared by the four memory units 11-0˜11-3 is arranged through the middle of the memory chip 10 and extends along the column direction (the direction in which the data line pairs or column selection lines extend). In this case, the number of data bus lines 13 is increased in proportion to the bit type of the semiconductor memory, that is, the number of bits for simultaneous input and output operations, and the area of the data bus lines 13 is also increased.

For example, in the case of a 16-bit type (×16) semiconductor memory, the data bus 13 must be wired with the amount of data that can transmit 16-bit size. Similarly, in a 32-bit type (×32) semiconductor memory In this case, the data bus 13 must be wired in an amount capable of transferring 32-bit data.

Second, the DQ line pairs 18 arranged in each of the middle memory blocks BLa-BLd in the memory cell are provided only between the small memory blocks CAL, CAR of the memory cell array, and extend only in the row direction (word line extending direction). In this case, the number of DQ line pairs 18 increases in proportion to the number of bits output from one middle block, and the area of the DQ line pairs 18 increases.

For example, in the case of carrying out the input and output of 4-bit data in one middle storage block, the DQ line pair 18 must be able to transmit the wiring of the data quantity of 4-bit size. In the case of inputting and outputting special data, the DQ line pair 18 is required to be the number of wires capable of transmitting 8-bit data.

Thirdly, a row decoder RD is arranged at one of both ends in the row direction of the memory cell, and a DQ buffer DQ is arranged at the other end. In this case, the column decoder CD0 is provided at one of both ends in the column direction in the memory cell, and the column decoder CD1 is provided at the other of the two ends.

On the other hand, the cell array controller CAC is provided at one of the two ends in the row direction across the four memory blocks BLa, BLb, BLc, and BLd.

Therefore, since the row decoder RD and the cell array controller CAC are both arranged at one of the two end portions in the row direction, it is very difficult to arrange and wire components constituting the row decoder RD and the cell array controller CAC. complex.

FIG. 3 shows a chip layout of a semiconductor memory as a second reference example of the present invention. FIG. 4 details the layout design in one memory cell of FIG. 3. FIG.

Using this reference example, a 32-bit type (×32) semiconductor memory capable of simultaneously inputting and outputting 32-bit data will be described.

Four memory cells 11 - 0 to 11 - 3 are arranged on one memory chip 10 . Each memory unit 11-0 to 11-3 is formed with memory cell arrays CAL, CAR, and cell array controller CAC, and is also formed with row decoder RD, column decoder CD0, CD1, and DQ buffer (called Peripheral circuits such as the buffer) DQ of the input and output part of the memory unit.

The memory cell array in one memory cell is divided into four memory blocks BLa, BLb, BLc, and BLd. And each storage block is divided into two small storage blocks CAL, CAR. Therefore, the memory cell array in one memory cell consists of 8 memory blocks.

The row decoders RD are respectively provided in each of the four middle memory blocks BLa, BLb, BLc, and BLd. The row decoder RD selects one of the two memory blocks CAL, CAR according to the row address signal, and selects one row (word line 17) from a plurality of rows in the selected one memory block.

Four column decoders CD0 to CD3 are provided in one memory cell. The column decoders CD0-CD3 respectively select one or more columns of the memory cell arrays of the four middle memory blocks BLa, BLb, BLc, and BLd according to the column address signals.

That is, after a certain column selection line 15-0～15-3 is selected by the column decoder CD0-CD3, the column selection switch 16 connected to the certain column selection line 15-0～15-3 becomes a conductor. On state, the data of one data line pair 14 or the data of a plurality of data line pairs 14 pass through the sense amplifier SA and the data pair line (hereinafter this data line pair is referred to as the DQ line pair to distinguish it from the data line pair 14) 18 is received It is sent to the DQ buffer DQ.

In this reference example, two columns are selected by one column decoder. In this case, since there are four column decoders, 8-bit data is input and output from each of the middle memory blocks BLa, BLb, BLc, and BLd. That is, 32 bits (4 bytes) of data are input and output by one memory cell. The 32-bit data is exchanged between one of the memory units 11 - 0 to 11 - 3 and the data input/output area 12 through the data bus 13 .

The sense amplifier SA and the column selection switch 16 are disposed between the small blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

The row decoder RD and the DQ buffer DQ are arranged to face each other with the memory cell arrays CAL and CAR sandwiched therebetween. The column decoder CD0 is arranged on one side of the two ends in the direction in which the four memory blocks BLa, BLb, BLc, and BLd are arranged, that is, in the column direction (the direction in which the data line pair or column selection line extends). , and the column decoder CD1 is provided at the other side of the two ends.

The cell array controller CAC is configured adjacent to the row decoder. The cell array controller CAC controls the input and output operations of data in the memory cells.

A memory cell selector SEL for selecting memory cells is usually arranged directly after the DQ buffer DQ.

Data is directed to main DQ line pair 18 after passing through data line pair 14 , sense amplifier SA and column select switch 16 . The DQ line pair 18 is provided between the small memory blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

Therefore, data moves in a direction perpendicular to the direction (column direction) in which the memory blocks BLa, BLb, BLc, and BLd of the four memory cell arrays are arranged (column direction), that is, the row direction (the direction in which the word line extends) through the DQ line pair 18. After that, it is output from the memory unit through the DQ buffer DQ.

The data bus 13 that 4 memory cells share is arranged between the memory cells 11-0, 11-1 and the memory cells 11-2, 11-3, and stores the blocks BLa, BLb, BLc, and BLd in the memory cell array. The arrangement direction, that is, extends in the column direction. The data bus 13 is a data input/output path between the memory cells 11 - 0 to 11 - 3 and the data input/output area 12 .

In this reference example, since a 32-bit type semiconductor memory is assumed, the data bus 13 is configured to simultaneously input and output 32-bit (4-byte) data.

In the data input/output area 12, 32 input/output circuits (I/O) are formed so as to simultaneously input and output 32-bit (4-byte) data.

The data input/output operation of the semiconductor memory described above is performed as follows.

First, one memory cell is selected from the four memory cells 11-0 to 11-3 by the memory cell selector SEL. In a selected memory cell, the access operation of the storage element is performed according to the address signal.

In the case of data output (reading), data of 2 ⁿ bits (for example, 32 bits (4 bytes)) is output from the selected one memory cell through the DQ line pair 18 . The ²ⁿ -bit data output from this memory cell is led to the data input/output area 12 via the data bus 13, and thus the data input/output area 12 is output to the outside of the semiconductor memory (memory chip).

In the case of data input (writing), 2 ⁿ bits (for example, 32 bits (4 bytes)) of data are input into the selected one memory cell through the data input and output area 12 and the data bus 13 . The ^2n- bit data input into the selected memory cell is stored into the storage elements of the memory cell array through the DQ line pair 18 and the sense amplifier SA.

In the chip layout of the semiconductor memory described above, there are the same disadvantages as those of the chip layout of the semiconductor memory of the first reference example shown in FIGS. 2 and 3 .

That is, first, the number of data bus lines 13 commonly provided in a plurality of memory cells is increased in proportion to the bit type of the semiconductor memory, that is, the number of bits performing simultaneous input and output operations, and the area of the data bus lines 13 is increased. big. Second, the number of DQ line pairs 18 in the memory cell is increased in proportion to the number of bits output from the middle memory block of each memory cell, and the area of the DQ line pair 18 is increased. Third, since the row decoder RD and the cell array controller CAC are both provided at one of both ends in the row direction, the arrangement and wiring of elements constituting the row decoder RD and the cell array controller CAC become Very complicated.

In addition, in this reference example, since two column decoders are respectively arranged at the two end portions in the column direction, the arrangement and wiring of elements constituting the column decoders CD0 to CD3 are complicated.

FIG. 5 schematically shows the positions of memory cells and the positions of data buses of the semiconductor memory of the first reference example shown in FIGS. 1 and 2 .

The area on the memory chip 10 is mainly occupied by memory cells 11 - 0 to 11 - 3 and a data input/output area (I/O) 12 . The data input/output area 12 is arranged adjacent to one of the four sides of the memory chip 10 , that is, one of the two sides in the column direction.

The memory cell array in the memory cell is composed of a plurality of small memory blocks arranged in the column direction, and one middle memory block is formed of two small memory blocks.

Word lines extending in the row direction and data lines and column selection lines extending in the column direction (the direction in which the small memory blocks are arranged) are arranged in each small memory block.

DQ line pairs 18 extend in the row direction between the two small memory blocks. There are only enough DQ line pairs 18 between two small memory blocks to transmit 4-bit data.

Data bus line 13 is provided between memory cells 11-0, 11-1 and memory cells 11-2, 11-3, and extends in the column direction. The data bus 13 is configured to transmit 16-bit (2-byte) data.

FIG. 6 shows a modified example of the chip layout of the semiconductor memory of the first reference example shown in FIGS. 1 and 2 . FIG. 7 shows in detail the chip layout design of the semiconductor memory of FIG. 6 .

Compared with the chip layout in Figure 1 and Figure 1, this chip layout is different in the following points.

First, one memory unit (main memory unit) is constituted by two sub memory units.

That is, the main memory unit 11-0 is composed of sub memory units 11-0-#0, 11-0-#1, and the main memory unit 11-1 is composed of memory units 11-1-#0, 11-1-#1 , the main memory unit 11-2 is composed of sub memory units 11-2-#0, 11-2-#1, and the main memory unit 11-3 is composed of sub memory units 11-3-#0, 11-3-#1.

The sub memory cells 11-0-#0, 11-0-#1 are simultaneously selected by the memory cell selection circuit. In the case where the sub memory cells 11-0-#0, 11-0-#1 are selected, the remaining sub memory cells are not selected. Similarly, for example, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the remaining sub-memory units are not selected.

Also, a group is constituted by four sub-memory units 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0, and four sub-memory units 11-0-#1 , 11-1-#1, 11-2-#1, and 11-3-#1 form a group.

That is to say, input and output of 8-bit data are performed simultaneously in a group of sub-memory units 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0, In a group of sub memory cells 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1, 8-bit data is simultaneously input and output.

Second, it is configured to perform input and output of 8-bit (1 byte) data in one sub-memory unit.

The layout design of the sub-memory unit is compared with the layout design of the memory unit in FIG. 1 and FIG. 2 , the difference is that there is only one column decoder CD. In the case of this example, since one sub-memory cell performs input and output of 8-bit data, only one column decoder CD is sufficient. However, the column decoder CD selects two columns similarly to the semiconductor memories of FIGS. 1 and 2, and stores 2-bit data in blocks BLa, BLb, BLc, and BLd in each of the memory cell arrays. input Output.

The layout of the memory cell arrays CAL, CAR, the row decoder RD, the DQ line pair 18 and the DQ buffer DQ in the sub-memory unit is almost the same as the layout in the memory unit of the semiconductor memory of FIG. 1 and FIG. 2 .

Third, the data input/output circuits (I/O) 12a, 12b are arranged elongatedly along the row direction in the middle of the memory chip 10, and the data bus 13a is arranged in the sub memory units 11-0-#0, 11-1-#0 , 11-2-#0, and 11-3-#0 are arranged on both sides of the data input and output circuit 12a, and the data bus 13b is in the sub-memory unit 11-0-#1, 11-1-# 1, 11-2-#1, and 11-3-#1 are provided on both sides of the data input and output 12b.

The data bus lines 13a, 13b each extend in the column direction between the sub-memory cells, and are connected to the data input/output circuits 12a, 12b at the center of the memory chip 10 . The data buses 13a, 13b are each configured to transmit 8-bit data.

In a semiconductor memory having such a chip layout, for example, when sub-memory cells 11-0-#0 and 11-0-#1 are selected, data passes between sub-memory cells 11-0-#0 and data input/output circuit 12a. The bus 13a transmits and receives 8-bit data, and the sub-memory unit 11-0-#1 and the data input/output circuit 12b transmit and receive 8-bit data through the data bus 13b. FIG. 8 shows a modified example of the chip layout of the semiconductor memory of the first reference example shown in FIGS. 1 and 2 . FIG. 9 shows in detail the chip layout of the semiconductor memory of FIG. 8 .

Compared with the chip layouts in Fig. 1 and Fig. 2, this chip layout has the following differences.

First, one memory unit (main memory unit) is constituted by two sub memory units.

That is, the main memory unit 11-0 is composed of sub memory units 11-0-#0, 11-0-#1, and the main memory unit 11-1 is composed of sub memory units 11-1-#0, 11-1-#1 The main memory unit 11-2 is composed of sub memory units 11-2-#0, 11-2-#1, and the main memory unit 11-3 is composed of sub memory units 11-3-#0, 11-3-#1.

The sub memory cells 11-0-#0, 11-0-#1 are simultaneously selected by the memory cell selection circuit. In the case where the sub-memory cells 11-0-#0, 11-0-#1 are selected, the remaining sub-memory cells are not selected. Similarly, for example, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the remaining sub-memory units are not selected.

And by 4 sub-memory units 11-0-#0, 11-1-#0, 11-2-#0, 11-3-#0 form a group, by 4 sub-memory units 11-0-#1, 11 -1-#1, 11-2-#1, and 11-3-#1 form a group.

That is to say, input and output of 8-bit data are performed simultaneously in a group of sub memory units 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0 8-bit data is simultaneously input and output in a group of sub memory cells 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1.

Second, one sub-memory unit is configured to input and output 8-bit (1-byte) data.

The layout of this memory cell is compared with the layout of the memory cells of FIG. 1 and FIG. 2, the difference is that there is only one column decoder CD. Since, in the case of this example, one sub-memory cell performs input and output of 8-bit data, only one column decoder CD is sufficient. However, the column decoder CD selects two columns as in the semiconductor memories of FIGS. 1 and 2 so that 2-bit data is stored in the memory blocks BLa, BLb, BLc, and BLd in each of the memory cell arrays. input Output.

The layout design of the memory cell arrays CAL, CAR, the row decoder RD, the DQ line pair 18 and the DQ buffer DQ in the memory unit is the same as that of the semiconductor memory in FIG. 1 and FIG. 2 .

The 3rd, the data bus 13a is arranged in the group of sub-memory unit 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0 extending in the column direction, the data bus 13b is arranged so as to extend in the column direction in groups of sub memory cells 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1.

That is, the data bus 13a is extended in the column direction from the data input/output circuit 12a provided at the end of the column direction between the sub-memory units, and the data bus 13b is extended from the data input-output circuit 12a provided at the end of the column direction between the sub-memory units. 12b extends in the column direction.

Each of the data buses 13a, 13b is configured so as to be able to transmit 8-bit data.

In a semiconductor memory with such a chip layout, for example, when the sub memory cells 11-0-#0 and 11-0-#1 are selected, the data input/output circuit 12 passes between the sub memory cells 11-0-#0 and the data input/output circuit 12. The data bus 13a transmits and receives 8-bit data, and the sub-memory unit 11-0-#1 and the data input/output circuit 12b transmits and receives 8-bit data through the data bus 13b.

FIG. 10 shows a chip layout design of a semiconductor memory as a first embodiment of the present invention. Figure 11 shows in detail the layout design in one memory cell of Figure 10.

In this embodiment, a 16-bit type (×16) semiconductor memory capable of simultaneously inputting and outputting 16-bit data will be described.

Four memory cells 11 - 0 to 11 - 3 are arranged on one memory chip 10 . Memory cell arrays CAL, CAR, and cell array controller CAC are formed in each of the memory cells 11-0 to 11-3, and row decoders RD, column decoders CD0, CD1, and DQ buffers (referred to as Peripheral circuits such as the buffer of the input and output part of the memory unit) DQ, etc.

The memory cell array in one memory cell is divided into four memory blocks BLa, BLb, BLc, and BLd. And each storage block is divided into two small storage blocks CAL, CAR. Thus, the memory cell array in one memory cell consists of 8 memory blocks.

Row decoders RD are individually provided in each of the four middle memory blocks BLa, BLb, BLc, and BLd. This row decoder RD selects one of the two small storage blocks CAL, CAR according to the row address signal, and selects one row (word line 17) from the multiple rows in the selected storage block.

The selection of a small memory block of the memory cell array is performed by applying a high voltage to either of the two word lines 19a, 19b. For example, when a high voltage is applied to the word line 19a, the switch 20a is turned on, and the small memory block CAL is selected. At this time, because a low voltage is applied to the word line 19b, the switch 20b is turned off, and the small memory block CAR is not selected.

Both column decoders CD0, CD1 are provided in one memory unit. Each of the column decoders CD0, CD1 selects one or more columns of the memory cell arrays of the four middle memory blocks BLa, BLb, BLc, and BLd according to the column address signals.

For example, when the column selection line 15 is selected by the column decoder CD1, the two column selection switches 16 connected to the column selection line 15 are turned on. Thereby, the data of 2 bits promptly is outputted to the data line pair (this data line is called local DQ line symmetrically below by the sense amplifier SA and the column selection switch 16 from the two data line pairs 14 connected to the two column selection switches 16 Yes, to distinguish it from the data line pair 14) 18a.

In this embodiment, one column decoder selects two rows. In this case, since there are two column decoders, 4-bit data is input and output from each of the memory blocks BLa, BLb, BLc, and BLd. That is to say, 16 bits (2 bytes) of data are input and output from one memory unit.

The sense amplifier SA and the column selection switch 16 are disposed between the small blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

The row decoder RD and the cell array controller CAC are arranged to face each other with the memory cell arrays CAL, CAR sandwiched therebetween. That is, the row decoders RD are arranged in the direction perpendicular to the direction in which the four memory blocks BLa, BLb, BLc, and BLd are arranged, that is, in the row direction (the direction in which the word lines 17, 19a, and 19b extend). on one side of the two ends, and the cell array controller CAC is arranged on the other side of the two ends.

The cell array controller CAC is used to control the input and output operations of data in the memory cells.

The column decoders CD0 and CD1 are arranged at one of the two ends of the arrangement direction of the four memory blocks BLa, BLb, BLc, and BLd, that is, the column direction (the direction in which the data line pair or column selection line extends). on the side.

The two column decoders CD0, CD1 are arranged in the row direction so as to equally divide the columns of the memory cell array each column decoder CD0, CD1 undertakes.

The DQ buffer DQ is provided on the other side of the two ends in the column direction (the direction in which the data line pair or column selection line extends). That is, the column decoders CD0 and CD1 and the DQ buffer DQ are arranged to face each other with the memory cell arrays CAL and CAR sandwiched therebetween.

A memory cell selector SEL for memory cell selection is usually arranged immediately after the DQ buffer DQ.

Data is directed to local DQ line pair 18a after passing through data line pair 14, sense amplifier SA and column select switch 16. The local DQ line pair 18a is disposed between the small memory blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

Thus, the local DQ line pair 18a extends in the row direction (the direction in which word lines extend).

The data line pair (hereinafter referred to as a global DQ line pair to distinguish it from the data line pair 14 ) 18b is arranged to extend in the column direction on the small memory blocks CAL and CAR of the memory cell array. The first end of the global DQ line pair 18b is connected to the local DQ line pair 18a through the switch 21, and the second end is connected to the DQ buffer DQ.

The on/off of the switch 21 is controlled by the control signal CON.

The data bus line 13 common to the four memory cells is provided between the memory cells 11-0, 11-2 and the memory cells 11-1, 11-3, and extends in the row direction. The data bus 13 serves as a data input/output path between the memory cells 11 - 0 to 11 - 3 and the data input/output area 12 .

In this embodiment, since a 16-bit type semiconductor memory is assumed, the data bus 13 is configured to simultaneously input and output 16-bit (2-byte) data.

The data input/output area 12 is provided on one side of both ends in the row direction of the memory chip 10 . In this data input/output area 12, 16 input/output circuits (I/O) are formed in order to simultaneously perform input and output of 16-bit (2-byte) data.

The data input/output operation of the semiconductor memory described above is performed as follows.

First, the memory cell selector SEL selects one memory cell from the four memory cells 11-0 to 11-3. In a selected memory cell, the access operation of the storage element is performed according to the address signal.

In the case of data output (reading), 2 ⁿ bits (for example, 16 bits (2 bytes)) of data are output from the selected memory cell through the local DQ line pair 18a and the global DQ line pair 18b. The 2 ⁿ -bit data output from this memory cell is led to the data input/output area 12 through the data bus 13, and output from the data input/output area 12 to the outside of the semiconductor memory (memory chip).

In the case of data input (writing), 2 ⁿ bits (for example, 16 bits (2 bytes)) of data are input to the selected one memory cell through the data input/output area 12 and the data bus 13 . The 2 ⁿ bits of data input to the selected memory cell are stored into the storage elements of the memory cell array through the local DQ line pair 18a, the global DQ line pair 18b and the sense amplifier SA.

The chip layout of the semiconductor memory described above has the following features.

First, the cell array controller CAC and the row decoder RD are disposed so as to face each other at end portions in the row direction with the memory cell arrays CAL and CAR sandwiched therebetween. On the other hand, column decoders CD0, CD1 and DQ buffer DQ are disposed so as to face each other at ends in the column direction with memory cell arrays CAL, CAR sandwiched therebetween.

That is, the cell array controller CAC, the row decoder RD, the column decoders CD0, CD1, and the DQ buffer DQ may be arranged adjacent to one side of any one of the memory cell arrays CAL, CAR.

Accordingly, arrangement, wiring, and the like of elements constituting the cell array controller CAC, the row decoder RD, the column decoders CD0, CD1, and the DQ buffer DQ can be easily performed.

Second, in the memory cell, the local DQ line pair 18a extending in the row direction and the global DQ line pair 18b extending in the column direction are provided so that data can be output from the end of the memory cell in the column direction.

That is, since the DQ buffer DQ can be provided at the end of the memory cell in the column direction, the first feature described above can be realized.

Moreover, as in this embodiment, even if the number of bits for input and output in one of the middle memory blocks of the memory cell array is 4 bits, the local DQ lines arranged between the small memory blocks CAL and CAR can be The pair 18a is set to 2 bits on the column decoder CD0 side and 2 bits on the column decoder CD1 side.

This is for arranging the column decoders CD0 and CD1 adjacent to the memory cell array in the row direction, so that input and output of data are performed at the ends of the memory cells in the column direction.

Accordingly, the area required for the local DQ line pair 18a can be reduced, specifically, the area required for arranging the DQ line pair can be reduced to half of that of the reference example shown in FIGS. 1 and 2 .

On the other hand, when the global DQ line pairs 18b are used to input and output 4-bit data in one middle memory block, it is necessary to have a number capable of transferring 16-bit data in one memory cell. Therefore, since the global DQ line pair 18b is set on the memory cell arrays CAL, CAR, it is not necessary to reset the area for configuring the global DQ line pair 18b.

Third, the data bus 13 is arranged between the memory units 11-0, 11-2 and the memory units 11-1, 11-3 to extend in the row direction. This is for disposing the DQ buffer DQ in the memory cell at one of the two ends in the column direction.

As a result, the number of wires constituting the data bus 13 can be reduced by planning the layout of the memory cells and data input/output circuits, and the area of the data bus 13 occupied on the memory chip 10 can be reduced.

FIG. 12 shows a structural example of switches 16 and 21 constituting the semiconductor memory of FIGS. 10 and 11 .

Column selection switch 16 is composed of N-channel MOS transistors N1 and N2. The gates of the MOS transistors N1, N2 are connected to the column selection line 15, one of the source-drain regions is connected to the sense amplifier SA, and the other of the source-drain regions is connected to the local DQ line pair 18a.

The switch 21 is composed of N-channel MOS transistors N3 and N4. The gates of the MOS transistors N3 and N4 are connected to the control line 22, one of the source-drain regions is connected to the local DQ line pair 18a, and the other of the source-drain regions is connected to the DQ buffer DQ.

FIG. 13 shows an example of the structure of a column decoder of the semiconductor memory of FIGS. 10 and 11 .

In this example, the column decoder CD0 will be described as an example.

Column address signals A0 to A10 are input to column decoder CD0. Column address signals A0～A7 use the level of the output signal of any one of the pre-decoders in the pre-decoder (NAND "NAND" circuit) 23-1, 23-2, ~ 23-N as "L (Low)", and the levels of the output signals of all other pre-decoders are taken as "H (High)". The column address signal A8-A10 regards the level of the output signal of any one of the decoders 24-1, 24-2, ~ 24-M as "L (low)", and all the others are decoded. The level of the output signal of the device is regarded as "H (high)".

The output signals of the pre-decoders 23-1, 23-2, 23-N are input to the storage blocks 25-1, 25-2, ~ 25-N, and the decoders 24-1, 24-2, ~ 24 The output signal of -M is input to all the memory blocks 25-1, 25-2, to 25-N.

In the NOR "or not" circuit 26-0, 26-1, ~ 26-7, the output signal of the input pre-decoder 23-1, 23-2, ~ 23-N and the decoder 24-1, 24 -2, ~24-M output signal.

For example, when the level of the signal output from the pre-decoder 23-1 is "L" and the level of the output signal of the decoder 24-1 is "L", only the output of the NOR circuit 26-0 The level of the signal becomes "H", and the levels of output signals of all other NOR circuits become "L".

The output signals of the NOR circuits 26-0, 26-1, and 26-7 are input to the lock through the transmission gates 27-0, 27-1, and 27-7 while the level of the control signal L is "H". Storage circuits 28-0, 28-1, ~ 28-7.

The output signals of the latch circuits 28-0, 28-1, and 28-7 pass through the AND circuits 29-0, 29-1, and 29-7 while the level of the control signal T is "H". is applied to column select line 15.

For example, when the output signal level of the preset decoder 23-1 is "L" and the output signal level of the decoder 24-1 is "L", only one of the column selection lines 15 The level of CSL0 becomes "H", and the levels of all other column selection lines become "L". The column selection switch connected to the "H" level column selection line is turned on.

BW is a block write signal. The level of the block write signal BW is "L" in the normal mode, and becomes "H" in the block write mode. That is, in the memory block writing mode, the levels of the output signals of all decoders 24-1, 24-2, to 24-M are "L" regardless of column address signals A8-A10.

Therefore, for example, when the output signal level of the predecoder 23-1 is "L", all the levels of the eight column selection lines CSL0 to CSL7 controlled by the memory block 25-1 become "H". The column selection switch connected to the "H" level column selection line is turned on.

In this way, data is written in units of memory blocks.

FIG. 14 shows an example of the configuration of the memory cell selection circuit SEL of the semiconductor memory of FIGS. 10 and 11 .

The memory cell selection circuit SEL is composed of transfer gates T01 , T02 , T11 , T12 , T21 , T22 , T31 , and T32 connected between the DQ buffer DQ and the data bus 13 . The transmission gates T01, T02, T11, T12, T21, T22, T31, and T32 are constituted by N-channel MOS transistors and P-channel MOS transistors.

In the memory cell 11-0, the memory cell selection signals BNK0, /BLK0 are input to the memory cell selection circuit SEL. That is, the memory cell selection signal BNK0 is input to the gates of the N-channel MOS transistors constituting the transfer gates T01 and T02, and the memory cell selection signal /BNK0 is input to the gates of the P-channel MOS transistors constituting the transfer gates T01 and T02.

Similarly, in the memory cell 11-1, the memory cell selection signals BNK1, /BLK1 are input to the memory cell selection circuit SEL, and in the memory cell 11-2, the memory cell selection signals BNK2, /BLK2 are input to the memory cell selection circuit. SEL, and in the memory cell 11-3, memory cell selection signals BNK3, /BLK3 are input to the memory cell selection circuit SEL.

When any one of the memory cell selection signals BNK0-BNK3 becomes "H", the remaining levels become "L".

For example, when memory cell 11-0 is selected, the level of memory cell selection signal BNK0 becomes "H", and the levels of memory cell selection signals BNK1, BNK2, and BNK3 all become "L". At this time, only the DQ register DQ of the memory unit 11 - 0 is connected to the data bus 13 , and the DQ registers DQ of the memory units 11 - 1 , 11 - 2 , and 11 - 3 are disconnected from the data bus 13 .

As a result, data transfer is only possible between the memory cell 11 - 0 and the data input/output circuit 12 .

FIG. 15 shows a configuration example of the data input/output circuit 12 of the semiconductor memory of FIGS. 10 and 11 .

In this example, one data input/output circuit that performs 1-bit data input/output will be described. That is, for example, in a 16-bit type (×16) semiconductor memory, 16 data input/output circuits are required in this example.

The data input and output circuit is mainly composed of a data bus read amplifier DBSAMP, a data bus write buffer DBWBF, an output latch circuit 30 , an output circuit 31 and an output buffer 32 .

The data bus write buffer DBWB F is used when data is written.

The control signal NW is input to the synchronous pulse inverter CI1, and the control signal WX is input to the synchronous pulse inverters CI2 and CI5. During data writing in the normal operation mode, the level of the control signal NW becomes "H", and the sync pulse inverter CI1 is activated. While the control signal WX is at "H" level, the input data (write data) RWDm (m is 0, 1... or 15) passes through the synchronous pulse inverter CI1, the latch circuit LA and the synchronous pulse inverter CI2 , CI5 are directed to data bus 13 . This data is input to the selected memory cell via the data bus 13 .

The control signal BW is input to the synchronous pulse inverter CI3. At the time of data writing in the memory block writing mode, the level of the control signal BW becomes "H", and the sync pulse inverter CI3 is activated. While the control signal WX is at "H" level, the color register data CRm (m is 0, 1...or 15) is transferred through the pulse synchronous inverter CI3, the latch circuit LA and the synchronous pulse inverters CI2 and CI5. Leads to data bus 13 . This data is input to the selected memory cell via the data bus 13 .

The color register data CRm is supplied from the color register. Data patterns to be simultaneously written into a plurality of storage elements in the memory cell write mode are stored in advance in the color register. A color register is generally provided in an image memory, and is used when simultaneously writing data of a predetermined format into a plurality of storage elements. The content (data format) of the color register is changed in the mode of changing the data of the color register.

The control signal TW is input to the synchronous pulse inverter CI4. When writing data in the test mode, the control signal TW becomes "H" level, and the sync pulse inverter CI4 is activated. While the control signal WX is at "H" level, the output signal of the "exclusive OR" circuit EX is guided to the data bus 13 through the synchronous pulse inverter CI4, the latch circuit LA and the synchronous pulse inverter circuits CI2 and CI5 . This data is input to the selected memory cell via the data bus 13 .

Color register data /CRm and data RWD0 are input to the exclusive OR circuit EX. That is, in this example, it is configured according to the data pattern used when the test pattern is obtained from the color register.

A test circuit used in the semiconductor memory device of this embodiment will be described later.

The data bus sense amplifier DBSAMP is used in data readout.

The data bus sense amplifier DBSAMP contains an N-channel operational amplifier SAN and a P-channel operational amplifier SAP. The data bus sense amplifier DBSAMP is activated when the activation signal RENBL is at "H" level, and is not activated when the activation signal RENBL is at "L" level.

When the activation signal RENBL is at "L" level, the synchronous pulse inverter CI6 is not activated, and the data bus sense amplifier DBSAMP is separated from the read/write data line RWD. The read/write data line RWD is both an output data (read data) path and an input data (write data) path.

The precharge transistor PR precharges the read/write data line RWD to "H" level before the output data RWDm (m is 0, 1, . . . or 15) is output to the read/write data line RWD.

When the output data RWD is output by the data bus sense amplifier DBSAMP, the output data RWDm is input to the output circuit through the output latch circuit 30 .

The output latch circuit 30 is reset by a reset signal /RS. The synchronization signal QST is input to the output circuit 31 . That is, the output data DQm (m is 0, 1 .

The NAND circuit 33 and the "exclusive OR" circuit 34 are part of the test circuit used in the test mode.

The output data of the output latch circuit 30 and the test signal ReDT are input into the NAND circuit 33 . In the test mode, the test signal ReDT is "H" level. The output signal of the NAND circuit 33 and the color register data /CRm are input to an exclusive OR circuit 34 . This "exclusive OR" circuit 34 outputs an output signal TRDm (m is 0, 1...or 15) indicating "yes" or "no" of the test result.

FIG. 16 shows the overall configuration of a test circuit employed in the semiconductor memory device of the present invention. In FIG. 16, the structural elements corresponding to the structural elements of the data input/output circuit of FIG. 15 are denoted by the same symbols as those used in FIG.

This test circuit assumes that a 32-bit type (×32) semiconductor memory is tested.

The test circuit of this embodiment is composed of a NAND circuit 33 , an exclusive OR circuit 34 , a conversion circuit 100 for testing, and an output circuit 200 for input.

In the test mode, the test signal ReDT becomes "H" level. An output signal TRDm (m is 0, 1 . . . or 15) of the exclusive OR circuit 34 is input to the switching circuit 100 for testing.

32-bit data representing a test result is input to the test conversion circuit 100 . The test conversion circuit 100 sequentially (serially) outputs the 32-bit data to the test output circuit 200 .

The test output circuit 200 is activated when the control signal TQST- becomes "H" level. At this time, the control signal QST is at "L" level, and the output circuit 31 used in the normal mode is deactivated.

Fig. 17 shows details of a test circuit used in the semiconductor memory of the present invention. In FIG. 17, the structural elements corresponding to the structural elements of the data input/output circuit of FIG. 15 are denoted by the same symbols as those in FIG.

This test circuit presupposes the test of a 32-bit type (×32) semiconductor memory.

In the color register 35, data (0, 1, 0...1) having a predetermined pattern are stored in advance. However, the content (pattern) of the color register 35 can be changed by inputting the control signal Z in the pattern change mode.

The data /CR0, /CR1, ~CR31 of the color register 35 and the input data RWD0 are input to the "exclusive OR" circuit EX. The level of the input data WD0 may be "L" or "H".

For example, when the input data RWD is "L" level, "H" data is input in cell array 0, "L" data is input in cell array 1, "H" data is input in cell array 2, and "H" data is input in cell array 31. The data to be entered in "L".

In the case that all cell arrays 0-31 are normal, the cell arrays 0, 1, 2...31 will output the data of "H", "L", "H"..."L" respectively.

In this case, all output signals TRDm of the exclusive OR circuit 34 become "L".

The output signal TRDm of the exclusive OR circuit 34 is output to the outside of the memory chip as a judgment signal DQ0 through the test mode conversion circuit 100 and the test mode output circuit 200 .

In the measurement mode switching circuit 100, the test result is judged to be OK (cell array is normal) or NG (cell array is abnormal). When the cell array is normal, since the output signals TRDm of the "exclusive OR" circuit 34 are all "L" level, that is, the output signal of "L" level is output by the test mode switching circuit 100, the test result is judged as OK.

On the other hand, when the cell array is abnormal, the level of the output signal TRDm of the "abnormal" circuit 34 receiving the output data of the abnormal cell array becomes "H". At this time, the output signal of the test mode switching circuit 100 becomes "H" level, and the test result is judged as NG.

When the test result is NG, check which cell array among cell arrays 0-32 is abnormal. This check can be performed by latching the output signal of the "exclusive OR" circuit 34 in the latch circuits LATCH0-31, and serially reading the latched data sequentially.

According to such a test circuit, the data of the color register 35 is applied to the test of the semiconductor memory, and when the test result is NG, a signal indicating that a memory element of a certain cell array is bad is serially output.

Therefore, with the test circuit of this embodiment, while the structure of the test circuit itself can be simplified, only one test contact piece (terminal) used only in the test is enough, and the memory chip can be reduced in size and expanded. cut costs.

FIG. 18 shows a configuration example of the test mode switching circuit 100 of FIG. 17 .

The "exclusive NOR" circuit 36 is a part for checking whether there is a problem in the cell arrays 0-31.

This "exclusive OR" circuit 36 is composed of "exclusive OR" circuits EX-OR0, EX-OR1, ~EX-OR30 and synchronous pulse inverter CI7.

Output signals TRD0 to TRD31 are input to exclusive OR circuits EX-OR0, EX-OR1, to EX-OR30. When all output signals TRD0 to TRD31 are at "L" level, the level of the output signal of "exclusive OR" circuit EX-OR30 becomes "L".

When the control signal /SRCH becomes "H" level, the sync pulse inverter CI7 is activated. At this time, an output signal ReDRD indicating the test result is output from the synchronous pulse inverter CI7.

When output signals TRD0 to TRD31 are all at "L" level, output signal ReDRD becomes "H" level. That is, a signal indicating that the test result is OK is output from the test output circuit.

When the level of at least one of the output signals TRD0 to TRD31 is "H", the output signal ReDRD becomes "L" level. That is, the test output circuit outputs a signal indicating that the test result is NG.

The switch circuit unit 37 is for specifying which cell array has a problem or a bad cell array when the measurement result is NG.

The switching circuit unit 17 is composed of transmission gates TG0 , TG1 to TG31 and a synchronous pulse inverter CI8 , and each of the transmission gates TG0 , TG1 to TG31 is composed of an N-channel MOS transistor and a P-channel MOS transistor. The off/on actions of the transmission gates TG0 , TG1 - TG31 are controlled by the sequence selector 38 .

Sequencer 38 is activated when control signal SRCH is at "H" level, and outputs control signals Q0, Q1 to Q31 in synchronization with clock signal CLK. One of the control signals Q0, Q1 to Q31 is at "H" level, and all the others are at "L" level. The "H" level control signal is sequentially (serially) converted from Q0 to Q31. That is, the data TRD0, TRD1 to TRD31 are sequentially (serially) output through the sync pulse inverter CI8.

Sync pulse inverter CI8 is activated when control signal SRCH is at "H" level.

19 and 20 show the operation of the semiconductor memory device of the present invention during the test.

Checking whether there is a problem in the semiconductor memory cell array is performed in the induction test mode. In the serial search test mode, a check is performed to specifically designate a problematic cell array among a plurality of cell arrays.

/RE determines when the row address signal is taken into the semiconductor memory. That is, the row address signal is taken into the semiconductor memory when /RE is at "L" level.

/CE determines the timing at which the column address signal is taken into the semiconductor memory. That is, when /CE is at "L" level, the column address signal is taken into the semiconductor memory.

The induction test mode can be executed, for example, by setting the test signal TEST to the "L" level when /CE is at the "L" level.

The serial search test mode can be executed, for example, by setting the test signal TEST to "H" level when /CE is at "L" level.

FIG. 21 shows a chip layout design of a semiconductor memory as a second embodiment of the present invention.

In this embodiment, a 32-bit type (×32) semiconductor memory capable of simultaneously inputting and outputting 32-bit data will be described.

Four memory cells 11 - 0 to 11 - 3 are arranged on one memory chip 10 . Memory cell arrays CAL, CAR, and cell array controller CAC are formed in each memory unit 10-0 to 11-3, and row decoders RD, column decoders CD0 to CD3, and DQ buffers (referred to as memory registers) are formed. Peripheral circuits such as registers of unit input and output parts) DQ, etc.

The memory cell array in one memory cell is divided into four middle memory blocks BLa, BLb, BLc, and BLd. And each storage block is divided into two small storage blocks CAL, CAR. Therefore, the memory cell array in one memory cell consists of 8 memory blocks.

Row decoders RD are respectively provided in each of the four middle memory blocks BLa, BLb, BLc, and BLd. The row decoder RD selects one of the two small memory blocks CAL, CAR according to the row address signal, and selects a row (word line) from a plurality of the selected memory blocks.

Four column decoders CD0 to CD3 are provided in one memory cell. The column decoders CD0-CD3 respectively select one or more columns of the memory cell arrays of the four middle memory blocks BLa, BLb, BLc, and BLd according to the column address signals.

For example, after the column selection line is selected by the column decoder CD0, the two column selection switches connected to the column selection line become the conduction state. Then output 2-bit data from the two data line pairs connected to the two column selection switches to the local DQ line pair 18a.

In this embodiment, one column decoder is configured to select two columns. In this case, since there are four column decoders, the memory blocks BLa, BLb, BLc, and BLd input and output data of 8 bits each. That is, 32 bits (4 bytes) of data are input and output from one memory cell.

Sense amplifiers and column selection switches are provided between the small blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

The row decoder RD and the cell array controller CAC are arranged to face each other with the memory cell arrays CAL, CAR sandwiched therebetween. That is, the row decoder RD is provided on one side of the two ends in the direction perpendicular to the direction in which the four memory blocks BLa, BLb, BLc, and BLd are arranged, that is, in the row direction (the direction in which the word lines extend). side, and the cell array controller CAC is set on the other side of the two ends.

The cell array controller CAC performs input and output operations of data in the memory cells.

The column decoders CD0-CD3 are arranged at one of the two ends in the direction in which the memory blocks BLa, BLb, BLc, and BLd are arranged, that is, in the column direction (the direction in which the data line pair or column selection line extends) among the four side.

The four column decoders CD0 to CD3 are arranged in the row direction so as to quarter the columns of the memory cell array each column decoder CD0 to CD3 is responsible for.

The DQ buffer DQ is provided on the other side of both ends in the column direction. That is, column decoders CD0 to CD3 and DQ buffer DQ are arranged to face each other with memory cell arrays CAL and CAR sandwiched therebetween.

Data is directed to the local DQ line pair 18a after passing through the data line pair, sense amplifier and column select switch. The local DQ line pair 18a is provided between the small memory blocks CAL, CAR of the memory cell array in the respective middle blocks BLa, BLb, BLc, and BLd of the memory cell array.

Accordingly, the local DQ line pair 18a is extended in the row direction (the direction in which the word lines are extended).

On the other hand, the global DQ line pair 18b is arranged to extend in the column direction on the small memory blocks CAL, CAR of the memory cell array. The first end of the global DQ line pair 18b is connected to the local DQ line pair 18a through a switch, and the second end is connected to the DQ buffer DQ.

The data bus 13 common to the four memory cells is provided between the memory cells 11-0, 11-2 and 11-1, 11-3, and extends in the row direction. The data bus 13 serves as a data input/output path between the memory units 11 - 0 to 11 - 3 and the data input/output area 12 .

In this embodiment, since a 32-bit type semiconductor memory is assumed, the data bus 13 is configured to simultaneously input and output 32-bit (4-byte) data.

The data input/output area 12 is provided on one side of two end portions in the row direction of the memory chip 10 . In the data input/output area 12, 32 input/output circuits (I/O) capable of simultaneously inputting and outputting 32-bit (4-byte) data are formed.

The data input/output operation of the semiconductor memory described above is performed as follows.

First, the memory cell selector selects one memory cell from the four memory cells 11-0 to 11-3. In a selected memory cell, an access operation of the memory cell is performed according to an address signal.

In the case of data output (read), 32 bits (4 bytes) of data are output from the selected one memory cell through the local DQ line pair 18a and the global DQ line pair 18b. The 32-bit data output from this memory cell is guided to the data input-output area 12 through the data bus 13, and output from the data input-output area 12 to the outside of the semiconductor memory (memory chip).

In the case of data input (writing), 32 bits (4 bytes) of data are input to the selected one memory cell through the data input and output area 12 and the data bus 13 . The 32-bit data input to a memory cell selected here is stored into the memory elements of the memory cell array through the local DQ line pair 18a, the global DQ line pair 18b and the sense amplifier.

The chip layout of the semiconductor memory described above has the following features.

First, the cell array controller CAC and the row decoder RD are disposed so as to face each other at end portions in the row direction with the memory cell arrays CAL and CAR sandwiched therebetween. On the other hand, column decoders CD0 to CD3 and DQ buffer DQ are disposed so as to face each other at end portions in the column direction with memory cell arrays CAL and CAR sandwiched therebetween.

That is, the cell array controller CAC, the row decoder RD, the column decoders CD0-CD3 and the DQ register DQ can be adjacently arranged on one side of any one of the memory cell arrays CAL, CAR.

Therefore, arrangement and wiring of elements constituting the cell array controller CAC, row decoder RD, column decoders CD0 to CD3, and DQ buffer DQ can be easily performed.

Second, a local DQ line pair 18a extending in the row direction and a global DQ line pair 18b extending in the column direction are provided in the memory cell so that data is input and output from the end of the memory cell in the column direction.

That is, since the DQ buffer DQ can be provided at the end of the memory cell in the column direction, the first feature described above can be realized.

Moreover, as in this embodiment, even if the input and output in one memory block of the memory cell array is 8 bits, the local DQ line pair 18a arranged between the small memory blocks CAL and CAR can be It is set to 2 bits on the column decoder CD0 side, and 2 bits each on the column decoders CD1 to CD3 sides similarly.

This is because the column decoders CD0 to CD3 are arranged adjacent to the memory cell array in the row direction, and data input and output are performed at the ends of the memory elements in the column direction.

The area necessary for the local DQ line pair 18a can thereby be reduced.

Furthermore, when the global DQ line pairs 18b perform input and output of 8-bit data in one middle memory block, there must be a number capable of transferring 32-bit data in one memory cell. Therefore, since the global DQ line pair 18b is provided on the memory cell arrays CAL, CAR, there is no need to reset the area required for configuring the global DQ line pair 18b.

Third, the data bus 13 is provided between the memory units 11-0, 11-2 and 11-1, 11-3 to extend along the row direction. This is for disposing the DQ buffer DQ in the memory cell at one of the two ends in the column direction.

As a result, the number of wires constituting the data bus 13 can be reduced by means of skill in arranging the memory cells and data input/output circuits, and the area occupied by the data bus 13 on the memory chip can be reduced.

FIG. 22 schematically shows the positions of memory cells and the positions of data buses of the semiconductor memory of the first embodiment shown in FIG. 10 .

The area on the memory chip 10 is mainly occupied by memory cells 11 - 0 to 11 - 3 and a data input/output area (I/O) 12 . The data input/output area 12 is arranged adjacent to one of the four sides of the memory chip 10 , that is, one of the two sides in the row direction.

The memory cell array in the memory cell is composed of a plurality of small memory blocks arranged in the column direction, and one middle memory block is formed of two small memory blocks.

Word lines extending in the row direction, data lines extending in the column direction, and column selection lines are arranged in each small memory block.

Local DQ line pairs 18a extend in the row direction between two small memory blocks. And the global DQ line pair 18b extends in the column direction on the memory cell array. The local DQ pair 18a and the global DQ pair 18b are interconnected by means of switches.

Data bus 13 is provided between memory cells 11-0, 11-2 and memory cells 11-1, 11-3, and extends in the row direction. The data bus 13 is configured to transmit 16-bit (2-byte) data.

FIG. 23 shows a first modified example of the semiconductor memory of FIGS. 10 and 22 .

This modified example is characterized in that the data input/output circuit (I/O) 12 is provided in the central part of the memory chip 10, and that the memory cells 11-0 to 11-3 and the data buses 13a and 13b are respectively provided in the data Both sides of the input and output circuit 12.

That is, the area on the memory chip 10 is mainly occupied by the memory cells 11 - 0 to 11 - 3 and the data input/output area (I/O) 12 . The data input/output area 12 is provided at the central portion of the memory chip 10 and extends in the column direction.

The memory cells 11 - 0 and 11 - 1 are provided on one side of the data input/output area 12 , and the memory cells 11 - 2 and 11 - 3 are provided on the other side of the data input/output area 12 .

The storage unit array of the memory unit is composed of a plurality of small storage blocks arranged in the column direction, and one storage block is formed of two small storage blocks. Word lines extending in the row direction, data lines and column selection lines extending in the column direction are arranged in each small memory block.

The local DQ line pair 18a extends long in the row direction between two small memory blocks. And the global DQ line pair 18b extends in the column direction on the memory cell array. The local DQ line pair 18a and the global DQ line pair 18b are connected to each other through switches.

The data bus line 13 a is provided between the memory cell 11 - 0 and the memory cell 11 - 1 , extends in the row direction, and is connected to the data input/output circuit 12 . Likewise, the data bus line 13 b is provided between the memory cell 11 - 2 and the memory cell 11 - 3 to extend in the row direction, and is connected to the data input/output circuit 12 . The data buses 13a, 13b are each configured to transmit 16-bit (2-byte) data.

FIG. 24 shows in detail the chip layout design of the semiconductor memory of FIG. 23 .

The layout in each memory cell is the same as the layout in each memory cell of the semiconductor memory of FIG. 10 .

FIG. 25 shows a first modified example of the semiconductor memory of FIG. 21 .

This modified example is characterized in that the data input/output circuit (I/O) is provided in the central part of the memory chip 10, and that the memory cells 11-0 to 11-3 and the data buses 13a and 13b are provided in the data input and output circuits respectively. This point on both sides of the output circuit 12.

That is, the area on the memory chip 10 is mainly occupied by the memory cells 11 - 0 - 11 - 3 and the data input/output area (I/O) 12 . The data input/output area 12 is provided at the central portion of the memory chip 10 and is elongated in the column direction.

The memory cells 11 - 0 and 11 - 1 are provided on one side of the data input/output area 12 , and the memory cells 11 - 2 and 11 - 3 are provided on the other side of the data input/output area 12 .

The memory cell array in the memory cell is composed of a plurality of small memory blocks arranged in the column direction, and two small memory blocks constitute one memory block. Word lines extending along the row direction, data lines and column selection lines extending along the column direction are respectively arranged in each small memory block.

Local DQ line pairs 18a extend in the row direction between two small memory blocks. And the global DQ line pair 18b extends in the column direction on the memory cell array. The local DQ line pair 18a and the global DQ line pair 18b are interconnected by switches.

The data bus line 13 a is provided to extend in the row direction between the memory element 11 - 0 and the memory element 11 - 1 , and is connected to the data input/output circuit 12 . Likewise, the data bus line 13 b is provided to extend in the row direction between the memory cell 11 - 2 and the memory cell 11 - 3 , and is connected to the data input/output circuit 12 . Each of the data buses 13a, 13b is configured to transmit 32-bit (4-byte) data.

The layout in each memory cell is the same as the layout in each memory cell of the semiconductor memory of FIG. 22 .

FIG. 26 shows a second modified example of the chip layout of the semiconductor memory device of the first embodiment shown in FIGS. 10 and 22 . FIG. 27 shows the chip layout of the semiconductor memory of FIG. 26 in detail.

This chip layout differs from the chip layouts of FIGS. 10 and 22 in the following points.

First, one memory unit (main memory unit) is composed of two sub memory units.

That is, main memory units 11-0, 11-1, 11-2, and 11-3 are composed of sub memory units 11-0-#0 and 11-0-#1, 11-1-#0, and 11-1, respectively. -#1, 11-2-#0 and 11-2-#1, and 11-3-#0 and 11-3-#1 are constituted.

The sub memory cells 11-0-#0, 11-0-#1 are simultaneously selected by the memory cell selection circuit. When the sub-memory units 11-0-#0 and 11-0-#1 are selected, the remaining memory units are not selected. Similarly, for example, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the remaining sub-memory units are not selected.

Also, four sub memory cells 11-0-#0, 11-0-#1, 11-1-#0, and 11-1-#1 constitute one group, and the memory cells of this group are connected to the data bus 13a. Equally, constitute a group with 4 sub-memory units 11-2-#0, 11-2-#1, 11-3-#0, and 11-3-#1, the memory unit of this group is connected to the data bus 13b.

Second, it is configured such that 8-bit (1-byte) data input and output are performed in one sub-memory unit.

The layout of the sub-memory cells differs from the layout of the memory cells in FIG. 10 in that there is only one column decoder CD. Because, in the case of this example, since 8-bit data is input and output in one sub-memory cell, only one column decoder CD is sufficient. However, the column decoder CD also selects two columns similarly to the semiconductor memory of FIG. 10, so that the input and output of 2-bit data are performed in each of the memory blocks BLa, BLb, BLc, and BLd in the memory cell array. .

The memory cell array CAL, CAR in the sub-memory unit, the row decoder RD, the local DQ line pair 18a, the layout of the global DQ line pair 18b and the DQ register DQ are all the same as the layout in the memory cell of the semiconductor memory of Fig. 10 same.

Third, the data input/output circuit (I/O) 12 is arranged in the central part of the memory chip 10 in a column direction, and the data bus 13a is commonly provided on the sub-memory unit 11 on the side of the data input/output circuit 12. In -0-#0, 11-0-#1, 11-1-#0, and 11-1-#1, the data bus 13b is commonly provided in the sub-memory unit on the other side of the data input-output circuit 12 11-2-#0, 11-2-#1, 11-3-#0, and 11-3-#1.

The data buses 13a, 13b each extend in the row direction between the sub-memory cells, and are connected to the data input/output circuit 12 at the center of the memory chip 10 . The data buses 13a, 13b are each configured to transmit 16-bit data.

In a semiconductor memory having such a chip layout, for example, when the sub-memory units 11-0-#0 and 11-0-#1 are selected, between the sub-memory unit 11-0-#0 and the data input/output circuit 12 8-bit data is exchanged between them via the data bus 13a, and 8-bit data is exchanged between the sub-memory units 11-0-#1 and the data input/output circuit 12 via the data bus 13a.

FIG. 28 shows a second modified example of the chip layout of the semiconductor memory device of the second embodiment shown in FIG. 21 .

This chip layout differs from the chip layout of FIG. 21 in the following points.

First, one memory unit (main memory unit) is composed of two sub memory units.

That is, main memory units 11-0, 11-1, 11-2, and 11-3 are composed of sub memory units 11-0-#0 and 11-0-#1, 11-1-#0, and 11-1, respectively. -#1, 11-2-#0 and 11-2-#1, and 11-3-#0 and 11-3-#1 are constituted.

The sub memory cells 11-0-#0, 11-0-#1 are simultaneously selected by the memory cell selection circuit. When the sub-memory cells 11-0-#0 and 11-0-#1 are selected, the remaining sub-memory cells are not selected. Similarly, for example, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the remaining sub-memory units are not selected.

Also, a group is constituted by four sub memory cells 11-0-#0, 11-0-#1, 11-1-#0, and 11-1-#1, and the memory cells of this group are connected to the data bus 13a. Likewise, a group is formed by 4 sub-memory units 11-2-#0, 11-2-#1, 11-3-#0, and 11-3-#1, and the memory units of this group are connected to the data bus 13 .

Second, it is configured such that input and output of 16-bit (2-byte) data are performed in one sub-memory unit.

The layout of the sub-memory cells differs from the layout of the memory cells in FIG. 21 in that there are two column decoders CD. That is, the layout of the sub-memory cells is the same as that of the memory of FIG. 10 .

Because, in the case of this example, since one sub-memory cell performs input and output of 16-bit data, two column decoders CD are sufficient. However, since the column decoder CD selects two columns similarly to the semiconductor memory in FIG. 21, 4-bit data is input and output to each of the memory blocks BLa, BLb, BLc, and BLd in the memory cell array.

The layout of the memory cell array CAL, CAR, the row decoder RD, the local DQ line pair 18a, the global DQ line pair 18b and the DQ register DQ in the sub-memory unit is all the same as the layout in the memory unit of the semiconductor memory of Fig. 11 .

The 3rd, data input and output circuit (I/O) 12 is provided in the central part of memory chip 10 and stretches along column direction, and data bus line 13a is commonly provided in sub-memory unit 11-0 on the side of data input and output circuit 12. -#0, 11-0-#1, 11-1-#0, and 11-1-#1, while the data bus 13b is shared in the sub-memory unit on the other side of the data input and output circuit 12 11-2-#0, 11-2-#1, 11-3-#0, and 11-3-#1.

Each of the data bus lines 13a, 13b extends in the row direction between the sub-memory cells, and is connected to the data input/output circuit 12 at the center of the memory chip 10 . The data buses 13a, 13b are configured to transmit 32-bit data each.

In a semiconductor memory with such a chip layout, for example, when sub-memory cells 11-0-#0 and 11-0-#1 are selected, there The transfer of 16-bit data is performed through the data bus 13a, and similarly, the transfer of 16-bit data is performed between the sub-memory unit 11-0-#1 and the data input/output circuit 12 through the data bus 13a.

FIG. 29 shows a third modified example of the chip layout design of the semiconductor memory of the first embodiment shown in FIGS. 10 and 22 . FIG. 30 shows in detail the chip layout design of the semiconductor memory of FIG. 29 .

This chip layout differs from the chip layouts of Figures 10 and 22 in the following points.

First, one memory unit (main memory unit) is composed of two sub memory units.

That is, main memory units 11-0, 11-1, 11-2, and 11-3 are respectively composed of sub memory units 11-0-#0 and 11-0-#1, 11-1-#0, and 11- 1-#1, 11-2-#0 and 11-2-#1, and 11-3-#0 and 11-3-#1 constitute.

The sub memory cells 11-0-#0, 11-0-#1 are simultaneously selected by the memory cell selector. In the case where the sub-memory cells 11-0-#0, 11-0-#1 are selected, the remaining sub-memory cells are not selected. Similarly, for example, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the remaining sub-memory units are not selected.

And by 4 sub-memory units 11-0-#0, 11-1-#0, 11-2-#0 and 11-3-#0 form a group, the memory unit of this group passes data bus 13a, 13b It is connected to the data input and output circuit 12a. Similarly, 4 sub-memory units 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1 form a group, and the memory units of this group pass the data summary 13c, 13d It is connected to the data input and output circuit 12b.

Second, it is configured to input and output 8-bit (1-byte) data in one sub-memory unit.

The layout of the sub-memory cells differs from the layout of the memory cells in FIG. 10 in that it has only one column decoder. In the case of this example, since 8-bit data is input and output in one sub-memory cell, only one column decoder CD is sufficient. However, the column decoder CD selects two columns similarly to the semiconductor memory in FIG. 10, so that 2-bit data is input and output to each of the memory blocks BLa, BLb, BLc, and BLd in the memory cell array.

The layout of the storage cell array CAL, CAR in the sub-memory unit, the row decoder RD, the local DQ line pair 18a, the global DQ line pair 18b and the DQ register DQ is almost the same as that in the memory unit of the semiconductor memory of Fig. 10 The layout is the same.

Third, data input and output circuits (I/O) 12a, 12b are arranged on the memory chip 10 and extend along the column direction, data 13a, 13b are arranged on both sides of the data input and output circuit 12a, and data bus lines 13c, 13d are provided on both sides of the data input/output circuit 12b.

The data buses 13a, 13b, 13c, and 13d are each commonly provided at the sub memory units 11-0-#0 and 11-1-#0, 11-2-#0 and 11-3-#0, 11-0 -#1 with 11-1-#1, and 11-2-#1 with 11-3-#1.

The data bus lines 13a, 13b respectively extend along the row direction among the sub-memory units, and are connected to the data input and output circuits. Likewise, the data bus lines 13c, 13d respectively extend in the middle of the sub-memory cells in the row direction and are connected to the data input-output circuit 12b. Each of the data buses 13a to 13d is configured to transmit 8-bit data.

In a semiconductor memory with such a chip layout, for example, when the sub-memory units 11-0-#0 and 11-0-#1 are selected, the data bus 13a is used between the sub-memory units 11-0-#0 and the data input/output circuit 12a The transfer of 8-bit data is performed, and the transfer of 8-bit data is performed between the sub-memory unit 11-0-#1 and the data input and input circuit 12b through the data bus 13c.

That is, in a 16-bit type semiconductor memory, the data bus lines 13a to 13d may be formed of wirings capable of transmitting 8-bit data, thereby reducing the area of the data bus lines on the memory chip.

FIG. 31 shows a third modified example of the chip layout of the semiconductor memory of the second embodiment shown in FIG. 21 .

This chip layout differs from the chip layout of FIG. 21 in the following points.

First, one memory unit (main memory unit) is composed of two sub memory units.

That is, main memory units 11-0, 11-1, 11-2, and 11-3 are respectively composed of sub memory units 11-0-#0 and 11-0-#1, 11-1-#0 and 11- 1-#1, 11-2-#0 and 11-2-#1, and 11-3-#0 and 11-3-#1.

The sub memory cells 11-0-#0, 11-0-#1 are simultaneously selected by the memory cell selection circuit. When the sub-memory units 11-0-#0 and 11-0-#1 are selected, the remaining sub-memory units are not selected. Similarly, for example, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the rest of the sub-memory units will not be selected.

And form a group by 4 sub-memory units 11-0-#0, 11-1-#0, 11-2-#1, and 11-3-#0, the memory units of this group are connected by data bus 13a, 13b to the data input and output circuit 12a. Similarly, 4 sub-memory units 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1 form a group, and the memory units of this group are connected by data bus 13c, 13d to the data input and output circuit 12b.

Second, it is configured to input and output 16-bit (2-byte) data in one sub-memory unit.

The layout of the sub-memory cells differs from the layout of the memory cells in FIG. 21 in that there are two column decoders CD. That is, the layout of the sub-memory cells is the same as that of the memory cells of FIG. 10 .

In the case of this example, since 16-bit data is input and output in one sub-memory cell, two column decoders CD are sufficient. However, column decoder CD selects two columns similarly to the semiconductor memory of FIG. 21, so memory blocks BLa, BLb, BLc, and BLd in the memory cell array each input and output 4-bit data.

The memory cell array CAL, CAR in the sub-memory unit, the row decoder RD, the local DQ line pair 18a, the layout of the global DQ line pair 18b and the DQ register DQ are all the same as the layout in the memory cell of the semiconductor memory of Fig. 10 same.

Third, the data input and output circuits (I/O) 12a, 12b are configured to extend in the column direction on the memory chip 10, the data bus lines 13a, 13b are arranged on both sides of the data input and output circuit 12a, and the data bus lines 13c, 13d are arranged On both sides of the data input and output circuit 12b.

The data buses 13a, 13b, 13c and 13d are respectively provided in common in the sub memory units 11-0-#0 and 11-1-#0, 11-2-#0 and 11-3-#0, 11-0- #1 and 11-1-#1, and 11-2-#1 and 11-3-#1.

The data buses 13a, 13b each extend in the row direction between the sub-memory cells and are connected to the data input/output circuit 12a. Similarly, the data buses 13c, 13d each extend in the row direction between the sub-memory cells and are connected to the data input/output circuit 12b. Each of the data buses 13a to 13d is configured to transmit 16-bit data.

In the semiconductor memory of such a chip layout, for example, when the sub-memory units 11-0-#0 and 11-0-#1 are selected, data passes between the sub-memory units 11-0-#0 and the data input and output circuit 12a. The bus 13a transmits and receives 16-bit data, and the sub-memory unit 11-0-#1 and the data input/output circuit 12b transmits and receives 16-bit data through the data bus 13c.

That is to say, in a 32-bit type semiconductor memory, the data bus lines 13a to 13d may also be composed of wirings capable of transmitting 16-bit data, thereby reducing the area of the data bus lines on the memory chip.

FIG. 32 shows a fourth modified example of the chip layout of the semiconductor memory device of the first embodiment shown in FIGS. 10 and 22 . FIG. 33 shows the chip layout of the semiconductor memory of FIG. 32 in detail.

Compared with the chip layouts in Figure 10 and Figure 22, this chip layout differs in the following points.

First, one memory unit (main memory unit) is composed of two sub memory units.

That is, the main memory units 11-0, 11-1, 11-2, and 11-3 are each composed of the sub memory units 11-0-#0 and 11-0-#1, 11-1-#0 and 11- 1-#1, 11-2-#0 and 11-2-#1, and 11-3-#0 and 11-3-#1 constitute.

The sub-memory units 11-0-#1, 11-0-#1 are simultaneously selected by the memory unit selection circuit, and when the sub-memory units 11-0-#0, 11-0-#1 are selected, the rest of the sub-memory Units are not selected. Similarly, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the rest of the sub-memory units will not be selected.

And, 4 sub-memory units 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0 form a group, and the memory units of this group are all connected to Data input and output circuit 12 . Similarly, 4 sub-memory units 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1 form a group, and the memory units of this group are connected to the data input through the data bus 13b output circuit 12.

Second, it is configured to input and output 8-bit (1 byte) data in one sub-memory unit.

The layout of the sub-memory cells differs from the layout of the memory cells in FIG. 10 in that there is only one column decoder CD. Because in the case of this example, since 8-bit data is input and output in one sub-memory cell, one column decoder CD is sufficient. However, the column decoder CD selects two columns similarly to the semiconductor memory in FIG. 10, so that each of the memory blocks BLa, BLb, BLc, and BLd in the memory cell array performs 2-bit data input and output.

The layout of the storage cell array CAL, CAR, row decoder RD, local DQ line pair 18a, global DQ line pair 18b and DQ buffer DQ in the sub-memory unit is roughly the same as the layout in the memory unit of the semiconductor memory of FIG. 10 same.

Thirdly, a data input/output circuit (I/O) 12 is provided at the central portion of the memory chip 10 extending along the column direction, and data bus lines 13a, 13b are provided at both sides of the data I/O circuit 12 .

The data bus 13a is commonly provided on the sub memory units 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0, and the data bus 13b is commonly provided On sub memory units 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1.

Each of the data bus lines 13 a and 13 b extends in the row direction between the sub-memory cells, and is connected to the data input/output circuit 12 . Each of the data buses 13a, 13b is configured to transmit 8-bit data.

In a semiconductor memory with such a chip layout, for example, when the sub-memory units 11-0-#0 and 11-0-#1 are selected, the data bus 13a between the sub-memory units 11-0-#0 and the data input/output circuit 12 The transfer of 8-bit data is performed, and the transfer of 8-bit data is performed between the sub-memory unit 11-0-#1 and the data input/output circuit 12 through the data bus 13b.

That is, in a 16-bit type semiconductor memory, the data bus lines 13a and 13b can be constituted by the number of wirings capable of transferring 8-bit data, thereby reducing the area of the data bus lines on the memory chip.

FIG. 34 shows a fourth modified example of the chip layout design of the semiconductor memory device of the second embodiment shown in FIG. 21 .

This chip layout differs from the chip layout of Figure 21 in the following points.

First, one memory unit (main memory unit) is composed of two sub memory units.

That is, the main memory units 11-0, 11-1, 11-2, and 11-3 are each composed of the sub memory units 11-0-#0 and 11-0-#1, 11-1-#0 and 11- 1-#1, 11-2-#0 and 11-2-#1, and 11-3-#0 and 11-3-#1 constitute.

The sub memory cells 11-0-#0, 11-0-#1 are simultaneously selected by the memory cell selection circuit. When the sub memory cells 11-0-#0, 11-0-#1 are selected, the remaining sub memory cells are not selected. Similarly, for example, when the sub-memory units 11-1-#0 and 11-1-#1 are selected, the remaining memory units are not selected.

And, 4 sub-memory units 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0 form a group, and the memory units of this group are connected to the data input through the data bus 13a. output circuit 12. Similarly, 4 sub-memory units 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1 form a group, and the memory units of this group are connected to the data input through the data bus 13b output circuit 12.

Second, it is configured such that 16-bit (2-byte) data input and output are performed in one sub-memory unit.

The layout of the sub-memory cells differs from the layout of the memory cells in FIG. 21 in that there are two column decoders CD. That is, the layout of this sub-memory cell is the same as that of the memory cell of FIG. 10 .

In the case of this example, since one sub-memory cell performs input and output of 16-bit data, two column decoders CD are sufficient. However, the column decoder CD selects two columns similarly to the semiconductor memory in FIG. 21, and therefore performs input and output of 4-bit data in each of the memory blocks BLa, BLb, BLc, and BLd in the memory cell array.

The layout of memory cell arrays CAL, CAR, row decoder RD, local DQ line pair 18a, global DQ line pair 18b and DQ buffer DQ in the sub-memory unit is the same as that of the memory cell of the semiconductor memory in FIG. 10 .

Third, a data I/O circuit (I/O) 12 is provided at the center of the memory chip 10 so as to extend in the column direction, and data bus lines 13a, 13b are provided on both sides of the data I/O circuit 12 .

The data bus 13a is commonly provided on the sub memory units 11-0-#0, 11-1-#0, 11-2-#0, and 11-3-#0, and the data bus 13b is commonly provided on the sub memory units 11-0-#1, 11-1-#1, 11-2-#1, and 11-3-#1 on.

The data bus lines 13 a and 13 b extend in the row direction between the sub-memory cells and are connected to the data input/output circuit 12 . The data buses 13a, 13b are each configured to transmit 16-bit data.

In the semiconductor memory with such a chip layout, for example, when the sub-memory units 11-0-#0 and 11-0-#1 are selected, the sub-memory unit 11-0-#0 and the data input/output circuit 12 are connected through the data bus 13a. 16-bit data is exchanged, and 16-bit data is exchanged between the sub-memory units 11-0-#1 and the data input/output circuit 12 through the data bus 13b.

That is, in a 32-bit type semiconductor memory, the data bus lines 13a, 13b can also be constituted by the number of wires capable of transmitting 16-bit data, thereby reducing the area of the data bus lines on the memory chip.

Fig. 35 shows the data transfer system of the present invention.

Each of n (n is an even number) memory blocks BL0 to BLn is constituted by the same element. The memory blocks BL0 to BLn are arranged to extend in the column direction. Now take the storage block BL0 as an example to describe its composition.

Memory block BL0 has two switch arrays 41a, 41b arranged in the column direction. Each of the switch arrays 41a, 41b is constituted by a plurality of switches (MOS transistors) 46a, 46b arranged in a matrix.

The row decoder 42a is arranged adjacent to one of both ends of the switch array 41a in the row direction. The row decoder 42a is arranged adjacent to one of both ends of the switch array 41b in the row direction. The first ends of the word lines 44a and 44b are connected to the row decoders 41a and 42b, and the word lines 44a and 44b are also connected to control terminals (gates) of a plurality of switches 46a and 46b belonging to the same row.

The column decoder 43 is arranged adjacent to one of both ends of the switch array 41a in the column direction. The first end of the column selection line 49 is connected to the column decoder 43 .

Registers 47a, 47b and column selection column switches 48a, 48b are disposed between the two switch arrays 41a, 41b. The first ends of the data lines 45a, 45b are connected to the registers 47a, 47b and the column selection switches 48a, 48, and the data lines 45a, 45b are also connected to the output terminals (drains) of a plurality of switches 46a, 46b belonging to the same column. . Column selection line 49 is connected to column selection switches 48a, 48b.

Data is applied to the inputs (sources) of a plurality of switches 46a, 46b.

The local DQ line 50-0 is arranged between the two switch matrices 41a, 41b to extend in the row direction. Local DQ line 50-0 is connected to registers 47a, 47b and column select switches 48a, 48b.

The global DQ line 51-0 is arranged on the switch array of n memory blocks BL0-BLn to extend in the column direction. The first end of the global DQ line 51 - 0 is connected to the local DQ line 50 - 0 , and the second end thereof is connected to a data input/output circuit (I/O) 52 .

The data input/output circuit 52 is arranged adjacent to one of the two ends in the column direction of the n memory blocks BL0 to BLn.

The above-mentioned data transmission system is characterized in that, when n memory blocks BL0-BLn are arranged to extend in the column direction, for example, the data output by the memory blocks BL0-BLn pass through the global DQ lines 51-1 on the switch arrays 41a, 41b. 0 to 51-n are guided to the data input/output circuit 52 .

That is to say, the data output from the memory blocks BL0 to BLn is collected in the data input/output circuit 52 disposed adjacent to one of the two ends of the memory blocks BL0 to BLn in the column direction, and at the same time the data is input and output. The circuit 52 outputs to the outside of the LSI.

Fig. 36 shows the structure of the memory system of the present invention.

Here, an example of a memory system using the semiconductor memory of FIGS. 1 to 34 will be described.

10 is a memory chip whose structure is set to be the same as that of a selected one of the semiconductor memories described in FIGS. 1 to 34 .

In the memory chip 10 are formed a memory cell array 51 , a read/write circuit 52 , an input circuit 53 , an output circuit 54 , a synchronization circuit 55 , and a clock buffer 56 .

The CPU chip 58 outputs a clock signal CK. This clock signal CK is supplied to the memory chip 10 as an internal clock signal CLK. Within the memory chip 10, an internal clock signal CLK is supplied to the read/write circuit 52, causing the latter to operate in synchronization with CLK.

The deviation (distortion) between the clock signal CK and the internal clock signal CLK is removed by the synchronization circuit 55 . The synchronization circuit 55 outputs an internal clock signal CK' and supplies it to the input circuit 53 and the output circuit 54. The input circuit 53 and the output circuit 54 operate in synchronization with the inter-step clock signal CK'.

The I/O bus 57 connects the memory chip 10 and the CPU chip 58 . Data is transferred between the memory chip 10 and the CPU chip 58 through the I/O bus 57 .

As described above, according to the semiconductor memory device, its test system, and data transfer system of the present invention, the following effects can be obtained.

A plurality of memory cells are provided, and local DQ lines extending in the row direction provided between small memory blocks of the memory cell array and global DQ lines extending in the column direction provided on the memory cell array are provided in each memory cell. In addition, the input and output data are exchanged between the DQ buffer provided at the end of the memory cell in the column direction and the memory cell array through the local DQ line and the global DQ line.

Adopt such structure, because the cell array controller, row decoder, column decoder, DQ register in each memory cell can be arranged on the adjacent place with respective memory cell array one side, just may In the special type, clock synchronization type, and memory cell type semiconductor memory, the data transfer speed is increased without increasing the area of the chip.

Claims (66)

1. a semiconductor memory comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of memory cells on the described memory chip, be used for storing independently of each other and exporting the data of many bits, each memory cell comprises

A plurality of memory cell block, each memory cell block has 2 sub-pieces, reading magnifier, word line, data line and column selection line, each described sub-piece is made up of 1 memory cell array, described reading magnifier is between described 2 sub-pieces, described word line, data line and column selection line are arranged on the memory cell array that constitutes described 2 sub-pieces, described memory cell block separates along the row of memory cell, and described column selection line and data line and described sub-piece also separate along the row of memory cell;

At least one column decoder is positioned at the 1st end of every row of memory cell, and is connected to described column selection line;

A plurality of line decoders are positioned at the 1st end of every row of memory cell, and described word line extends along memory cell, and is connected to described word line, and each described line decoder offers a memory cell block;

A plurality of DQ buffers are positioned at the 2nd end of every row of memory cell; With

The cell array controller is positioned at the 1st end of every row of memory cell, is used to control the read and write of described many bits data,

Be arranged on the data input and output zone on the described memory chip, be used for receiving many bits data and many bits data being outputed to external unit from external unit,

Offer the described data bus of described a plurality of memory cells, the row that are parallel to described memory cell extend, and are used to transmit the many bits data between described a plurality of memory cell and the described data input and output zone.

2. semiconductor memory as claimed in claim 1 is characterized in that,

Each described memory cell comprises

A pair of local DQ line between described sub-piece, is parallel to the line direction extension of described memory cell and is connected to described reading magnifier,

A pair of overall DQ line is arranged on the described memory cell block, and the column direction that is parallel to memory cell extends and be connected to a pair of described local DQ line of described DQ buffer.

3. semiconductor memory as claimed in claim 2 is characterized in that, also comprises

Be arranged on the switch between described a pair of local DQ line and the described a pair of overall DQ line.

4. semiconductor memory as claimed in claim 3 is characterized in that,

Described each switch is made up of the N-channel MOS transistor.

5. semiconductor memory as claimed in claim 1 is characterized in that,

Described each memory cell has memory cell selection circuit at the 2nd end of every row of memory cell, described memory cell selects circuit that one of described memory cell is connected to described data bus, and remaining memory cell is not connected with described data bus, so that export and receive many bits data.

6. semiconductor memory as claimed in claim 1 is characterized in that,

Described a plurality of memory cell is 4 memory cells being arranged to 2 row, 2 row.

7. semiconductor memory as claimed in claim 1 is characterized in that, also comprises

Column select switch is between described sub-piece and be connected to described column selection line.

8. semiconductor memory as claimed in claim 1 is characterized in that,

Described data input and output zone is arranged on the 1st end of the every row of described memory cell.

9. semiconductor memory as claimed in claim 1 is characterized in that,

Described data input and output zone is rectangular, is arranged on the middle body of described memory chip, and is parallel to the row extension of memory cell.

10. semiconductor memory as claimed in claim 1 is characterized in that,

Described data input and output zone has a plurality of data imput output circuits, is used for receiving simultaneously and exporting the bit of described many bits data.

11. semiconductor memory as claimed in claim 1 is characterized in that,

Described data bus is arranged on the middle body of described memory chip, and the row that are parallel to described memory cell extend, the described memory cell of a part is positioned at the 1st side of described data bus, and remaining memory cell is positioned at the 2nd side of described data bus.

12. semiconductor memory as claimed in claim 1 is characterized in that,

Described column selection line is separated into mutual distinct group, and each described memory cell has a plurality of column decoders of the group that is used for controlling respectively the column selection line.

13. semiconductor memory as claimed in claim 1 is characterized in that,

Each described line decoder is selected in described 2 sub-pieces, then one in the described word line is extended on the described selecteed sub-piece.

14. semiconductor memory as claimed in claim 1 is characterized in that,

At least one described column decoder has the 1st function of selecting one of described column selection line and the 2nd function of selecting two described column selection lines at least, and the described the 1st and the 2nd function is changed mutually according to control signal.

15. a semiconductor memory comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of main storage units on the described memory chip, be used for storing independently of each other and exporting the data of many bits, each is made up of a plurality of quantum memories unit, and each comprises

A plurality of memory cell block, each memory cell block has 2 sub-pieces, reading magnifier, word line, data line and column selection line, each described sub-piece is made up of 1 memory cell array, described reading magnifier is between described 2 sub-pieces, described word line, data line and column selection line are arranged on the memory cell array that constitutes described 2 sub-pieces, described memory cell block separates along the row of memory cell, and described column selection line and data line and described sub-piece also separate along the row of memory cell;

At least one column decoder is positioned at the 1st end of every row of memory cell, and is connected to described column selection line;

A plurality of line decoders are positioned at the 1st end of every row of memory cell, and described word line extends along memory cell, and is connected to described word line, and each described line decoder offers a memory cell block;

A plurality of DQ buffers are positioned at the 2nd end of every row of memory cell; With

The cell array controller is positioned at the 1st end of every row of memory cell, is used to control the read and write of described many bits data,

Be arranged on the data input and output zone on the described memory chip, be used for receiving many bits data and many bits data being outputed to external unit from external unit,

At least offer a plurality of data buss of 2 described sub-pieces, the row that is parallel to described memory cell extends, and is used to transmit the many bits data between described quantum memory unit and the described data input and output zone.

16. semiconductor memory as claimed in claim 15 is characterized in that,

Each described quantum memory unit comprises

A pair of local DQ line between described sub-piece, is parallel to the line direction extension of described memory cell and is connected to described reading magnifier,

A pair of overall DQ line is arranged on the described memory cell block, and the column direction that is parallel to memory cell extends and be connected to a pair of described local DQ line of described DQ buffer.

17. semiconductor memory as claimed in claim 16 is characterized in that, also comprises

Be arranged on the switch between described a pair of local DQ line and the described a pair of overall DQ line.

18. semiconductor memory as claimed in claim 17 is characterized in that,

Described each switch is made up of the N-channel MOS transistor.

19. semiconductor memory as claimed in claim 16 is characterized in that,

Each described sub-piece has memory cell selection circuit at the 2nd end of every row of memory cell, at least 2 memory cells that described memory cell selects circuit will constitute whole main storage units are connected to described data bus, and remaining quantum memory unit is not connected with described data bus, so that export and receive many bits data.

20. semiconductor memory as claimed in claim 19 is characterized in that,

Between described selecteed quantum memory unit and described data input and output zone, by different data bus transmission data item.

21. semiconductor memory as claimed in claim 15 is characterized in that, also comprises

Column select switch is between described sub-piece and be connected to described column selection line.

22. semiconductor memory as claimed in claim 15 is characterized in that,

Each described main storage unit is made up of n sub-memory cell, and described data input and output zone has a plurality of data imput output circuits, is used for receiving simultaneously and exporting n times of bit of described many bits data.

23. semiconductor memory as claimed in claim 15 is characterized in that,

Described column selection line is separated into mutual distinct group, and each described memory cell has a plurality of column decoders of the group that is used for controlling respectively the column selection line.

24. semiconductor memory as claimed in claim 15 is characterized in that,

Each described line decoder is selected in described 2 sub-pieces, then one in the described word line is extended on the described selecteed sub-piece.

25. semiconductor memory as claimed in claim 15 is characterized in that,

Described data input and output zone is rectangular, is arranged on the middle body of described memory chip, and is parallel to the row extension of memory cell.

26. semiconductor memory as claimed in claim 25 is characterized in that,

Described data bus is arranged on the both sides in described data input and output zone, and the row that is parallel to described memory cell extends, and in the right corner in described data input and output zone.

27. semiconductor memory as claimed in claim 26 is characterized in that,

The row that described data bus is parallel to described memory cell extend, and described quantum memory unit is positioned at the both sides of described data bus.

28. semiconductor memory as claimed in claim 27 is characterized in that,

Described quantum memory unit is 8 memory cells being arranged to 4 row, 2 row.

29. semiconductor memory as claimed in claim 15 is characterized in that,

Described data input and output zone is positioned at the 1st end of every row of memory cell.

30. semiconductor memory as claimed in claim 29 is characterized in that,

The row that described data input and output zone is parallel to described memory cell extend, and the row that described data bus is parallel to described memory cell extends and in the 1st side in described data input and output zone.

31. semiconductor memory as claimed in claim 30 is characterized in that,

The row that described data bus is parallel to described memory cell extends, and described quantum memory unit is positioned at the both sides of described data bus.

32. semiconductor memory as claimed in claim 31 is characterized in that,

Described quantum memory unit is 8 memory cells being arranged to 4 row, 2 row.

33. a semiconductor memory comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of main storage units on the described memory chip, be used for storing independently of each other and exporting the data of many bits, each is made up of a plurality of quantum memories unit, and each comprises

A plurality of memory cell block, each memory cell block has 2 sub-pieces, reading magnifier, word line, data line and column selection line, each described sub-piece is made up of 1 memory cell array, described reading magnifier is between described 2 sub-pieces, described word line, data line and column selection line are arranged on the memory cell array that constitutes described 2 sub-pieces, described memory cell block separates along the row of memory cell, and described column selection line and data line and described sub-piece also separate along the row of memory cell;

At least one column decoder is positioned at the 1st end of every row of memory cell, and is connected to described column selection line;

A plurality of line decoders are positioned at the 1st end of every row of memory cell, and described word line extends along memory cell, and is connected to described word line, and each described line decoder offers a memory cell block;

A plurality of DQ buffers are positioned at the 2nd end of every row of memory cell, and each described DQ buffer offers 1 memory cell block; With

The cell array controller is positioned at the 1st end of every row of memory cell, is used to control the read and write of described many bits data,

Be arranged on the data input and output zone on the described memory chip, be used for receiving many bits data and many bits data being outputed to external unit from external unit,

At least offer a plurality of data buss of 2 described sub-pieces, the row that is parallel to described memory cell extends, and is used to transmit the many bits data between described quantum memory unit and the described data input and output zone,

Wherein, described input and output zone separates along the row of described memory cell, described data bus is arranged on the both sides in each described input and output zone and along the row of described memory cell separately, and described quantum memory unit is arranged on the both sides of each described data bus.

34. semiconductor memory as claimed in claim 33 is characterized in that,

Each described quantum memory unit comprises

A pair of local DQ line between described sub-piece, is parallel to the line direction extension of described memory cell and is connected to described reading magnifier,

A pair of overall DQ line is arranged on the described memory cell block, and the column direction that is parallel to memory cell extends and be connected to a pair of described local DQ line of described DQ buffer.

35. semiconductor memory as claimed in claim 34 is characterized in that, also comprises

Be arranged on the switch between described a pair of local DQ line and the described a pair of overall DQ line.

36. semiconductor memory as claimed in claim 35 is characterized in that,

Described each switch is made up of the N-channel MOS transistor.

37. semiconductor memory as claimed in claim 33 is characterized in that,

Each described sub-piece has memory cell selection circuit at the 2nd end of every row of memory cell, at least 2 memory cells that described memory cell selects circuit will constitute whole main storage units are connected to described data bus, and remaining quantum memory unit is not connected with described data bus, so that export and receive many bits data.

38. semiconductor memory as claimed in claim 37 is characterized in that,

Between described selecteed quantum memory unit and described data input and output zone, by different data bus transmission data item.

39. semiconductor memory as claimed in claim 33 is characterized in that, also comprises

Column select switch is between described sub-piece and be connected to described column selection line.

40. semiconductor memory as claimed in claim 33 is characterized in that,

Each described main storage unit is made up of n sub-memory cell, and described data input and output zone has a plurality of data imput output circuits, is used for receiving simultaneously and exporting the bit of described many bits data.

41. semiconductor memory as claimed in claim 33 is characterized in that,

Described column selection line is separated into mutual distinct group, and each described memory cell has a plurality of column decoders of the group that is used for controlling respectively the column selection line.

42. semiconductor memory as claimed in claim 33 is characterized in that,

Each described line decoder is selected in described 2 sub-pieces, then one in the described word line is extended on the described selecteed sub-piece.

43. semiconductor memory as claimed in claim 33 is characterized in that,

Described quantum memory unit is 8 memory cells being arranged to 4 row, 2 row.

44. semiconductor memory as claimed in claim 33 is characterized in that,

Each described main storage unit and clock signal synchronization action are so that store and export many bits data.

45. a semiconductor memory comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of memory cells on the described memory chip, be used for reading and writing independently of each other the data of many bits, each memory cell comprises

A plurality of memory cell block, each memory cell block comprises 2 sub-pieces, reading magnifier and DQ line, each described sub-piece comprises memory cell array, word line and data line, described word line extends on line direction, described data line extends on column direction, and described reading magnifier and DQ line are between described 2 sub-pieces, and described DQ line parallel extends in described word line, described DQ line is connected to described reading magnifier

The column selection line is arranged on described a plurality of memory cell block, and described column selection line parallel extends in described data line,

Column decoder is connected to described column selection line,

Line decoder is connected to described word line,

The DQ buffer is connected to described DQ line,

The memory cell selector switch is used for selecting of described a plurality of memory cells,

The cell array controller is used to control the read and write of described many bits data,

Be arranged on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell, be connected to described a plurality of memory cell, be parallel to described data line and extend, be used for transmitting the many bits data between of described a plurality of memory cells and the described data input and output zone.

46. semiconductor memory as claimed in claim 45 is characterized in that,

Described a plurality of memory cell is 2 memory cells.

47. semiconductor memory as claimed in claim 45 is characterized in that,

Described a plurality of memory cell is 4 memory cells.

48. semiconductor memory as claimed in claim 45 is characterized in that and comprises

Column select switch is between described 2 sub-pieces and be connected to described column selection line.

49. a semiconductor memory comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of memory cells on the described memory chip, be used to be independent of the data of the many bits of other memory cell ground read-write, each memory cell comprises

A plurality of memory cell block, each memory cell block comprises an antithetical phrase piece, corresponding to the reading magnifier and the DQ line of every pair of described sub-piece, each described sub-piece comprises memory cell array, word line and data line, described word line extends on line direction, described data line extends on column direction, and described reading magnifier and DQ line are between described 2 sub-pieces, and described DQ line parallel extends in described word line, described DQ line is connected to described reading magnifier

The column selection line is arranged on described a plurality of memory cell block, and described column selection line parallel extends in described data line,

Column decoder is connected to described column selection line,

Line decoder is connected to described word line,

The DQ buffer is connected to described DQ line,

The memory cell selector switch is used for selecting of described a plurality of memory cells,

The cell array controller is used to control the read and write of described many bits data,

Be arranged on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell, be connected to described a plurality of memory cell, be parallel to described data line and extend, be used for transmitting the many bits data between of described a plurality of memory cells and the described data input and output zone.

50. semiconductor memory as claimed in claim 49 is characterized in that,

Described a plurality of memory cell is 2 memory cells.

51. semiconductor memory as claimed in claim 49 is characterized in that,

Described a plurality of memory cell is 4 memory cells.

52. semiconductor memory as claimed in claim 49 is characterized in that and comprises

Column select switch is between described 2 sub-pieces and be connected to described column selection line.

53. a test circuit is used to test the semiconductor memory that comprises the memory cell array with the 1st and the 2nd memory cell block, it is characterized in that, comprises

Register is used to keep the 1st and the 2nd test data,

Data write circuit is written to the 1st test data the 1st memory cell in described the 1st memory cell block simultaneously and the 2nd test data is written to the 2nd memory cell in described the 2nd memory cell block,

The data reading circuit reads to be stored in the 1st read data and the 2nd read data that is stored in described the 2nd memory cell block in described the 1st memory cell block simultaneously,

Comparator circuit compares the 1st read data and the 1st test data and exports the 1st output data, and compares the 2nd read data and the 2nd test data and export the 2nd output data,

Decision-making circuit, determine according to the 1st and the 2nd output data whether the 1st and the 2nd memory cell is flawless, when at least 1 the described the 1st and the 2nd output data represent that at least 1 the described the 1st and the 2nd memory cell are defectiveness, the defective 1 bit data of described decision-making circuit output expression

Wherein, when at least 1 the described the 1st and the 2nd output data represented that at least 1 the described the 1st and the 2nd memory cell are defectiveness, described decision-making circuit output expression whether the 1st memory cell was that whether the 2nd memory cell is flawless the 2nd signal for flawless the 1st signal and expression.

54. test circuit as claimed in claim 53 is characterized in that, also comprises

Latch the 1st latch cicuit and the 2nd latch cicuit that latchs the 2nd signal of the 1st signal, wherein the 1st and the 2nd signal sequence ground is exported.

55. a test circuit is used to test the semiconductor memory that comprises the memory cell array with a plurality of memory cell block, it is characterized in that, comprises

Register is used to keep a plurality of test datas,

Data write circuit is written to test data the memory cell in the described memory cell block simultaneously,

The data reading circuit reads to be stored in a plurality of read datas in the described memory cell block simultaneously,

Comparator circuit, the comparative reading certificate is with test data and export a plurality of output datas,

Decision-making circuit, whether according to output data decision memory cell is flawless, when at least 1 described output data represented that at least 1 described memory cell is defectiveness, the described memory cell of described decision-making circuit output expression was defective 1 bit data

Wherein, when at least 1 described output data represented that at least 1 described memory cell is defectiveness, whether at least 1 memory cell was flawless signal in described decision-making circuit output expression.

56. test circuit as claimed in claim 55 is characterized in that, also comprises

The latch cicuit of latch signal, wherein said signal sequence ground is exported.

57. a data communication system,

Have a plurality of storage blocks of extending configuration at column direction,

Each storage block is by the switch arrays of forming by a plurality of switch of rectangular configuration, in abutting connection with the line decoder of the row of the described switch arrays of selection of ground, the end of described switch arrays line direction configuration, constitute in abutting connection with the local DQ line that extends along described line direction of ground, the column direction end configuration of described switch arrays and a plurality of switches that are connected described switch arrays and with the data line that data are directed to described local DQ line

It is characterized in that,

The 1st end that described column direction disposes with extending in described a plurality of storage blocks upper edge is connected to the overall DQ line of described local DQ line,

In abutting connection with the column decoder of the row of the described switch arrays of the described a plurality of storage blocks of selection of ground, the end configuration of the described column direction of described a plurality of storage blocks and

The data imput output circuit that carries out the data input and output that is connected with the 2nd end of described overall DQ line of ground, the described column direction end configuration of the described a plurality of storage blocks of adjacency.

58. data communication system as claimed in claim 57 is characterized in that,

Be provided with the column selection line that is arranged on the described switch arrays.

59. data communication system as claimed in claim 58 is characterized in that,

Be provided with in abutting connection with the column select switch of ground, described switch arrays end configuration, described column select switch is connected to described column selection line.

60. data communication system as claimed in claim 57 is characterized in that,

Be provided with in abutting connection with the register of ground, the end configuration of described switch arrays, described register is connected between described data line and the described local DQ line.

61. as data communication system as described in the claim 57, it is characterized in that,

Described data imput output circuit carries out the input and output of the data of many bits simultaneously.

62. an accumulator system comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that, comprise

Be provided with memory chip, be arranged on a plurality of main storage units that constitute by a plurality of quantum memories unit on the described memory chip, be arranged on the data input and output zone of carrying out the data input and output of many bits with clock synchronization ground on the described memory chip, constitute that the quantum memory unit more than two in whole quantum memories unit of described a plurality of main storage units is common to be provided with and to extend on line direction, a plurality of data buss as the data path of the quantum memory unit of described a plurality of main storage units and the described many bits between the described data input and output zone, generate the cpu chip of described clock signal, with with described memory chip and the interconnective I/O line of described cpu chip

Described a plurality of quantum memory chip comprises

Have by memory cell array constitute and be arranged on column direction two little storage blocks, be arranged on the reading magnifier between described two little storage blocks and be arranged on word line, data line and column selection on the described memory cell array, on column direction, dispose a plurality of in storage block

Side in two ends of described column direction disposes and connects at least one column decoder of described column selection line,

Side in two ends of described line direction configuration and in described storage block line decoder one, that be connected to described word line is set separately,

The DQ buffer of the opposing party in two ends of described column direction configuration and

The opposing party in two ends of described line direction configuration is also controlled the reading or the cell array controller of write operation of data of described many bits, and

Described a plurality of quantum memories unit separately by the data of carrying out described many bits independently of each other read or write operation constitutes like that.

63. an accumulator system comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of memory cells on the described memory chip, be used for storing independently of each other and the data of many bits that output and clock signal are synchronous, each memory cell comprises

A plurality of memory cell block, each memory cell block has 2 sub-pieces, reading magnifier, word line, data line and column selection line, each described sub-piece is made up of 1 memory cell array, described reading magnifier is between described 2 sub-pieces, described word line, data line and column selection line are arranged on the memory cell array that constitutes described 2 sub-pieces, described memory cell block separates along the row of memory cell, and described column selection line and data line and described sub-piece also separate along the row of memory cell;

At least one column decoder is positioned at the 1st end of every row of memory cell, and is connected to described column selection line;

A plurality of line decoders are positioned at the 1st end of every row of memory cell, and described word line extends along memory cell, and is connected to described word line, and each described line decoder offers a memory cell block;

A plurality of DQ buffers are positioned at the 2nd end of every row of memory cell, and each described DQ buffer offers 1 memory cell block; With

The cell array controller is positioned at the 1st end of every row of memory cell, is used to control the read and write of described many bits data,

Be arranged on the data input and output zone on the described memory chip, be used for receiving many bits data and many bits data being outputed to external unit from external unit,

Offer the described data bus of described a plurality of memory cells, the row that are parallel to described memory cell extend, and are used to transmit the many bits data between described a plurality of memory cell and the described data input and output zone,

Generate the cpu chip of described clock signal,

Be connected the I/O bus between described memory chip and the described cpu chip.

64. an accumulator system comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of main storage units on the described memory chip, be used for storing independently of each other and the data of many bits that output and clock signal are synchronous, each is made up of a plurality of quantum memories unit, and each comprises

A plurality of memory cell block, each memory cell block has 2 sub-pieces, reading magnifier, word line, data line and column selection line, each described sub-piece is made up of 1 memory cell array, described reading magnifier is between described 2 sub-pieces, described word line, data line and column selection line are arranged on the memory cell array that constitutes described 2 sub-pieces, described memory cell block separates along the row of memory cell, and described column selection line and data line and described sub-piece also separate along the row of memory cell;

At least one column decoder is positioned at the 1st end of every row of memory cell, and is connected to described column selection line;

A plurality of line decoders are positioned at the 1st end of every row of memory cell, and described word line extends along memory cell, and is connected to described word line, and each described line decoder offers a memory cell block;

A plurality of DQ buffers are positioned at the 2nd end of every row of memory cell, and each described DQ buffer offers 1 memory cell block; With

The cell array controller is positioned at the 1st end of every row of memory cell, is used to control the read and write of described many bits data,

Be arranged on the data input and output zone on the described memory chip, be used for receiving many bits data and many bits data being outputed to external unit from external unit,

At least offer a plurality of data buss of 2 described sub-pieces, the row that is parallel to described memory cell extends, and is used to transmit the many bits data between described quantum memory unit and the described data input and output zone,

Generate the cpu chip of described clock signal,

Be connected the I/O bus between described memory chip and the described cpu chip.

65. an accumulator system comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of memory cells on the described memory chip, be used for storing independently of each other and the data of many bits that output and clock signal are synchronous, each memory cell comprises

A plurality of memory cell block, each memory cell block has 2 sub-pieces, reading magnifier, word line, data line and column selection line, each described sub-piece is made up of 1 memory cell array, described reading magnifier is between described 2 sub-pieces, described word line, data line and column selection line are arranged on the memory cell array that constitutes described 2 sub-pieces, described memory cell block separates along the row of memory cell, and described column selection line and data line and described sub-piece also separate along the row of memory cell;

At least one column decoder is positioned at the 1st end of every row of memory cell, and is connected to described column selection line;

A plurality of line decoders are positioned at the 1st end of every row of memory cell, and described word line extends along memory cell, and is connected to described word line, and each described line decoder offers a memory cell block;

A plurality of DQ buffers are positioned at the 2nd end of every row of memory cell; With

The cell array controller is positioned at the 1st end of every row of memory cell, is used to control the read and write of described many bits data,

Be arranged on the data input and output zone on the described memory chip, be used for receiving many bits data and many bits data being outputed to external unit from external unit,

Offer the described data bus of described a plurality of memory cells, the row that are parallel to described memory cell extend, and are used to transmit the many bits data between described a plurality of memory cell and the described data input and output zone,

Generate the cpu chip of described clock signal,

Be connected the I/O bus between described memory chip and the described cpu chip.

66. an accumulator system comprises

Memory chip,

Be arranged on a plurality of memory cells on the described memory chip,

Be arranged on the data input and output of carrying out many bits on the described memory chip data input and output zone and

Be arranged on the data bus between described a plurality of memory cell and described data input and output zone,

It is characterized in that,

Be arranged on a plurality of main storage units on the described memory chip, be used for storing independently of each other and the data of many bits that output and clock signal are synchronous, each is made up of a plurality of quantum memories unit, and each comprises

A plurality of memory cell block, each memory cell block has 2 sub-pieces, reading magnifier, word line, data line and column selection line, each described sub-piece is made up of 1 memory cell array, described reading magnifier is between described 2 sub-pieces, described word line, data line and column selection line are arranged on the memory cell array that constitutes described 2 sub-pieces, described memory cell block separates along the row of memory cell, and described column selection line and data line and described sub-piece also separate along the row of memory cell;

At least one column decoder is positioned at the 1st end of every row of memory cell, and is connected to described column selection line;

A plurality of line decoders are positioned at the 1st end of every row of memory cell, and described word line extends along memory cell, and is connected to described word line, and each described line decoder offers a memory cell block;

A plurality of DQ buffers are positioned at the 2nd end of every row of memory cell, and each described DQ buffer offers 1 memory cell block; With

The cell array controller is positioned at the 1st end of every row of memory cell, is used to control the read and write of described many bits data,

Be arranged on the data input and output zone on the described memory chip, be used for receiving many bits data and many bits data being outputed to external unit from external unit,

At least offer a plurality of data buss of 2 described sub-pieces, the row that is parallel to described memory cell extends, and is used to transmit the many bits data between described quantum memory unit and the described data input and output zone,

Wherein, described input and output zone separates along the row of described memory cell, described data bus is arranged on the both sides in each described input and output zone and along the row of described memory cell separately, and described quantum memory unit is arranged on the both sides of each described data bus

Generate the cpu chip of described clock signal,

Be connected the I/O bus between described memory chip and the described cpu chip.

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