CN109903712A - Array substrate horizontal drive circuit and display panel - Google Patents
Array substrate horizontal drive circuit and display panel Download PDFInfo
- Publication number
- CN109903712A CN109903712A CN201910364398.XA CN201910364398A CN109903712A CN 109903712 A CN109903712 A CN 109903712A CN 201910364398 A CN201910364398 A CN 201910364398A CN 109903712 A CN109903712 A CN 109903712A
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- China
- Prior art keywords
- array substrate
- horizontal drive
- drive circuit
- substrate horizontal
- test cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000000758 substrate Substances 0.000 title claims abstract description 93
- 239000010409 thin film Substances 0.000 claims abstract description 29
- 239000010408 film Substances 0.000 claims abstract description 16
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000011800 void material Substances 0.000 claims 1
- 238000013461 design Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 238000003698 laser cutting Methods 0.000 description 2
- 238000000691 measurement method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a kind of array substrate horizontal drive circuit and display panels.The array substrate horizontal drive circuit includes: the multiple single level array substrate horizontal drive circuits and an at least virtual test cell being concatenated together, it is consistent with the quantity of the thin film transistor (TFT) in single level array substrate horizontal drive circuit, disposing way, position and size in the virtual test cell from domain；The source electrode of each thin film transistor (TFT), drain electrode and three end of grid are respectively equipped with corresponding via hole and connect with corresponding via hole in the virtual test cell, do not connect between each thin film transistor (TFT) in virtual test cell.The present invention also provides corresponding display panels.Array substrate horizontal drive circuit of the invention and display panel, which propose, a kind of puts scheme conducive to the virtual test cell of parsing；By putting virtual test cell in array substrate horizontal drive circuit area, using the electrical property of virtual test cell energy rapid survey respective films transistor, so that entire circuit be made to be conducive to parsing.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate horizontal drive circuits and display panel.
Background technique
Array substrate row drives (Gate Driver On Array, abbreviation GOA), that is, utilizes existing thin film transistor (TFT)
Array process in liquid crystal display in array substrate, realizes gate line scanning drive signal circuit production to grid line by line
The driving method of scanning.
When display exception occurs in panel, needs to parse panel using many-sided means, finds out abnormal reason,
But constantly becoming larger with panel size, it is difficult rapidly to find out the root of problem.In order to rapidly find out reason, judgement is
No is that array substrate horizontal drive circuit goes wrong, it usually needs surveys the thin film transistor (TFT) inside array substrate horizontal drive circuit
(TFT) electrically, but there are many thin film transistor (TFT) inside every level-one array substrate horizontal drive circuit, how to measure quickly and accurately
The electrical property of respective films transistor is a challenge always for traditional measurement method.
Fig. 1 is four clock signal array substrate horizontal drive circuit distributed architecture schematic diagram of a routine.On display panel, battle array
Region locating for column substrate horizontal-drive signal is properly termed as the area bus (Busline), area locating for array substrate horizontal drive circuit
Domain is properly termed as array substrate horizontal drive circuit area, and the region that bus area and array substrate horizontal drive circuit area form altogether can
Area is driven with referred to as array substrate row.Mainly arrangement is equipped with and is used for transmission array substrate horizontal drive circuit work when institute in bus area
The a plurality of signal wire of various signals is needed, such as shown in Fig. 1, each signal line transmits four clock signals CK1, CK2, CK3 respectively
And CK4, low-frequency clock signal LC1, LC2, initial signal STV2 and power supply low-voltage VSS.Array substrate horizontal drive circuit area
It is mainly disposed with array substrate horizontal drive circuits at different levels step by step, array substrate horizontal drive circuits at different levels export corresponding at different levels respectively
Scanning signal G (1), the effective display area of G (n) to panel G (2) ... scan lines at different levels.
Fig. 2 is a kind of existing single level array substrate horizontal drive circuit schematic diagram, depict by four thin film transistor (TFT) T11,
The single level array substrate horizontal drive circuit of T21, T31 and T41 composition, for exporting pair of scanning signal G (n) to effective display area
Answer the scan line of grade.For full HD (FHD) product, scan line shares 1080 grades, that is to say, that it at least needs 1080 grades
Array substrate horizontal drive circuit as shown in Figure 2.
Fig. 3 is corresponding version (layout) figure of the horizontal drive circuit of single level array substrate shown in Fig. 2, wherein with dotted line box form
Corresponding circuit function/the structure of each section in domain is generally identified, primary identity has gone out four thin film transistor (TFT)s in domain
T11, T21, T31 and T41, clock signal CK (n) input terminal, power supply low-voltage VSS input terminal, scanning signal output end G (n),
And bootstrap capacitor Cb (Fig. 2 does not show).When using traditional measurement method measure some thin film transistor (TFT) in Fig. 3 when, need to first by
Other thin film transistor (TFT)s being connected with the thin film transistor (TFT) are connect by laser cutting, then find out the thin-film transistor gate, source
The via hole of pole and the connection of three ends of drain electrode, measurement platform test the thin film transistor (TFT) via via hole, obtain the film crystal
The electrical information of pipe.Three ends of usual many thin film transistor (TFT)s are being all connected with via hole, in domain as shown in Figure 3, film
There is no all connection via hole, only one end to be connected to corresponding via hole 10 at three ends of transistor T11, this results in film crystal
Pipe T11 electrically can not accurately be obtained when grade.
Summary of the invention
Therefore, the purpose of the present invention is to provide a kind of array substrate horizontal drive circuit and display panels, are conducive to measurement battle array
The electrical property of thin film transistor (TFT) in column substrate horizontal drive circuit.
To achieve the above object, the present invention provides a kind of array substrate horizontal drive circuit include: be concatenated together it is more
A single level array substrate horizontal drive circuit and at least a virtual test cell, from domain, the virtual test cell
In it is consistent with the quantity of the thin film transistor (TFT) in single level array substrate horizontal drive circuit, disposing way, position and size；It is described
In virtual test cell the source electrode of each thin film transistor (TFT), drain electrode and three end of grid be respectively equipped with corresponding via hole and with it is corresponding
Via hole connection, do not connected between each thin film transistor (TFT) in the virtual test cell.
Wherein, the virtual test cell is located at rising in the multiple single level array substrate horizontal drive circuits being concatenated together
Near the single level array substrate horizontal drive circuit of beginning grade or end grade.
Wherein, the domain size one of the domain size of the virtual test cell and single level array substrate horizontal drive circuit
It causes.
Wherein, including two virtual test cells of the first virtual test cell and the second virtual test cell.
Wherein, first virtual test cell is located in the multiple single level array substrate horizontal drive circuits being concatenated together
Starting grade single level array substrate horizontal drive circuit near, second virtual test cell be located at be concatenated together it is multiple
Near the single level array substrate horizontal drive circuit of end grade in single level array substrate horizontal drive circuit.
Wherein comprising amorphous silicon film transistor.
Wherein comprising indium gallium zinc oxide thin film transistor (TFT).
The present invention also provides a kind of display panel, the array substrate horizontal drive circuit area of the display panel includes as before
State described in any item array substrate horizontal drive circuits.
To sum up, array substrate horizontal drive circuit of the invention and display panel propose a kind of virtual test conducive to parsing
Unit puts scheme；In original array substrate horizontal drive circuit design basis, by array substrate horizontal drive circuit area
Virtual test cell is put, using the electrical property of virtual test cell energy rapid survey respective films transistor, to make entire electricity
Road is conducive to parsing.
Detailed description of the invention
With reference to the accompanying drawing, by the way that detailed description of specific embodiments of the present invention, technical solution of the present invention will be made
And other beneficial effects are apparent.
In attached drawing,
Fig. 1 is four clock signal array substrate horizontal drive circuit distributed architecture schematic diagram of a routine；
Fig. 2 is a kind of existing single level array substrate horizontal drive circuit schematic diagram；
Fig. 3 is the domain of the horizontal drive circuit of single level array substrate shown in Fig. 2；
Fig. 4 is the domain of the virtual test cell of one preferred embodiment of array substrate horizontal drive circuit of the present invention.
Specific embodiment
It referring to fig. 4, is the virtual test cell (test of one preferred embodiment of array substrate horizontal drive circuit of the present invention
Key domain).It includes the multiple single level array substrate rows driving electricity being concatenated together that array substrate horizontal drive circuit of the present invention, which removes,
Road (as shown in Figure 1) further includes an at least virtual test cell, array substrate horizontal drive circuit of the present invention in display panel outside
Area devises virtual test cell, domain shown in Fig. 4 can be put into the starting grade of the array substrate horizontal drive circuit in Fig. 1 and/
Or the blank space near end grade, such environment can reflect the crystalline substance of the film in array substrate horizontal drive circuit area to greatest extent
Body pipe ring border.
Virtual test cell in the preferred embodiment is specially single level array substrate horizontal drive circuit according to Fig.2,
Design show that the size of the domain of virtual test cell shown in Fig. 4 can drive electricity with single level array substrate row shown in Fig. 3
The size of the domain on road is substantially uniform；Four film crystalline substances are identified generally with dotted line box form in domain shown in Fig. 4
Body pipe T11, T21, T31 and T41.
From Fig. 4 and domain shown in Fig. 3, in the virtual test cell with single level array substrate horizontal drive circuit
In the quantity of thin film transistor (TFT), disposing way, position and size it is consistent；Each film crystal in the virtual test cell
Source electrode, drain electrode and three end of grid of pipe T11, T21, T31 and T41 are respectively equipped with corresponding via hole and connect with corresponding via hole
It connects, is not connected between each thin film transistor (TFT) T11, T21, T31 and T41 in the virtual test cell.
When parsing display panel, judges whether it is that array substrate horizontal drive circuit goes wrong, need to study single level array
In substrate horizontal drive circuit when the electrical property of some thin film transistor (TFT), it is only necessary to find out its corresponding film in virtual test cell
Transistor can be measured.And do not have to need as existing design first by the film crystal in single level array substrate horizontal drive circuit
Manage coupled thin film transistor (TFT) laser cutting, then find out thirdly hold connection via hole, and usually many thin film transistor (TFT)s three
There is no all connect via hole at end.By taking the thin film transistor (TFT) T11 in Fig. 4 as an example, source electrode, drain electrode and three end of grid are respectively equipped with
Corresponding via hole 12,13 and 14 is simultaneously connected with corresponding via hole 12,13 and 14, it is only necessary to is put into measurement platform, be can be obtained thin
Film transistor T11 electrical property information.
First virtual test cell can be set to the multiple single level array substrate rows driving being concatenated together by the present invention
Near the single level array substrate horizontal drive circuit of starting grade in circuit, the second virtual test cell is set to and is concatenated together
Multiple single level array substrate horizontal drive circuits in end grade single level array substrate horizontal drive circuit near.The present invention is in original
In some array substrate row driving design basis, by each near the starting grade in array substrate horizontal drive circuit area and end grade
A virtual test cell is put, using the electrical property of virtual test cell energy rapid survey respective films transistor, passes through comparison etc.
Mode can accelerate parsing progress, so that the root of problem is found out, so that entire circuit be made to be conducive to parsing.
Array substrate horizontal drive circuit method of the invention is suitable for all amorphous silicons (a-si) and indium gallium zinc oxide
(IGZO) array substrate horizontal drive circuit.
Based on array substrate horizontal drive circuit of the invention, the present invention also provides corresponding display panel, the display
The array substrate horizontal drive circuit area of panel includes array substrate horizontal drive circuit above-mentioned.
To sum up, array substrate horizontal drive circuit of the invention and display panel propose a kind of virtual test conducive to parsing
Unit puts scheme；In original array substrate horizontal drive circuit design basis, by array substrate horizontal drive circuit area
Virtual test cell is put, using the electrical property of virtual test cell energy rapid survey respective films transistor, to make entire electricity
Road is conducive to parsing.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the appended right of the present invention
It is required that protection scope.
Claims (8)
1. a kind of array substrate horizontal drive circuit characterized by comprising the multiple single level array substrate rows being concatenated together drive
Dynamic circuit and an at least virtual test cell, from domain, in the virtual test cell with single level array substrate row
The quantity of thin film transistor (TFT) in driving circuit, disposing way, position and size are consistent；It is each in the virtual test cell
Source electrode, drain electrode and three end of grid of thin film transistor (TFT) are respectively equipped with corresponding via hole and connect with corresponding via hole, the void
It is not connected between each thin film transistor (TFT) in quasi- test cell.
2. array substrate horizontal drive circuit as described in claim 1, which is characterized in that the virtual test cell is located at cascade
The single level array substrate horizontal drive circuit of the starting grade or end grade in multiple single level array substrate horizontal drive circuits together
Near.
3. array substrate horizontal drive circuit as described in claim 1, which is characterized in that the domain of the virtual test cell is big
It is small in the same size with the domain of single level array substrate horizontal drive circuit.
4. array substrate horizontal drive circuit as described in claim 1, which is characterized in that including the first virtual test cell and
Two virtual test cells of virtual test cell two.
5. array substrate horizontal drive circuit as claimed in claim 4, which is characterized in that first virtual test cell is located at
Near the single level array substrate horizontal drive circuit for the starting grade in multiple single level array substrate horizontal drive circuits being concatenated together,
Second virtual test cell is located at the list of the end grade in the multiple single level array substrate horizontal drive circuits being concatenated together
Near grade array substrate horizontal drive circuit.
6. array substrate horizontal drive circuit as described in claim 1, which is characterized in that it includes amorphous silicon film transistor.
7. array substrate horizontal drive circuit as described in claim 1, which is characterized in that it includes that indium gallium zinc oxide film is brilliant
Body pipe.
8. a kind of display panel, which is characterized in that the array substrate horizontal drive circuit area of the display panel includes that right such as is wanted
Seek 1~7 described in any item array substrate horizontal drive circuits.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910364398.XA CN109903712A (en) | 2019-04-30 | 2019-04-30 | Array substrate horizontal drive circuit and display panel |
| PCT/CN2019/102478 WO2020220531A1 (en) | 2019-04-30 | 2019-08-26 | Array substrate row driving circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910364398.XA CN109903712A (en) | 2019-04-30 | 2019-04-30 | Array substrate horizontal drive circuit and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109903712A true CN109903712A (en) | 2019-06-18 |
Family
ID=66956537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910364398.XA Pending CN109903712A (en) | 2019-04-30 | 2019-04-30 | Array substrate horizontal drive circuit and display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109903712A (en) |
| WO (1) | WO2020220531A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111025632A (en) * | 2019-12-27 | 2020-04-17 | 宜昌南玻显示器件有限公司 | Simple design method of combined display system |
| CN111369929A (en) * | 2020-04-10 | 2020-07-03 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| WO2020220531A1 (en) * | 2019-04-30 | 2020-11-05 | 深圳市华星光电半导体显示技术有限公司 | Array substrate row driving circuit and display panel |
| WO2023029228A1 (en) * | 2021-09-01 | 2023-03-09 | 长鑫存储技术有限公司 | Layout of driving circuit, semiconductor structure and semiconductor memory |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2020220531A1 (en) | 2020-11-05 |
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Application publication date: 20190618 |