CN109901380A - Application circuit and method of redundancy design based on hardware arbitration in power supply processor - Google Patents
Application circuit and method of redundancy design based on hardware arbitration in power supply processor Download PDFInfo
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Abstract
The present invention discloses application circuit of the base based on the redundancy design of hardware mediation on power system processor, circuit mainly by signal interface board, master signal processing unit, backup signal processing unit, arbitration unit and display screen control board group at, master signal processing unit has independent CPU minimum system and its BIT detection circuit, and arbitration unit judges the working condition of master signal processing unit according to the BIT information from master signal processing unit；If judging, master signal processing unit is in effective status, keeps master signal processing unit as the signal processing unit uniquely to work；If judging, master signal processing unit is in failure state, and arbitration unit system carries out arbitrating and being sent to arbitration result respectively signal interface board and display screen control plate, using backup signal processing unit as the new signal processing unit uniquely to work.
Description
Technical field
The application circuit and method that the present invention relates to the redundancy designs based on hardware mediation on power system processor.
Background technique
Power system processor is the core equipment of automatic power distribution system, and the load supplying of property relationship to entire aircraft is excellent
Bad or even its reliability influences whether the execution of aerial mission.Currently, the performance and mission reliability of promotion power system processor refer to
Mark, generallys use redundancy design.Based on the remaining control of software arbitration because of the reasons such as its real-time is poor, reliability is low, it is easy to send out
It gives birth to the failures such as competition and fails, but the Redundancy Control System based on hardware mediation, then can occur to avoid similar problems, it is reliable
Property is also greatly enhanced.
Summary of the invention
The present invention provide a kind of novel application circuit based on the redundancy design of hardware mediation on power system processor and
Method.
In order to realize the purpose, technical scheme is as follows: based on the redundancy design of hardware mediation at power supply
Application circuit on reason machine, which is characterized in that circuit is mainly by signal interface board, master signal processing unit, backup signal
Unit, arbitration unit and display screen control board group are managed at master signal processing unit has independent CPU minimum system and its BIT
Detection circuit, master signal processing unit is connect with signal interface board and display screen control plate respectively, and backup signal processing unit
Equally there is independent CPU minimum system and its BIT detection circuit, backup signal processing unit respectively with signal interface board and aobvious
The connection of display screen control plate, arbitration unit judge master signal processing unit according to the BIT information from master signal processing unit
Working condition；If judging, master signal processing unit is in effective status, keeps master signal processing unit as unique
The signal processing unit of work；If judging, master signal processing unit is in failure state, and arbitration unit system is arbitrated simultaneously
Arbitration result is sent to signal interface board and display screen control plate respectively, is uniquely worked using backup signal processing unit as new
Signal processing unit.
Application method based on the redundancy design of hardware mediation on power system processor includes,
Step S1 provides above-mentioned application circuit；
Step S2, according to the BIT information for being two signal processing units, BIT detection circuit includes for the arbitration of arbitration unit
Peripheral circuit detection, the inspection of each voltage detecting, the temperature detection of each heat generating spot, software watchdog of functional unit minimum system
The parts such as survey, signal interface board pci interface communication detection, the detection of display screen control plate serial communication, synchronous signal processing unit
System other parts BIT information can be obtained from arbitration unit；
Step S3, arbitration unit make the award according to the respective BIT information that two signal processing units are sent, according to
FMEC analysis, selection seriously affect the BIT of cpu system task run to make arbitration judgement, and the crucial BIT of selection is as follows: soft
Part is effective: what house dog characterized is the software efficiency of master signal processing unit, breaks down when CPU feeds dog, indicates master control
The software of signal processing unit, which is run, to break down, and needs to be immediately switched to backup signal processing unit；Interface board PCI is effective:
The particularly critical channel of system with the input and output that the pci bus of interface board undertakes data, when master signal processing unit with
When the pci bus failure of interface board, master signal processing unit will be unable to acquisition and sending and receiving data, need to be immediately switched to back up
Signal processing unit；Screen control plate serial ports is effective, and transmission and the key of display data are undertaken in the RS422A serial communication with screen control plate
The transmitting of information is equally a critical passage, main when the RS422A communication failure of master signal processing unit and screen control plate
Control signal processing unit will be unable to receive key information and output display data, and it is single to need to be immediately switched to backup signal processing
Member；
Step S4, arbitration unit system arbitrate and arbitration result are sent to two signal processing units and signaling interface
Plate, display screen control plate.
In addition to it is described above present invention solves the technical problem that, constitute technical solution technical characteristic and by these
Except beneficial effect brought by the technical characteristic of technical solution, other technologies problem, technical solution that the present invention can solve
In include other technical characteristics and these technical characteristic bring beneficial effects, will be made in conjunction with attached drawing further details of
Explanation.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of one embodiment of the invention.
Fig. 2 is the structural schematic diagram of main control part in one embodiment of the invention.
Fig. 3 is the working principle diagram of one embodiment of the invention.
Fig. 4 is the flow chart of one embodiment of the invention.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.It needs to illustrate herein
It is the explanation of these embodiments to be used to help to understand the present invention, but do not constitute a limitation of the invention.In addition, below
Involved technical characteristic as long as they do not conflict with each other can phase in the described each embodiment of the present invention
Mutually combination.
For the mission reliability for improving power system processor, foundation system function, using the double redundancy based on hardware mediation
Design application.The signal processing of complete machine is divided into 3 control units: signal interface board, signal-processing board are (signal processing unit, standby
Part signal processing unit), display screen control plate.Machine system is as shown in Figure 1.
Signal processing unit two-node cluster hot backup Redundancy Design, there are two completely self-contained CPU minimum systems and its BIT to examine for tool
Slowdown monitoring circuit.Arbitration circuit judges the working condition of CPU element according to the BIT information of CPU element, when arbitration unit is according to BIT
Information judges to be arbitrated when master cpu element failure according to arbitration mechanism, and arbitration result is sent to signal interface board respectively and shows
Display screen control plate, using the output of current new master cpu as effective output.
Redundancy design application of the present invention based on hardware mediation, comprising the following steps:
Step 1: the arbitration foundation of arbitration unit is each signal processing unit BIT information.CPU element BIT circuit includes
Peripheral circuit detection, the inspection of each voltage detecting, the temperature detection of each heat generating spot, software watchdog of functional unit minimum system
The parts such as survey, signal interface board pci interface communication detection, the detection of display screen control plate serial communication, synchronous signal processing unit
System other parts BIT information can be obtained from arbitration unit.Signal-processing board BIT is illustrated in fig. 2 shown below.
Step 2: arbitration unit makes the award according to the respective unit B IT that two CPU elements are sent, according to FMEC points
Analysis, selection seriously affect the BIT of cpu system task run to make arbitration judgement, and the crucial BIT of selection is as follows:
◆ software is effective
What house dog characterized is the software efficiency of this CPU element, breaks down when CPU feeds dog, indicates the software of this CPU
Operation is broken down, and needs to be immediately switched to backup CPU element；
◆ interface board PCI is effective
The particularly critical channel of system with the input and output that the pci bus of interface board undertakes data, when this CPU element with
When the pci bus failure of interface board, this CPU element will be unable to acquisition and sending and receiving data, and it is mono- to need to be immediately switched to backup CPU
Member；
◆ screen control plate serial ports is effective
The transmission of display data and the transmitting of key information are undertaken in RS422A serial communication with screen control plate, are equally one
Critical passage, when this CPU element and screen control plate RS422A communication failure when, this CPU element will be unable to receive key information and
Output display data, need to be immediately switched to backup CPU element.
Arbitration principle is illustrated in fig. 3 shown below, wherein being sent to the arbitration result of two CPU and signal interface board, display screen control plate
It is a set of register in FPGA, is wired to different pins respectively inside FPGA, it is unique for being sent to the arbitration result of each unit
's.
Step 3: when meeting the failure therein occurred all the way, arbitration selection signal is generated, the switching of CPU is completed, is had
Body handover mechanism see the table below.Arbitration uses priority management method using BIT signal, and CPU software watchdog reset BIT is one
Grade, the BIT of PCI are second level, and the BIT of RS422A is three-level.When level-one BIT has a failure, then by another unit master
Control；When level-one BIT does not fail, according to second level BIT ruling, when second level BIT has a failure, then by another unit master
Control；When level-one BIT, second level BIT do not fail, according to three-level BIT ruling, when three-level BIT has a failure, then by other one
A unit master control.
Screen control plate, wherein 1 tunnel is backup arbitration result signal.Arbitration result exports the square wave that ` uses two kinds of frequencies:
10KHz and 20KHz.Wherein, 10KHz signal indicates that current master control is CPUA, and 20KHz signal indicates that current master control is CPUB, standby
Part arbitration result exports identical arbitrating signals, when main arbitration output result is invalid signals, then using the arbitration of redundancy backup
Export result.
Step 4: what the arbitration result of arbitration unit mainly influenced is the output of system, and the RS422 including interface board is defeated
Out, the output of discrete magnitude and the display of display screen control plate output.In order to avoid occurring cpu fault production when being output to half
Output data mistake caused by raw switching, can be using the output task of CPU as an independent task, and setting exports before exporting
Mark begin to output unit, output complement mark, output beginning flag and output complement mark preservation are set when exporting and completing
In the FPGA of output unit.When CPU arbitrary switch-over occurs, signal interface board and display screen control receive head after arbitration result
First judgement output complement mark then passes through interrupt notification if being not properly completed output (having beginning flag, no complement mark)
The currently active CPU re-executes the output operation of last time.System Safety output process is illustrated in fig. 4 shown below.
Step 5: the double redundancy design application based on hardware mediation terminates.
Embodiments of the present invention are only expressed above, and the description thereof is more specific and detailed, but and cannot therefore understand
For the limitation to patent of invention range.It should be pointed out that for those of ordinary skill in the art, not departing from this hair
Under the premise of bright design, various modifications and improvements can be made, and these are all within the scope of protection of the present invention.Therefore, this hair
The scope of protection shall be subject to the appended claims for bright patent.
Claims (2)
1. the application circuit based on the redundancy design of hardware mediation on power system processor, which is characterized in that circuit is mainly by believing
Number interface board, master signal processing unit, backup signal processing unit, arbitration unit and display screen control board group are at master signal
Processing unit have independent CPU minimum system and its BIT detection circuit, master signal processing unit respectively with signal interface board
And the connection of display screen control plate, and backup signal processing unit equally has independent CPU minimum system and its BIT detection circuit,
Backup signal processing unit is connect with signal interface board and display screen control plate respectively, and arbitration unit is handled according to from master signal
The BIT information of unit judges the working condition of master signal processing unit；If judging, master signal processing unit is in effective
State then keeps master signal processing unit as the signal processing unit uniquely to work；If judging master signal processing unit
In failure state, then arbitration unit system carries out arbitrating and being sent to arbitration result respectively signal interface board and display screen control plate,
Using backup signal processing unit as the new signal processing unit uniquely to work.
2. the application method based on the redundancy design of hardware mediation on power system processor, which is characterized in that include,
Step S1 provides application circuit described in claim 1；
Step S2, according to the BIT information for being two signal processing units, BIT detection circuit includes function for the arbitration of arbitration unit
The peripheral circuit detection of unit minimum system, the detection of each voltage detecting, the temperature detection of each heat generating spot, software watchdog,
Parts, the synchronous signal processing units such as signal interface board pci interface communication detection, the detection of display screen control plate serial communication can also be from
Arbitration unit obtains system other parts BIT information；
Step S3, arbitration unit make the award according to the respective BIT information that two signal processing units are sent, according to FMEC points
Analysis, selection seriously affect the BIT of cpu system task run to make arbitration judgement, and the crucial BIT of selection is as follows: software is effective:
What house dog characterized is the software efficiency of master signal processing unit, breaks down when CPU feeds dog, indicates master signal processing
The software of unit, which is run, to break down, and needs to be immediately switched to backup signal processing unit；Interface board PCI is effective: with interface board
Pci bus to undertake the input and output of data be the particularly critical channel of system, when master signal processing unit and interface board
When pci bus failure, master signal processing unit will be unable to acquisition and sending and receiving data, need to be immediately switched to backup signal processing
Unit；Screen control plate serial ports is effective, and the transmission of display data and the biography of key information are undertaken in the RS422A serial communication with screen control plate
It passs, is equally a critical passage, when the RS422A communication failure of master signal processing unit and screen control plate, at master signal
Reason unit will be unable to receive key information and output display data, need to be immediately switched to backup signal processing unit；
Step S4, arbitration unit system carry out arbitration and arbitration result are sent to two signal processing units and signal interface board, is shown
Display screen control plate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115903581A (en) * | 2022-10-26 | 2023-04-04 | 中国航空工业集团公司西安航空计算技术研究所 | Master-slave preemption switching method of dual-redundancy controller |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038574A (en) * | 2006-03-17 | 2007-09-19 | 上海奇码数字信息有限公司 | Bus arbitration device |
| JP2008146236A (en) * | 2006-12-07 | 2008-06-26 | Toshiba Corp | Redundant control device and redundancy method of control right setting signal thereof |
| US20080184066A1 (en) * | 2007-01-26 | 2008-07-31 | Rdc Semiconductor Co., Ltd. | Redundant system |
| CN101281483A (en) * | 2008-05-12 | 2008-10-08 | 北京邮电大学 | Dual-computer redundant fault-tolerant system and its redundant switching method |
| CN102521059A (en) * | 2011-11-15 | 2012-06-27 | 北京空间飞行器总体设计部 | On-board data management system self fault-tolerance method |
| CN105335261A (en) * | 2015-12-08 | 2016-02-17 | 山东超越数控电子有限公司 | Design method for testing BIT in server equipment |
| CN107065830A (en) * | 2017-05-03 | 2017-08-18 | 北京电子工程总体研究所 | A kind of dual redundant hot backup system based on arbitration mode |
-
2017
- 2017-12-11 CN CN201711309768.7A patent/CN109901380A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038574A (en) * | 2006-03-17 | 2007-09-19 | 上海奇码数字信息有限公司 | Bus arbitration device |
| JP2008146236A (en) * | 2006-12-07 | 2008-06-26 | Toshiba Corp | Redundant control device and redundancy method of control right setting signal thereof |
| US20080184066A1 (en) * | 2007-01-26 | 2008-07-31 | Rdc Semiconductor Co., Ltd. | Redundant system |
| CN101281483A (en) * | 2008-05-12 | 2008-10-08 | 北京邮电大学 | Dual-computer redundant fault-tolerant system and its redundant switching method |
| CN102521059A (en) * | 2011-11-15 | 2012-06-27 | 北京空间飞行器总体设计部 | On-board data management system self fault-tolerance method |
| CN105335261A (en) * | 2015-12-08 | 2016-02-17 | 山东超越数控电子有限公司 | Design method for testing BIT in server equipment |
| CN107065830A (en) * | 2017-05-03 | 2017-08-18 | 北京电子工程总体研究所 | A kind of dual redundant hot backup system based on arbitration mode |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115903581A (en) * | 2022-10-26 | 2023-04-04 | 中国航空工业集团公司西安航空计算技术研究所 | Master-slave preemption switching method of dual-redundancy controller |
| CN115903581B (en) * | 2022-10-26 | 2025-04-01 | 中国航空工业集团公司西安航空计算技术研究所 | A master-slave switching method for dual-redundancy controller |
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Application publication date: 20190618 |