CN109874008B - Method for distinguishing crash problem through fault test - Google Patents

Abstract

The present invention relates to the technical field of smart TVs, and in particular to a method for distinguishing crash problems through fault testing, which includes: step S1, performing a plurality of different types of fault tests on a system-on-chip, so as to obtain information about the system-on-chip corresponding to different types of faults. For a plurality of reaction conditions, summarize the plurality of reaction conditions, and store them in a storage unit together with the corresponding fault type; step S2, according to the corresponding reaction information of the system on chip to be tested, carry out the process with the reaction conditions stored in the storage unit. match to obtain the current fault type of the system-on-chip under test. The beneficial effect is that: according to the corresponding response information of the system-on-chip to be tested, the response conditions stored in the storage unit are matched to obtain the current fault type of the system-on-chip to be tested, so that the problem can be quickly located or the scope of the problem can be narrowed down by the elimination method , which provides a good example for troubleshooting.

Description

A method of distinguishing crash problems by fault testing

technical field

The invention relates to the technical field of smart TVs, in particular to a method for distinguishing crash problems through fault testing.

Background technique

At present, smart TVs have more and more system functions, and the main frequency of a CPU (Central Processing Unit, central processing unit) is also getting higher and higher, and the requirements for the stability of the peripheral power supply are also getting higher and higher. In order to ensure the stability of the product and consider the life of the product, it is necessary to carry out a large number of pressure tests in the research and development stage, including high and low temperature tests (45 degrees -15 degrees), or AC switch tests, or remote switch tests. These tests are characterized by a large number of samples and a long test period. When some random loopholes appear in the test process, it will take a long time to troubleshoot and verify the problem, which will have a greater impact on the entire test progress, or even affect Development progress of the entire product.

The solution in the prior art is to add as many debugging nodes as possible during the software architecture development process, hoping to record the running state of the entire system. If an exception occurs during the aging process, the printed error log will become the most Precious analysis data, but because the driver of the SoC has a relatively independent flag, when a module is abnormal during the test process, the error log can point to the relevant module, such as EMMC (Embedded Multimedia Card, embedded memory), DDR (Double Data Rate, double rate synchronous dynamic random access memory), TUNER (radio coordinator) and other related module errors, can obviously get information from the error log, but the premise of the error log output is that the on-chip system is running normally, if The system-on-chip has an error and cannot output any information. In this case, it is impossible to analyze the problem through the error message. And this kind of system depth anomaly is the most difficult and time-consuming problem in aging experiments.

SUMMARY OF THE INVENTION

Aiming at the above problems existing in the prior art, a method for distinguishing a crash problem through a fault test is now provided.

The specific technical solutions are as follows:

A method of distinguishing crash problems through failure testing, for smart TVs, including:

Step S1, performing multiple different types of fault tests on the system-on-chip to obtain multiple response conditions corresponding to different types of fault types of the system-on-chip, summarizing the multiple response conditions, and together with the corresponding fault types. stored in a storage unit;

Step S2 , matching the response information stored in the storage unit according to the corresponding response information of the system-on-chip to be tested to obtain the current fault type of the system-on-chip to be tested.

Preferably, in the step S1, corresponding response information is obtained for each of the response conditions of the system-on-chip, and the response information includes a screen display and a correspondingly generated error log.

Preferably, the system-on-chip includes a power module; and/or a memory module; and/or a radio tuner module.

Preferably, in the step S1, the fault test for the power module includes a fixed pin short-circuit test; and/or a crystal oscillator output short-circuit test.

Preferably, in the step S1, the failure test for the memory module includes a short circuit test of memory clock data; and/or a short circuit test of memory data lines.

Preferably, in the step S1, in the step S1, the fault test of the radio tuner module includes a short-circuit test of a positive-phase power input pin and a negative-phase power input pin; and/or a low-voltage differential Short circuit test between the positive-phase clock signal pin of the signal and the negative-phase clock signal pin of the low-voltage differential signal; and/or the positive-phase clock signal pin of the high-definition multimedia interface and the negative-phase clock signal lead of the high-definition multimedia interface. Short circuit test of feet.

Preferably, the fixed pin short-circuit test includes a memory short-circuit test.

Preferably, the fixed pin short circuit test includes a graphics processor short circuit test.

Preferably, the fixed pin short-circuit test includes a central processing unit short-circuit test.

Preferably, the fixed pin short-circuit test includes a 3.3V power supply adjustment output pin or a 1.8V voltage analog front-end pin short-circuit test.

The beneficial effects of the technical solution of the present invention are: to provide a method for distinguishing a crash problem through fault testing, and according to the corresponding response information of the system on chip to be tested, it is matched with the response situation stored in the storage unit, so as to obtain the current state of the system on chip to be tested. In this way, the problem can be quickly located or the scope of the problem can be narrowed down through the elimination method, which provides a good example for troubleshooting.

Description of drawings

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the accompanying drawings are for illustration and illustration only, and are not intended to limit the scope of the present invention.

FIG. 1 is a flow chart of steps of a method for distinguishing a crash problem through a fault test according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict.

The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention.

In the prior art, due to the large difference between the ambient temperature and the normal temperature during the aging process, the change in temperature will cause some differences in the performance of the semiconductor, such as an increase in leakage current; low temperature will lead to a decrease in the effective capacitance of the capacitor. The change will cause the ripple of the power supply to become larger. As long as the system has a sudden operation, the load will become larger, which is likely to cause the system to collapse. The power supply of multiple modules is difficult to achieve.

Therefore, in view of the above-mentioned problems in the prior art, the present invention discloses a method for distinguishing the crash problem through a fault test, which is used in a smart TV, including:

Step S1, performing multiple different types of fault tests on the system-on-chip to obtain multiple response conditions corresponding to different types of faults in the system-on-chip, summarize the multiple response conditions, and store them together with the corresponding fault types in a storage in the unit;

Step S2 , matching the response information stored in the storage unit according to the corresponding response information of the system-on-chip to be tested, so as to obtain the current fault type of the system-on-chip to be tested.

Through the technical solution of the above method of distinguishing the crash problem through fault testing, as shown in Figure 1, the method is applied to smart TVs, and multiple different types of fault tests are performed on the SoC to obtain the SoC corresponding to different types of fault types. A plurality of reaction conditions, the plurality of reaction conditions are summarized, and stored in a storage unit together with the corresponding fault type, wherein the system-on-chip includes a power supply module; and/or a memory module; and/or a radio tuner module, and then according to The corresponding response information of the system-on-chip to be tested is matched with the response conditions stored in the storage unit to obtain the current fault type of the system-on-chip to be tested. In this way, the problem can be quickly located or the scope of the problem can be narrowed down through the elimination method, which provides a solution for troubleshooting. Good illustration.

In a preferred embodiment, in step S1, corresponding response information is obtained for each response situation of the system-on-chip, and the response information includes a screen display and a correspondingly generated error log. In a short period of time, the images of various hardware abnormal states can be linked with the error log, which provides a good example for analyzing the vulnerabilities of random crashes, and provides a good example for further locating the problem and eliminating the problem.

In a preferred embodiment, as shown in Figure 1, in step S1, the fault test for the power module includes a fixed pin short-circuit test; and/or a crystal oscillator output short-circuit test. Among them, the fixed pin short-circuit test includes memory short-circuit test, graphics processor short-circuit test, central processing unit short-circuit test and 3.3V power supply adjustment output pin or 1.8V voltage analog front-end pin short-circuit test.

Specifically, when the memory short-circuit test is performed, the screen corresponding to DDR_1V2 is displayed as the screen disappears, the red screen, and/or the generated error log is crash, printing stops, and there is no obvious error indication; the screen corresponding to DDR_2V5 is displayed as the screen disappears, black screen, and/or the resulting error log is a crash, printing stops, and no obvious error indication.

Further, when the graphics processor is short-circuit tested, the corresponding screen is displayed as the screen disappears, the screen is black, and/or the generated error log is a crash, printing stops, and there is no obvious error indication; when the CPU is short-circuited, the corresponding screen is displayed. The display shows that the screen is still, and/or the generated error log is crash, the printing stops, and there is no obvious error indication; when the 3.3V power supply adjustment output pin is short-circuited, the corresponding screen shows that the system restarts, and/or the generated The error log is printed without abnormality before restarting; when the voltage of 1.8V simulates the short circuit test of the front-end pins, the corresponding screen is displayed as the screen disappears, the screen is black, and/or the generated error log is crash, printing stops, and there is no obvious error indication ; When the crystal oscillator output is short-circuited, the corresponding screen is displayed as the screen disappears, the red screen, and/or the generated error log is crash, printing stops, and there is no obvious error indication. Further, images of various hardware abnormal states can be linked with error logs in a short period of time, providing a good example for analyzing the vulnerability of random crashes, so that the problem can be quickly located or narrowed by the elimination method, which is a good way to eliminate the problem. Questions provide a good illustration.

Table I

interference method screen display error log prompt Short DDR_1V2 Screen disappears, red screen Crash, printing stopped, no obvious error message Short DDR_2V5 Screen disappears, black screen Crash, printing stopped, no obvious error message Short VDDEE (GPU) Screen disappears, black screen Crash, printing stopped, no obvious error message Short VCCK(CPU) Still picture Crash, printing stopped, no obvious error message Short AO_3.3V system restart No abnormal printing before restart Short AFE_1.8V Screen disappears, black screen Crash, printing stopped, no obvious error message Short circuit crystal output Screen disappears, red screen Crash, printing stopped, no obvious error message

Further, multiple different types of fault tests are performed on the system-on-chip to obtain multiple response situations corresponding to different types of fault types of the system-on-chip, and the multiple response situations are summarized and stored together with the corresponding fault types in a storage device. Then, according to the corresponding response information of the system-on-chip to be tested, it is matched with the response conditions stored in the storage unit to obtain the current fault type of the system-on-chip to be tested.

In a preferred embodiment, in step S1, the failure test for the memory module includes a short circuit test of memory clock data; and/or a short circuit test of memory data lines.

Specifically, as shown in Figure 2, when the memory DDR clock data is short-circuited, the corresponding screen is displayed as the screen disappears, the red screen, and/or the generated error log is a crash restart without obvious error indication; or when the memory EMMC clock During the data short-circuit test, the corresponding screen is displayed as the screen is still, and/or the generated error log is a normal print output, indicating an EMMC error; when the memory EMMC data line is short-circuited, the corresponding screen is displayed as a normal screen, and/or generated The error log prints normal output, prompting an EMMC error. Further, images of various hardware abnormal states can be linked with error logs in a short period of time, providing a good example for analyzing the vulnerability of random crashes, so that the problem can be quickly located or narrowed by the elimination method, which is a good way to eliminate the problem. Questions provide a good illustration.

In a preferred embodiment, in step S1, the fault test for the radio tuner module includes a short-circuit test between the positive-phase power input pin and the negative-phase power input pin; and/or the positive-phase low-voltage differential signal Short-circuit test between clock signal pin and negative-phase clock signal pin of low-voltage differential signal; and/or short-circuit test between positive-phase clock signal pin of high-definition multimedia interface and negative-phase clock signal pin of high-definition multimedia interface .

Specifically, as shown in Figure 2, when the positive-phase power input pin and the negative-phase power input pin are short-circuited, the corresponding screen is displayed as the screen is still, and the screen returns to normal after the interference is stopped, and/or the generated error log In order to print the normal output, it indicates that there is no signal output; when the positive-phase clock signal pin of the low-voltage differential signal and the negative-phase clock signal pin of the low-voltage differential signal are short-circuited, the corresponding picture is displayed as the picture disappears, and the picture is normal after the interference is stopped. , and/or the generated error log is no abnormality in printing; when the positive-phase clock signal pin of the high-definition multimedia interface is short-circuited with the negative-phase clock signal pin of the high-definition multimedia interface, the corresponding picture is displayed as a picture disappears, the screen is normal after the interference is stopped, and/or the generated error log is the normal output of printing, indicating that there is no signal output. Further, images of various hardware abnormal states can be linked with error logs in a short period of time, providing a good example for analyzing the vulnerability of random crashes, so that the problem can be quickly located or narrowed by the elimination method, which is a good way to eliminate the problem. Questions provide a good illustration.

Table II

Further, multiple different types of fault tests are performed on the system-on-chip to obtain multiple response situations corresponding to different types of fault types of the system-on-chip, and the multiple response situations are summarized and stored together with the corresponding fault types in a storage device. Then, according to the corresponding response information of the system-on-chip to be tested, it is matched with the response conditions stored in the storage unit to obtain the current fault type of the system-on-chip to be tested.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the embodiments and protection scope of the present invention. For those skilled in the art, they should be able to realize that all equivalents made by using the description and illustrations of the present invention The solutions obtained by substitutions and obvious changes shall all be included in the protection scope of the present invention.

Claims (9)

1. a method for distinguishing crash problems by fault test, for smart TV, is characterized in that, comprises: Step S1, performing multiple different types of fault tests on the system-on-chip to obtain multiple response conditions corresponding to different types of fault types of the system-on-chip, summarizing the multiple response conditions, and together with the corresponding fault types. stored in a storage unit; Step S2, matching the response information stored in the storage unit according to the corresponding response information of the system-on-chip to be tested, so as to obtain the current fault type of the system-on-chip to be tested; In the step S1, corresponding response information is acquired for each of the response conditions of the system-on-chip, and the response information includes a screen display and a correspondingly generated error log. 2 . The method for distinguishing a crash problem through a fault test according to claim 1 , wherein the system-on-chip comprises a power module; and/or a memory module; and/or a radio tuner module. 3 . 3. The method for distinguishing a crash problem by fault testing according to claim 2, wherein in the step S1, the fault testing of the power module comprises a fixed pin short-circuit test; and/or the crystal oscillator output is short-circuited test. 4. The method according to claim 2, wherein in the step S1, the fault test for the memory module comprises a memory clock data short circuit test; and/or a memory data line Short circuit test. 5. The method according to claim 2, wherein in the step S1, the fault test of the radio tuner module comprises a positive-phase power input pin and a negative-phase power supply Short-circuit test of input pins; and/or short-circuit test of positive-phase clock signal pins of low-voltage differential signals and negative-phase clock signal pins of low-voltage differential signals; and/or positive-phase clock signal pins of high-definition multimedia interfaces Short circuit test with negative phase clock signal pin of HD multimedia interface. 6 . The method for distinguishing a crash problem through a fault test according to claim 3 , wherein the fixed pin short-circuit test comprises a memory short-circuit test. 7 . 7 . The method for distinguishing a crash problem through a fault test according to claim 3 , wherein the fixed pin short-circuit test comprises a graphics processor short-circuit test. 8 . 8 . The method for distinguishing a crash problem through a fault test according to claim 3 , wherein the fixed pin short-circuit test comprises a central processing unit short-circuit test. 9 . 9. the method for distinguishing crash problem by fault test according to claim 3, is characterized in that, described fixed pin short-circuit test comprises the short-circuit test of the power supply adjustment output pin of 3.3V or the voltage analog front-end pin of 1.8V .

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