CN109856876B - Array substrate, display panel, display device and driving method - Google Patents
Array substrate, display panel, display device and driving method Download PDFInfo
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Abstract
本申请公开了一种阵列基板、显示面板、显示装置及驱动方法，其中，阵列基板包括N行M列像素单元，各像素单元包括串联设置的第一晶体管和第二晶体管，所述第一晶体管的源极用于连接源极驱动电路，所述第一晶体管的栅极用于连接栅极驱动电路，所述第一晶体管的漏极与所述第二晶体管的源极连接，所述第二晶体管的漏极连接像素电容；奇数行的所述第二晶体管的栅极与同一第一控制信号线连接；偶数行的所述第二晶体管的栅极与同一第二控制信号线连接，所述第一控制信号线与所述第二控制信号线均用于与显示驱动IC连接。上述方案可以解决串扰的问题。
The present application discloses an array substrate, a display panel, a display device and a driving method, wherein the array substrate includes N rows and M columns of pixel units, each pixel unit includes a first transistor and a second transistor arranged in series, the first transistor The source of the first transistor is used to connect to the source drive circuit, the gate of the first transistor is used to connect to the gate drive circuit, the drain of the first transistor is connected to the source of the second transistor, and the second transistor is connected to the source of the second transistor. The drains of the transistors are connected to the pixel capacitors; the gates of the second transistors in odd rows are connected to the same first control signal line; the gates of the second transistors in even rows are connected to the same second control signal line, the Both the first control signal line and the second control signal line are used for connecting with the display driving IC. The above solution can solve the problem of crosstalk.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel, a display device and a driving method.
Background
At present, the development of science and technology is more and more rapid, along with the rapid development of science and technology, the mobile phone industry also has rapid and violent development, the only communication function of the traditional functional mobile phone can not meet the requirements of people on the mobile phone at present, the requirements of people on the mobile phone are added with the functions of audio and video playing and the like, so that consumers pay more and more attention to the details of the display content of the mobile phone.
In the current design scheme of a display screen of a mobile phone, a Thin Film Transistor (Thin Film Transistor) that controls the turn-On of a Gate On Array (Gate Driver circuit) of each row is turned On only once in one Frame (Frame) to charge a pixel capacitor (also referred to as a storage capacitor) of a liquid crystal, and the TFTs are all in a turn-off state for the rest of the time. The TFT is kept in the off state for a long time, which may cause a problem that the TFT is stressed (that is, the TFT characteristics are changed), and the TFT unit after stressed cannot be completely turned off, so that data of other rows may be filled in the pixel capacitors of the pixels of the row, which may cause a Crosstalk (Crosstalk) phenomenon.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide an array substrate, a display panel, a display device and a driving method for solving the crosstalk problem in the prior art.
In a first aspect, the present invention provides an array substrate, including N rows and M columns of pixel units, where each pixel unit includes a first transistor and a second transistor that are serially connected, a source of the first transistor is used to connect to a source driving circuit, a gate of the first transistor is used to connect to a gate driving circuit, a drain of the first transistor is connected to a source of the second transistor, and a drain of the second transistor is connected to a pixel capacitor;
the grid electrodes of the second transistors in the odd-numbered rows are connected with the same first control signal line; and the grid electrodes of the second transistors in the even rows are connected with the same second control signal line, and the first control signal line and the second control signal line are both used for being connected with a display driving IC.
Further, the first transistor and the second transistor are both TFTs.
In a second aspect, the present invention provides a display panel, including the array substrate.
In a third aspect, the present invention provides a display device, including the above array substrate; or, the display panel described above.
In a fourth aspect, the present invention provides a driving method of the array substrate, including:
sequentially inputting a first scanning voltage signal to the first transistors of each row through a gate driving circuit;
when a first scanning voltage signal is input to the first transistors in the odd-numbered rows, a first control voltage signal is input to the first control signal line through the display driving IC, so that the turn-on time of the first transistors and the turn-on time of the second transistors in the current row are at least partially overlapped;
when the first scanning voltage signal is input to the first transistors in the even-numbered rows, the second control voltage signal is input to the second control signal line through the display driving IC, so that the turn-on time of the first transistors and the turn-on time of the second transistors in the current row are at least partially overlapped.
Further, the first scanning voltage signal, the first control voltage signal and the second control voltage signal are all square wave signals.
Further, the pulse widths of the first control voltage signal and the second control voltage signal are both greater than the pulse width of the first scan voltage signal.
According to the scheme, each pixel unit is provided with the first transistor and the second transistor in series, and the corresponding pixel capacitor is charged through the source electrode driving circuit only under the condition that the first transistor and the second transistor are both conducted. In addition, since the gates of the second transistors of the odd-numbered rows are connected to the same first control signal line; the grid electrodes of the second transistors in the even-numbered rows are connected with the same second control signal line, and under the condition that the first transistor and the second transistor in a certain odd-numbered row or even-numbered row are both conducted, the second transistors in the other odd-numbered rows or even-numbered rows are also conducted. In addition, because the first control signal line and the second control signal line are both used for being connected with the display drive IC, the display drive IC outputs a voltage signal for controlling the on-off of the second transistor, and the voltage signal for controlling the on-off of the second transistor is not generated by the grid drive circuit, so that the grid drive circuit can be suitable for the existing grid drive circuit, the design complexity and difficulty are reduced under the condition that the grid drive circuit does not need to be modified, the subsequent forming process of the grid drive circuit does not need to be modified, and the rapid mass production is utilized.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a schematic diagram of a circuit of an array substrate according to an embodiment of the present invention;
fig. 2 is a timing diagram for driving the first transistor and the second transistor to be turned off according to an embodiment of the present invention.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
As shown in fig. 1, the array substrate provided by the present invention includes N rows and M columns of pixel units 1, each pixel unit 1 includes a first transistor 2 and a second transistor 3 that are serially connected, a source of the first transistor 2 is used for connecting to a source driving circuit, a gate of the first transistor 2 is used for connecting to a gate driving circuit, a drain of the first transistor 2 is connected to a source of the second transistor 3, and a drain of the second transistor 3 is connected to a pixel capacitor 4; the gates of the second transistors 3 in the odd-numbered rows are connected to the same first Control signal line Control _ odd; the gates of the second transistors 3 in the even-numbered rows are connected to the same second Control signal line Control _ even, and the first Control signal line Control _ odd and the second Control signal line Control _ even are both used for being connected to the display drive IC.
Where N and M are natural numbers, which can be set according to the resolution, for example, 1920 rows and 1080 columns are shown in fig. 1. The intersection of 1920 rows of gate lines and 1080 columns of source lines defines 1920 rows and 1080 columns of pixel cells arranged in a matrix. Wherein, the Gate lines of 1920 rows are marked as Gate1, gate2, gate3 \8230 \ 8230, gate1918, gate1919 and Gate1920 in sequence; the 1080 columns of Source lines are sequentially marked as Source line1, source line2, source line3 \8230, 8230, source line1078, source line1079 and Source line1080, it should be noted that signals in each line and the line where the signal is located adopt the same item number, for example, the first row of Gate lines is marked as Gate1, and the first scanning voltage signal on the Gate line is also marked as Gate1; the second row of Gate lines is labeled Gate2, and the first scan voltage signal on the Gate line is also labeled Gate2, and so on. The source of the first transistor 2 in each column is connected to a source driver circuit via a corresponding source line. The gates of the first transistors 2 in each row are connected to a gate driving circuit through corresponding gate lines.
The gate driving circuit is configured to input a first scanning voltage signal to the corresponding first transistor 2 through each gate line to control on/off of the first transistor 1, and the source driving circuit is configured to write data into the pixel capacitor 4 of the current row through each source line under the condition that the first transistor 2 and the second transistor 3 of the current row are both turned on, that is, charge the pixel capacitor 4 of the current row. When the first transistor 2 of the current row is turned on, a display driver IC (Integrated Circuit) is connected to the corresponding first control signal line or second control signal line to input a control voltage signal to the corresponding second transistor 3 of the odd-numbered row or even-numbered row, thereby turning on the corresponding second transistor 3 of the odd-numbered row or even-numbered row. If the current row is an odd-numbered row, the Control voltage signal is input to the second transistors 3 of all the odd-numbered rows through the first Control signal line Control _ odd, and if the current row is an even-numbered row, the Control voltage signal is input to the second transistors 3 of all the even-numbered rows through the second Control signal line Control _ even.
In the above scheme, each pixel unit 1 is provided with the first transistor 2 and the second transistor 3 in series, and only under the condition that the first transistor 2 and the second transistor 3 are both turned on, the corresponding pixel capacitor 4 is charged through the source driving circuit. Further, since the gates of the second transistors 3 of the odd-numbered rows are connected to the same first control signal line; the gates of the second transistors 3 in the even-numbered rows are connected to the same second control signal line, and when the first transistor and the second transistor 3 in a certain odd-numbered row or even-numbered row are both turned on, the second transistors 3 in the remaining odd-numbered rows or even-numbered rows are also turned on, and because the array substrate is scanned row by row in one frame, the corresponding second transistors 3 in the odd-numbered rows or even-numbered rows perform a switching operation once during each scanning row, so that the problem that the transistors are Stress due to being in an off state for a long time is avoided, and at least the second transistors 3 in the other rows can be completely turned off, that is, when the pixel capacitors in the current row are charged, the second transistors 3 in the other rows are completely turned off, so that the problem of crosstalk caused by the fact that the transistors cannot be completely turned off after Stress is solved. In addition, because the first Control signal line Control _ odd and the second Control signal line Control _ even are both used for being connected with the display drive IC, the display drive IC outputs a Control voltage signal for controlling the on/off of the second transistor 3, rather than generating a Control voltage signal for controlling the on/off of the second transistor 3 through the gate drive circuit, so that the gate drive circuit can be applied to the existing gate drive circuit, the design complexity and difficulty are reduced without modifying the gate drive circuit, the subsequent formation process of the gate drive circuit is not required to be modified, and the rapid mass production is utilized.
Further, the first transistor 2 and the second transistor 3 are both TFTs.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate, where specific structures of the array substrate refer to the foregoing embodiments, and are not described herein again.
In a third aspect, an embodiment of the present invention further provides a display device, including the array substrate; or the display panel described above. The display device is, for example, but not limited to, a display, a mobile phone, a tablet computer, etc.
In a fourth aspect, an embodiment of the present invention further provides a driving method of an array substrate, including sequentially inputting a first scanning voltage signal to the first transistors 2 in each row through a gate driving circuit;
when a first scanning voltage signal is input to the first transistors 2 in the odd-numbered rows, a first Control voltage signal Control _ odd is input to the first Control signal line through the display driving IC, so that the turn-on time of the first transistors 2 and the turn-on time of the second transistors 3 in the current row are at least partially overlapped;
when the first scan voltage signal is input to the first transistors 2 in the even-numbered rows, the second Control voltage signal Control _ even is input to the second Control signal line through the display drive IC, so that the turn-on time of the first transistors 2 and the turn-on time of the second transistors 3 in the current row at least partially coincide.
Specifically, as shown in fig. 2, the first scan voltage signal, the first control voltage signal and the second control voltage signal are all square wave signals. The first scanning voltage signal is generated by a gate driving circuit, the gate driving circuit is similar to a shift register, the gate driving circuit generates a square wave signal to control the on-off of the first transistor in one row, when another square wave signal is generated, the on-off of the first transistor in the next row is controlled, and the on-off control of the first transistors in the next row is performed by analogy, namely, the row-by-row scanning is performed. Thus, when the first Control voltage signal Control _ odd and the first scan voltage signals Gate1, gate3 \ 8230wherein the rising edge of Gate1919 is asserted to turn on the first transistor 2 and the second transistor 3 corresponding to the odd-numbered row, the first scan voltage signal of the even-numbered row completes a pull-down operation, and similarly, when the first Control voltage signal Control _ even and the first scan voltage signals Gate2, gate4 \ 8230, the rising edge of Gate1920 is asserted to turn on the first transistor 2 and the second transistor 3 corresponding to the even-numbered row, the first scan voltage signal of the odd-numbered row completes a pull-down operation.
For example, when the Gate driving circuit inputs the first scanning voltage signal Gate1 to the first transistor 2 in the first row, the display driving IC inputs the first Control voltage signal Control _ odd to the first Control signal line, the first scanning voltage signal Gate1 and the first Control voltage signal Control _ odd overlap at least partially, the first transistor 2 and the second transistor 3 are both turned on at the overlapped portion, the pixel capacitance of the corresponding pixel is charged by the source driving circuit at this time, and the second transistors 3 in the remaining odd-numbered rows are turned on and off once at this time.
When the Gate driving circuit inputs the first scanning voltage signal Gate2 to the first transistor 2 in the second row, the display driving IC inputs the first Control voltage signal Control _ even to the first Control signal line, at least a part of the time of the first scanning voltage signal Gate2 coincides with the first Control voltage signal Control _ even, at the coinciding part, the first transistor 2 and the second transistor 3 are both turned on, at this time, the pixel capacitor of the corresponding pixel is charged through the source driving circuit, at this time, the second transistors 3 in the remaining even rows perform one on-off operation.
When the Gate driving circuit inputs the first scanning voltage signal Gate3 to the first transistor 2 of the third row, the display driving IC inputs the first Control voltage signal Control _ odd to the first Control signal line, the first scanning voltage signal Gate3 and the first Control voltage signal Control _ odd are at least partially overlapped in time, the first transistor 2 and the second transistor 3 are both turned on at the overlapped part, at this time, the pixel capacitor of the corresponding pixel is charged through the source driving circuit, and at this time, the second transistors 3 of the rest odd-numbered rows are turned on and off once.
When the Gate driving circuit inputs the first scanning voltage signal Gate4 to the first transistor 2 in the fourth row, the display driving IC inputs the first Control voltage signal Control _ even to the first Control signal line, the first scanning voltage signal Gate4 and the first Control voltage signal Control _ even are at least partially overlapped in time, the first transistor 2 and the second transistor 3 are both turned on in the overlapped portion, at this time, the pixel capacitance of the corresponding pixel is charged through the source driving circuit, and at this time, the second transistors 3 in the remaining even-numbered rows perform one-time on-off operation.
In this way, scanning of all rows in one frame is finished, and in the scanning of all rows in one frame, the second transistor 3 is switched on and off for many times, so that the problem that the transistors are subjected to Stress due to the fact that the transistors are in a turn-off state for a long time is solved, at least the second transistor 3 can be completely switched off, namely when the pixel capacitor 4 in the current row is charged, the second transistors 3 in other rows are completely switched off, and the problem of crosstalk caused by the fact that the transistors cannot be completely switched off after Stress is solved.
Further, the pulse widths of the first Control voltage signal Control _ odd and the second Control voltage signal Control _ even are both greater than the pulse width of the first scan voltage signal. As a preferred mode, the pulse widths of the first Control voltage signal Control _ odd and the second Control voltage signal Control _ even are equal to each other and are Width2, and the pulse Width of the first scan voltage signal is Width1, width 2 >Width 1 That is, the duty ratio of the first Control voltage signal Control _ odd and the second Control voltage signal Control _ even is greater than the duty ratio of the first scan voltage signal. Width 2 >Width 1 It is ensured that the first transistor 2 and the second transistor 3 have a common on-time of a sufficiently long time to allow the pixel capacitance 4 to have a sufficient charging time. In order to ensure the charging duration, a preferred implementation manner is that the high level period of the first scan voltage signal is completely included in the high level period of the first/second control voltage signals.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
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| CN110687731A (en) * | 2019-10-12 | 2020-01-14 | 上海天马微电子有限公司 | Display panel, driving method and display device |
| CN113568232B (en) * | 2021-09-27 | 2021-12-28 | 南京初芯集成电路有限公司 | Pixel unit, array substrate and driving method, liquid crystal panel and liquid crystal display |
| WO2025137812A1 (en) * | 2023-12-25 | 2025-07-03 | 京东方科技集团股份有限公司 | Display substrate and display device |
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