CN109831203B - Switching device - Google Patents
Switching device Download PDFInfo
- Publication number
- CN109831203B CN109831203B CN201811650006.8A CN201811650006A CN109831203B CN 109831203 B CN109831203 B CN 109831203B CN 201811650006 A CN201811650006 A CN 201811650006A CN 109831203 B CN109831203 B CN 109831203B
- Authority
- CN
- China
- Prior art keywords
- switch
- signal
- tube
- switching tube
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 13
- 238000005070 sampling Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 description 10
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a conversion device. The device comprises: the first switch unit is used for receiving an alternating current part of an externally input differential signal pair and outputting a full-swing signal pair according to the alternating current part of the differential signal pair; a second switching unit for outputting a switching signal; an upper limit unit for configuring an upper limit amplitude of the full-swing signal pair according to the switch signal; and the lower limit unit is used for configuring the lower limit amplitude of the full-swing signal pair according to the switch signal. The invention can convert the differential signal pair into the full swing CMOS signal pair.
Description
Technical Field
The present invention relates to the field of circuits and signal processing, and more particularly, to a conversion device for converting differential signal pairs into CMOS signals.
Background
Differential signals are anti-noise techniques often used in the integrated circuit arts; the anti-common mode noise, anti-signal interference and anti-power ground noise characteristics. Differential signals are often used to transmit signals to the outside within the integrated circuit chip and at interfaces. But the external device receiving the signal receives only part of the full swing CMOS signal.
Disclosure of Invention
The embodiment of the invention discloses a conversion device which can convert a differential signal pair into a full-swing CMOS signal pair.
The conversion device includes:
The first switch unit is used for receiving an alternating current part of the differential signal pair input from the outside and outputting a full-swing signal pair according to the alternating current part of the differential signal pair;
a second switching unit for outputting a switching signal;
An upper limit unit for configuring an upper limit amplitude of the full-swing signal pair according to the switch signal;
And the lower limit unit is used for configuring the lower limit amplitude of the full-swing signal pair according to the switch signal.
In some embodiments of the present disclosure, the first switching unit includes:
The first switching circuit comprises a first forward switching tube and a first reverse switching tube, the input end of the first forward switching tube is coupled with the output end of the first reverse switching tube, the control ends of the first forward switching tube and the first reverse switching tube are used for inputting a first alternating current signal of a differential signal pair,
The second switching circuit comprises a second forward switching tube and a second reverse switching tube, the input end of the second forward switching tube is coupled with the output end of the second reverse switching tube, and the control ends of the second forward switching tube and the second reverse switching tube are both used for inputting a second alternating current signal of the differential signal pair;
The input end of the first reverse switching tube and the input end of the second reverse switching tube are coupled with the upper limit unit;
The output end of the first forward switching tube and the output end of the second forward switching tube are coupled with the lower limit unit;
A first output node is configured between the input end of the first forward switch tube and the output end of the first reverse switch, and the first output node is used for outputting a first swing signal of the full swing signal pair;
a second output node is configured between the input end of the second forward switch tube and the output end of the second reverse switch, and the second output node is used for outputting a second swing signal of the full swing signal pair.
In some embodiments of the disclosure, the first output node is coupled to the control ends of the first forward switching tube and the first reverse switching tube through a first bias resistor;
The second output node is coupled to the control ends of the second forward switching tube and the second reverse switching tube through a second bias resistor.
In some embodiments of the present disclosure, the first forward switching transistor and the second forward switching transistor are NMOS transistors;
The first reverse switch tube and the second reverse switch tube are PMOS tubes.
In some embodiments of the present disclosure, the conversion device further includes:
The first isolation unit is used for receiving a first single-ended signal of a differential signal pair input from the outside, isolating a direct current part of the first single-ended signal and outputting a first alternating current signal;
The second isolation unit is used for receiving a second single-ended signal of the differential signal pair input from the outside, isolating a direct current part of the second single-ended signal and outputting a second alternating current signal.
In some embodiments of the present disclosure, the second switching unit is configured to collect a differential signal pair and output a switching signal according to a mean value of the differential signal pair.
In some embodiments of the present disclosure, the second switching unit includes a first sampling resistor and a second sampling resistor;
The first sampling resistor and the second sampling resistor are connected in series between the differential signal pairs;
the first sampling resistor and the second sampling resistor are configured to output a switching signal.
In some embodiments of the present disclosure, the upper limit unit includes:
The input end of the power switch tube is coupled with an external power supply, the output end of the power switch tube is coupled with the input ends of the first reverse switch tube and the second reverse switch tube, and the control end inputs a switch signal.
In some embodiments of the present disclosure, the control terminal of the power switching tube inputs the switching signal through the inverter.
In some embodiments of the present disclosure, the lower limit unit includes:
the input end of the grounding switch tube is coupled with the output ends of the first forward switch tube and the second forward switch tube, the output end is grounded, and the control end inputs a switch signal.
Other features of embodiments of the present invention and advantages thereof will be apparent from the following detailed description of the disclosed exemplary embodiments with reference to the drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conversion device according to an embodiment;
FIG. 2 is a circuit diagram of a conversion device according to an embodiment;
fig. 3 is a circuit diagram of a conversion device according to the second embodiment.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as disclosed in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one:
The embodiment discloses a conversion device. For converting differential signal pairs into full swing CMOS signal pairs.
Referring to fig. 1, the conversion device includes a first isolation unit, a second isolation unit, a first switch unit, a second switch unit, an upper limit unit, and a lower limit unit.
The first isolation unit is configured to isolate a dc portion of the Vinp input from the outside, and output only an ac portion of the Vinp, that is, a first ac signal. The second isolation unit is used for isolating the direct current part of the Vinn input from the outside and outputting only the alternating current part of the Vinn, namely a second alternating current signal. The first ac signal and the second ac signal of the present embodiment are the same in size and opposite in phase.
The first switch unit is used for outputting full-swing CMOS signal pairs, namely Voutn and Voutp, according to the first alternating current signal and the second alternating current signal. The CMOS signal is independent of the common mode signals of Vinp and Vinn and is not affected by the common mode signal drift of Vinp and Vinn.
The second switch unit is used for collecting the first alternating current signal and the second alternating current signal and generating a switch signal according to the first alternating current signal and the second alternating current signal.
The upper limit unit is used for providing upper limit amplitude of Voutn and Voutp according to the switching signal; the lower limit unit is used for providing lower limit amplitude of Voutn and Voutp according to the switch signal.
Since the upper and lower limit amplitudes of the CMOS signal are provided by external power and power ground, noise from the external power and power ground can affect circuit performance. In order to eliminate the influence of the noise of the external power source and the power source ground on the circuit performance, the conversion device of the embodiment generates the switching signal through the first alternating current signal and the second alternating current signal, and then controls the upper limit unit and the lower limit unit to provide the upper limit amplitude and the lower limit amplitude for Voutn and Voutp through the switching signal, so that the external power source and the power source ground cause of Voutn and Voutp to cancel each other.
Preferably, the first isolation capacitor and the second isolation capacitor in this embodiment are a capacitor C1 and a capacitor C2.
Referring to fig. 2, the first switch unit of the present embodiment includes a first switch circuit and a second switch circuit.
The first switch circuit comprises a PMOS tube MP1 and an NMOS tube Mn1, wherein the grid electrodes of the PMOS tube MP1 and the NMOS tube Mn1 are coupled with external input through a capacitor C1, the drain electrode of the PMOS tube MP1 is coupled with the drain electrode of the NMOS tube Mn1, and the source electrode is coupled with the upper limit unit; the source of the NMOS transistor Mn1 is coupled to the lower limit unit. The second switch circuit comprises a PMOS tube MP2 and an NMOS tube Mn2, wherein the grid electrodes of the PMOS tube MP2 and the NMOS tube Mn2 are coupled with external input through a capacitor C2, the drain electrode of the PMOS tube MP2 is coupled with the drain electrode of the NMOS tube Mn2, and the source electrode is coupled with the upper limit unit; the source of the NMOS transistor Mn2 is coupled to the lower limit unit.
The drain electrode of the PMOS tube MP1 and the source electrode of the NMOS tube Mn1 are used as a first output node for coupling with the outside and outputting Voutn; the second output node between the PMOS transistor Mp2 and the NMOS transistor Mn2 is used for coupling with the outside and outputting Voutp.
Preferably, the part of the first switch unit may be directly implemented by two CMOS unit circuits.
With the above scheme, the first switch circuit and the second switch circuit in this embodiment respectively form a single-ended ac coupling structure, and are configured to output a CMOS signal pair according to the first ac signal and the second ac signal.
Preferably, the drain of the PMOS transistor Mp1 and the drain of the NMOS transistor Mn1 are coupled to the gate of the PMOS transistor Mp1 and the gate of the NMOS transistor Mn1 through a resistor R1; the drain of the PMOS tube MP2 and the drain of the NMOS tube Mn2 are coupled with the grid of the PMOS tube MP2 and the grid of the NMOS tube Mn2 through a resistor R2.
The four MOS tubes are respectively self-biased through the resistor R1 and the resistor R2, so that the average level of the grid electrode of the NMOS tube Mn1 and the grid electrode of the PMOS tube MP1 is equal to the average level of the drain electrode of the NMOS tube Mn1 and the drain electrode of the PMOS tube MP1, and the average level of the grid electrode of the NMOS tube Mn2 and the grid electrode of the PMOS tube MP2 is equal to the average level of the drain electrode of the NMOS tube Mn2 and the drain electrode of the PMOS tube MP 2; the duty ratio of Voutp and Voutn has a self-correcting function, and good duty ratio characteristics are obtained. Moreover, since the capacitor C1 and the capacitor C2 enable Vinp and Vinn to be input into the ac part only, the average levels of the gate of the NMOS transistor Mn1 and the gate of the PMOS transistor Mp1 are related to the average levels of the drain of the NMOS transistor Mn1 and the drain of the PMOS transistor Mp1 only, and the average levels of the gate of the NMOS transistor Mn2 and the gate of the PMOS transistor Mp2 are related to the average levels of the drain of the NMOS transistor Mn2 and the drain of the PMOS transistor Mp2 only; the common mode signals Vinp and Vinn can be arbitrarily valued, and generally take values between 0 and VDD.
Compared with the prior art, the value range of common mode signals of Vinp and Vinn is wider; and the common mode level of the comparator is required to ensure that the input MOS tube is in a saturation region and limit the value range of the common mode signal.
Referring to fig. 2, the second switch unit of the present embodiment includes a resistor R3 and a resistor R4, where the resistor R3 and the resistor R4 have the same value and are connected in series between a capacitor C1 and a capacitor C2. Then, a switching signal Vb is output between the resistor R3 and the resistor R4 as a sampling node, where the value of the switching signal Vb is an average value of the first ac signal and the second ac signal, that is, an average value of the gate voltages of the PMOS transistor Mp1 or the gate voltage of the NMOS transistor Mn1 and the gate voltage of the PMOS transistor Mp2 or the gate voltage of the NMOS transistor Mn 2.
Or the values of the resistor R3 and the resistor R4 are different. The value of the switch signal Vb in this embodiment is the voltage difference between the first ac signal and the second ac signal multiplied by the difference ratio between the resistor R3 and the resistor R4.
Referring to fig. 2, the upper limit unit of the present embodiment includes a PMOS transistor Mp3, a source of the PMOS transistor Mp3 is coupled to the external power supply VDD, a drain is coupled to sources of the PMOS transistors Mp1 and Mp2, and a gate is coupled to the sampling node. Then the tail current structure is formed by the PMOS tube MP3, so that the noise shielding of the external power supply VDD is realized; while being able to provide an upper limit amplitude for the CMOS signal pair.
Referring to fig. 2, the lower limit unit of the present embodiment includes an NMOS transistor Mn3, a source of the NMOS transistor Mn3 is coupled to the power ground, a drain is coupled to the source of the NMOS transistor Mn1 and the source of the NMOS transistor Mn2, and a gate is coupled to the sampling node. Then the NMOS tube Mn3 forms a tail current structure to realize noise shielding to the power ground; while being able to provide a lower limiting amplitude for the CMOS signal pair.
Embodiment two:
The conversion device of the present embodiment is different from the first embodiment in the second switching unit.
Referring to fig. 3, the second switching unit of the present embodiment includes an inverter A1, wherein an input end and an output end of the inverter A1 are coupled to output an oscillation level, and provide a switching signal Vb with stable frequency and an inversion signal with the same amplitude and opposite magnitude for switching on and off the gate of the PMOS transistor Mp3 and the gate of the NMOS transistor Mn 3. The present embodiment can mask noise of the external power supply VDD and the power supply ground; at the same time, the waveform of the CMOS signal pair is adjusted.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The conversion device is characterized by comprising a first isolation unit, a second isolation unit, a first switch unit, a second switch unit, an upper limit unit and a lower limit unit;
The first isolation unit is used for receiving a first single-ended signal of a differential signal pair input from the outside, isolating a direct current part of the first single-ended signal and outputting a first alternating current signal;
the second isolation unit is used for receiving a second single-ended signal of the differential signal pair input from the outside, isolating a direct current part of the second single-ended signal and outputting a second alternating current signal;
the first switch unit comprises a first switch circuit and a second switch circuit;
the first switching circuit comprises a first forward switching tube and a first reverse switching tube, the input end of the first forward switching tube is coupled with the output end of the first reverse switching tube, and the control ends of the first forward switching tube and the first reverse switching tube are both used for inputting a first alternating current signal of the differential signal pair;
The second switching circuit comprises a second forward switching tube and a second reverse switching tube, the input end of the second forward switching tube is coupled with the output end of the second reverse switching tube, and the control ends of the second forward switching tube and the second reverse switching tube are both used for inputting a second alternating current signal of the differential signal pair;
The input end of the first reverse switching tube and the input end of the second reverse switching tube are coupled with the upper limit unit;
The output end of the first forward switching tube and the output end of the second forward switching tube are coupled with the lower limit unit;
A first output node is configured between the input end of the first forward switch tube and the output end of the first reverse switch, and the first output node is used for outputting a first swing signal of a full swing signal pair;
a second output node is configured between the input end of the second forward switch tube and the output end of the second reverse switch, and the second output node is used for outputting a second swing signal of the full swing signal pair;
the second switch unit is used for collecting the differential signal pair and outputting a switch signal according to the average value of the differential signal pair;
the upper limit unit is used for configuring the upper limit amplitude of the full-swing signal pair according to the switch signal;
The lower limit unit is used for configuring the lower limit amplitude of the full-swing signal pair according to the switch signal.
2. The switching device according to claim 1, wherein,
The first output node is coupled with the control end of the first forward switching tube and the control end of the first reverse switching tube through a first bias resistor;
The second output node is coupled to the second forward switching tube and the control end of the second reverse switching tube through a second bias resistor.
3. The switching device according to claim 1, wherein,
The first forward switching tube and the second forward switching tube are NMOS tubes;
The first reverse switching tube and the second reverse switching tube are PMOS tubes.
4. The switching device according to claim 1, wherein,
The second switch unit comprises a first sampling resistor and a second sampling resistor;
the first sampling resistor and the second sampling resistor are connected in series between the differential signal pairs;
The first sampling resistor and the second sampling resistor are configured to output the switching signal.
5. The switching device according to claim 1, wherein,
The upper limit unit includes:
The input end of the power switch tube is coupled with an external power supply, the output end of the power switch tube is coupled with the input ends of the first reverse switch tube and the second reverse switch tube, and the control end inputs the switch signal.
6. The switching device according to claim 5, wherein,
The control end of the power switch tube inputs the switch signal through an inverter.
7. The switching device according to claim 1, wherein,
The lower limit unit includes:
And the input end of the grounding switch tube is coupled with the output ends of the first forward switch tube and the second forward switch tube, the output end of the grounding switch tube is grounded, and the control end of the grounding switch tube inputs the switch signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811650006.8A CN109831203B (en) | 2018-12-31 | 2018-12-31 | Switching device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811650006.8A CN109831203B (en) | 2018-12-31 | 2018-12-31 | Switching device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109831203A CN109831203A (en) | 2019-05-31 |
| CN109831203B true CN109831203B (en) | 2024-09-10 |
Family
ID=66860050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811650006.8A Active CN109831203B (en) | 2018-12-31 | 2018-12-31 | Switching device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109831203B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381747A (en) * | 2021-08-13 | 2021-09-10 | 上海奥令科电子科技有限公司 | High-speed low-swing level conversion circuit |
| CN118300597B (en) * | 2024-06-04 | 2024-08-16 | 瓴科微(上海)集成电路有限责任公司 | Anti-interference LVDS common mode feedback circuit |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1274171A1 (en) * | 2001-07-05 | 2003-01-08 | Telefonaktiebolaget L M Ericsson (Publ) | Differential line receiver |
| JP2006287305A (en) * | 2005-03-31 | 2006-10-19 | Matsushita Electric Ind Co Ltd | Voltage comparator |
| CN101304251B (en) * | 2008-05-30 | 2010-06-02 | 西安电子科技大学 | Differential interface circuit for on-chip long-wire interconnection |
| US8471601B2 (en) * | 2008-06-20 | 2013-06-25 | Cavium, Inc. | Single-ended to differential converter |
| KR101572483B1 (en) * | 2008-12-31 | 2015-11-27 | 주식회사 동부하이텍 | transmitter |
| US8116149B2 (en) * | 2009-04-14 | 2012-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit and method for small swing memory signals |
| US7759977B1 (en) * | 2009-06-08 | 2010-07-20 | Mediatek Inc. | Buffering circuit |
| US7990178B2 (en) * | 2009-12-01 | 2011-08-02 | Himax Imaging, Inc. | Driving circuit with impedence calibration |
| JP5581913B2 (en) * | 2010-09-06 | 2014-09-03 | ソニー株式会社 | Driver amplifier circuit and communication system |
| US9093987B1 (en) * | 2012-09-28 | 2015-07-28 | Xilinx, Inc. | Differential level shifter for improving common mode rejection ratio |
| CN103095224A (en) * | 2013-01-29 | 2013-05-08 | 天津大学 | Complementary metal-oxide-semiconductor transistor (CMOS) broadband low-noise amplifier adopting noise cancellation technology |
| CN103532497B (en) * | 2013-10-18 | 2016-08-24 | 中国科学技术大学 | A kind of ultra-wideband low-noise amplifier using inductance compensation technology |
| CN104124923B (en) * | 2014-06-25 | 2017-04-05 | 中国电子科技集团公司第三十八研究所 | A kind of low-noise mixer circuit |
| CN107870647A (en) * | 2016-09-22 | 2018-04-03 | 联发科技（新加坡）私人有限公司 | Pre-driver circuit |
| CN107979367A (en) * | 2017-12-14 | 2018-05-01 | 上海玮舟微电子科技有限公司 | A kind of high speed long arc differential driver and differential data interface system |
-
2018
- 2018-12-31 CN CN201811650006.8A patent/CN109831203B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109831203A (en) | 2019-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1758540B (en) | Comparator with output offset correction and metal oxide semiconductor logic circuit | |
| JP5090494B2 (en) | Low phase noise amplifier | |
| US20100301920A1 (en) | Mixer with high linearity | |
| CN101404481B (en) | Semiconductor circuit | |
| CN104426523A (en) | Waveform transformation circuit with reduced jitter | |
| CN109831203B (en) | Switching device | |
| CN100527619C (en) | Comparator circuit | |
| US7573302B2 (en) | Differential signal comparator | |
| US6229346B1 (en) | High frequency supply compatible hysteresis comparator with low dynamics differential input | |
| JP6102620B2 (en) | Duty cycle correction circuit | |
| KR19990077574A (en) | Oscillating circuit | |
| CN101453195A (en) | Method for improving common mode feedback stability by using grounding capacitor | |
| JP2009089059A (en) | Light receiving circuit | |
| KR101055788B1 (en) | A differential amplifier circuit having a wide bandwidth common mode input voltage range and an input buffer including the differential amplifier circuit | |
| KR101055850B1 (en) | Complementary circuit improves noise and distortion characteristics | |
| TWI790325B (en) | Self-biased amplifier | |
| CN107070437B (en) | Pulse width stabilizing circuit | |
| JP5195145B2 (en) | Differential amplifier | |
| CN114039560B (en) | Operational amplifier and output stage circuit thereof | |
| CN113595512B (en) | High linearity low noise amplifier | |
| JP3667616B2 (en) | Level conversion circuit | |
| JP6230903B2 (en) | Low noise amplifier | |
| CN113541619B (en) | Differential amplifier | |
| JP4623286B2 (en) | Duty adjustment circuit | |
| JPWO2012124106A1 (en) | Differential current source and differential current mirror circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20211122 Address after: 519000 room 901-9011, Hengqin international business center, No. 3000, Huandao East Road, Hengqin new area, Zhuhai, Guangdong Applicant after: Core microelectronics technology (Zhuhai) Co.,Ltd. Address before: 430000, No.1, floor 1-5, building 14, No.7, financial port 1st Road, Donghu New Technology Development Zone, Wuhan City, Hubei Province Applicant before: INNOSILICON TECHNOLOGY Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |