CN109829192B - Reference model construction method and device for processor computing unit - Google Patents

Abstract

The application provides a reference model construction method and a device for a processor computing unit, wherein the method comprises the following steps: acquiring a calculation function instruction, a control function and an interface function of a processor calculation unit; establishing a calculation model of a processor calculation unit according to the calculation function instruction; configuring a control model of the calculation model according to the control function; and configuring a model interface of the calculation model according to the interface function, and generating a reference model of the processor calculation unit. By implementing the application, the reference model established according to the actual calculation function instruction, the control function and the interface function has good consistency with the calculation unit in the real processor, so that the complete simulation verification of the calculation process of all calculation instructions in the calculation unit can be realized, and the problem of difficult function verification of the calculation unit can be solved by utilizing the reference model.

Description

A reference model construction method and device for a processor computing unit

Technical field

The invention relates to the field of computers, and in particular to a reference model construction method and device for a processor computing unit.

Background technique

In the design of the processor, the vector scalar computing unit, referred to as the computing unit, is the functional unit that best reflects the computing power of the processor. Its functions are complex (including simple fixed/floating point calculations, complex fixed/floating point calculations, data replacement, fixed and floating point conversions). , division/square root calculation, valuation calculation, decimal floating point calculation, encryption calculation and internal instruction decoding, control flow, data flow implementation, etc.), most of the calculation instructions of the instruction set must be implemented in it; therefore, for the computing unit Functional verification has always been a difficult problem. How to have a reference model with accurate calculation and complete functions in the functional verification of computing units is the key to solving the problem. Traditional MCU class models do not support the verification of complex computing function instructions such as floating point and vector calculations. Reference models that rely on external hardware devices may support complex calculations such as floating point and vector calculations, but they can only provide results and are not intuitive. Controlling and simulating the data flow and control flow cannot completely verify the instruction calculation process.

Contents of the invention

Embodiments of the present invention provide a reference model construction method and device for a processor computing unit to overcome the single verification function implemented by the reference model of the computing unit in the prior art and the inability to calculate all computing instructions in the computing unit. The process is fully verified.

Embodiments of the present invention provide a reference model construction method for a processor computing unit, which includes: obtaining computing function instructions, control functions and interface functions of the processor computing unit; establishing a reference model of the processor computing unit according to the computing function instructions. A computing model; a control model that configures the computing model according to the control function; a model interface that configures the computing model according to the interface function and generates a reference model of the processor computing unit.

Optionally, establishing a computing model of the processor computing unit according to the computing function instructions includes: obtaining parameter information of each computing function instruction; and establishing a computing model of each computing function instruction based on each of the parameter information. Instruction model: integrate each of the instruction models according to the corresponding computing instructions to generate the computing model.

Optionally, establishing the computing model of the processor computing unit according to the computing function instructions further includes: using a real processor to verify the computing model; when the verification fails, returning the computing model according to each The above parameter information is used to establish the steps of instruction model for each calculation function instruction.

Optionally, establishing the computing model of the processor computing unit according to the computing function instructions further includes: when the verification is passed, returning to the step of configuring the control model of the computing model according to the control function.

Optionally, the reference model construction method of the processor computing unit also includes: performing simulation verification on the model interface of the reference model; when the simulation verification fails, returning the calculation function instruction according to the The step of establishing a computing model of the processor computing unit.

Optionally, the reference model construction method of the processor computing unit further includes: when the simulation verification passes, determining the reference model that passes the simulation verification as the reference model of the processor computing unit.

Optionally, the reference model construction method of the processor computing unit further includes: obtaining verification functional requirements of the processor computing unit; and configuring a functional verification interface for the reference model according to the verification functional requirements.

Embodiments of the present invention also provide a reference model construction device for a processor computing unit, including: a function acquisition module for obtaining computing function instructions, control functions and interface functions of the processor computing unit; and a computing model construction module for Establish a computing model of the processor computing unit according to the computing function instructions; a control model configuration module for configuring the control model of the computing model according to the control function; a model interface configuration module for configuring the control model according to the interface function Configure the model interface of the computing model and generate a reference model of the processor computing unit.

Embodiments of the present invention also provide a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores computer instructions. The computer instructions are used to cause the computer to execute the above-mentioned processor calculation unit. Reference model construction method.

An embodiment of the present invention also provides a computer device, including: at least one processor; and a memory communicatively connected to the at least one processor, wherein the memory stores instructions that can be executed by the at least one processor, The instructions are executed by the at least one processor, so that the at least one processor executes the above-mentioned reference model construction method of the processor computing unit.

The technical solution of the present invention has the following advantages:

Embodiments of the present invention provide a method for building a reference model of a processor computing unit. The method establishes a computing model of the processor computing unit according to the computing function instructions of the processor computing unit, and establishes a computing model based on the control function and interface function of the computing unit. Configure the corresponding control model and model interface for the above computing model in turn, and then establish a reference model of the processor computing unit. Therefore, through the reference model established based on the actual computing function instructions, control functions and interface functions, the established reference model has good consistency with the computing unit in the real processor, and the calculation of all computing instructions in the computing unit can be realized. The process is fully simulated and verified, and the reference model can be used to solve the difficult problem of verifying the function of the computing unit.

Description of the drawings

In order to more clearly explain the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort.

Figure 1 is a flow chart of a reference model construction method of a processor computing unit in an embodiment of the present invention;

Figure 2 is a specific flow chart for establishing a computing model of a processor computing unit according to computing function instructions in an embodiment of the present invention;

Figure 3 is another flow chart of a reference model construction method of a processor computing unit in an embodiment of the present invention;

Figure 4 is a schematic structural diagram of the reference model in the embodiment of the present invention;

Figure 5 is a schematic structural diagram of a reference model construction device of a processor computing unit in an embodiment of the present invention;

Figure 6 is a schematic structural diagram of a computer device in an embodiment of the present invention.

Detailed ways

The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

Example 1

An embodiment of the present invention provides a reference model construction method for a processor computing unit. As shown in Figure 1, the reference model construction method for a processor computing unit includes:

Step S1: Obtain the computing function instructions, control functions and interface functions of the processor computing unit. Specifically, in practical applications, the computing unit in the processor can be divided into computing functions and control functions according to its functional implementation. For example, instructions such as scalar fixed, floating point computing instructions, vector fixed floating point computing instructions, etc. belong to computing instructions. , instruction decoding, data flow control, status bit update, etc. are control functions.

Step S2: Establish a computing model of the processor computing unit according to the computing function instructions. According to each computing function instruction in the above-mentioned computing unit, the function interface of each computing function instruction is defined according to the format set in the preset instruction set, and the corresponding instruction function is used to implement the function of each instruction to complete the relevant calculations and status bits. Generate, and finally integrate each instruction, and implement decoding and independent calling, thereby establishing the computing model of the computing unit.

Step S3: Configure the control model of the calculation model according to the control function. In practical applications, when the above-mentioned computing model implements corresponding computing function instructions, it is necessary to determine the acquisition location of the data source, the flow direction of the data, and the storage location of the calculation results. These operations are usually implemented through the above-mentioned control functions. Specifically, according to The processor computing unit controls the corresponding control functions required during the execution of each computing function instruction in the actual application process, uses corresponding control functions to implement each control function, and combines the control model composed of each control function with the above-mentioned The computing models are integrated to form a fully functional computing model.

Step S4: Configure the model interface of the computing model according to the interface function, and generate a reference model of the processor computing unit. In practical applications, in order for the finally established reference model to fully simulate the processor computing unit, the model interface of the above-mentioned computing model needs to be consistent with the actual interface of the processor computing unit, and the above-mentioned calculations are configured according to the interface functions of the above-mentioned computing unit. The model interface of the model obtains a reference model that is completely equivalent to the processor computing unit.

Through the above steps S1 to S4, the reference model construction method of the processor computing unit according to the embodiment of the present invention establishes the computing model of the processor computing unit according to the computing function instructions of the processor computing unit, and establishes the computing model according to the control function of the computing unit. and interface functions in turn configure the corresponding control model and model interface for the above computing model, and then establish a reference model of the processor computing unit. Therefore, through the reference model established based on the actual computing function instructions, control functions and interface functions, the established reference model has good consistency with the computing unit in the real processor, and the calculation of all computing instructions in the computing unit can be realized. The process is fully simulated and verified, and the reference model can be used to solve the difficult problem of verifying the function of the computing unit.

Specifically, in one embodiment, the above-mentioned step S1 obtains the computing function instructions, control functions and interface functions of the processor computing unit. In practical applications, the functions of the processor computing unit are complex, including both scalar calculations and vector operations, both fixed-point operations and floating-point operations. According to the functions, the operations performed by the computing unit can be divided into calculation instructions and control class function.

In a preferred embodiment, as shown in Figure 2, the above-mentioned step S2 establishes a computing model of the processor computing unit according to the computing function instructions, which specifically includes:

Step S21: Obtain parameter information of each computing function instruction. In practical applications, the parameter information of each computing function instruction includes the computing function information implemented by the computing function instruction, the specified data format information, the corresponding instruction interface information of the instruction, etc.

Step S22: Establish instruction models for each computing function instruction based on each parameter information. Specifically, in practical applications, C language can be used to perform function programming based on the above parameter information to realize the calculation function of the calculation function instruction. Taking the addition instruction in a simple fixed-point/floating-point computing unit as an example, the instruction sequence number format of the addition instruction in the instruction set is {[0:5],[6:10],[11:15],[ 16:20],[21:31]}={4,VRT,VRA,VRB,384}, and then define the function interface of the instruction (such as the decoded information, status register, and physical register that require the above instruction sequence number etc.), and use C functions to implement the instruction function, complete relevant calculations and status bit generation, and then complete the instruction model of the addition operation instruction. Specifically, the C function implementation of each of the above calculation function instructions is an existing technology and will not be described again here.

Step S23: Integrate each instruction model according to each corresponding computing instruction to generate a computing model. In practical applications, the various computing function instructions implemented above are integrated according to the functions implemented. Specifically, the integration method is integrated through a unified instruction decoding, execution pipeline structure, and unified register resource scheduling architecture. The computing unit reference model is obtained and each computing function instruction is decoded and independently called. All the above computing function instructions are integrated to form the above computing model.

Step S24: Use a real processor to verify the computing model. In practical applications, the above-mentioned processor computing unit is the processor in the Power server real machine. Each computing function instruction implemented in the above computing model has been implemented in the Power server real machine. Therefore, it can be used with the Power server real machine. The computer instructions perform theoretical value verification to determine whether each computing function instruction implemented by the above-mentioned computing model is consistent with the actual processor computing unit. Specifically, taking the above addition operation instruction as an example, the power server real machine has already implemented this instruction. A large number of random source operands VRA and VRB can be input into the computing model and the Power server real machine to see the destination operands of both. Whether the VRT and system status register results are consistent, thereby verifying the accuracy of the above calculation model. If the verification passes, step S3 is executed.

When the verification fails, return to step S22. In practical applications, if a real processor is used to verify the above calculation model and the verification fails, it means that there is an error between the calculation model and the calculation function instructions implemented by the calculation unit of the real processor, and it is necessary to analyze the reasons and re- Establish the instruction model of each computing function instruction and correct the relevant operations until the established computing model passes the verification of the real processor, thereby ensuring the consistency between the established computing model and the real processor, and providing a basis for subsequent calculations of the real processor Units provide an accurate model basis for functional verification.

Specifically, in one embodiment, the above-mentioned step S3 configures the control model of the calculation model according to the control function. In practical applications, the above control functions include: pipeline control, bypass control, status register read and write control, status bit update and other functions. Each control function is implemented with a C function by referring to the above calculation function instructions to obtain the above calculation The control model of the model.

Specifically, in one embodiment, the above-mentioned step S4 configures the model interface of the computing model according to the interface function to generate a reference model of the processor computing unit. In practical applications, in order to obtain a reference model that is completely equivalent to the processor calculation unit, it is necessary to refer to the interface function of the processor calculation unit, select the corresponding configuration parameters, and define the same data compression format to combine the above calculation model and control model. The interface signals are packaged and interconnected to form a reference model for the interface with the processor computing unit. Through the unified interfaces, parameters and data structures defined above, the control model and computing model implemented above are integrated to form a complete functional reference model, and the reference model interface is consistent with the interface of the processor computing unit.

In a preferred embodiment, as shown in Figure 3, the above-mentioned reference model construction method of the processor computing unit also includes:

Step S5: Perform simulation verification on the model interface of the reference model. In practical applications, in order to ensure that the interface of the established reference model is consistent with the interface of the processor computing unit, the functions of the above reference model need to be simulated and verified through the existing simulation platform.

Step S6: When the simulation verification is passed, the reference model that has passed the simulation verification is determined as the reference model of the processor computing unit. This means that the reference model is a consistent reference model of the processor computing unit, and the reference model can be used for simulation/formal verification applications of the processor computing unit. The simulation call of this reference model is consistent with the functions implemented by the processor computing unit.

When the simulation verification fails, return to step S2. In practical applications, if the simulation verification fails, it means that there is a certain error in the design of the reference model. After analyzing the error, the above calculation model needs to be readjusted until the simulation verification passes. Thus, the consistency of the finally generated reference model and the processor computing unit is further ensured through the above steps of simulation verification.

Specifically, in actual applications, if the above reference model is applied to a specific verification scenario, interfaces with specific functions can also be added to the above reference model to adapt to the actual verification scenario, such as: input and output data structures Compression format, etc.

The reference model established through the above reference model construction method of the processor computing unit is shown in Figure 4. The details of the basic component modules of the reference model are as follows:

Input signal interface module (IOP_STRUCT), which is a structure named IOP_Desc, including the control signal transmitted by the ISU and the data and related signals of the LSU.

Output signal interface module (VSU_OUT_STRUCT), this module is a structure named VSU_OUT, including output signals such as instruction execution status, Store data output and ecc error.

Instruction decoding module (DECODE) determines the decoding of instructions by the IOP members vs_route and vs_iop, and then enters the instruction execution module.

The data channel control module (Data_flow_control) mainly includes data flow selection functions such as global bypass and localbypass.

The instruction execution module (VSU) is responsible for the execution of instruction functions and register access and other operations. The operating process is controlled by the IOP signal. It obtains the operand from the data channel and writes the execution result back to the data channel. The instruction execution status is output through the above-mentioned output signal interface module.

The SAR module implements the functions of SAR (software architecture register), swap cast-in, swapcast-out, completion cast-out and sar bypass.

The VRF module implements the functions of VRF (vector register file), vrf cast-in, vrf cast-out, load LU data and write the results back to VRF and other functions.

The error checking and correction module (ECC), including the ECC gen and ECC check modules, mainly performs ECC processing of data.

The FMT module formats the input LU data and then loads it into the data pipeline, and formats the output data before outputting it.

The relevant information referenced and used in the above reference model construction method of the processor computing unit will be further described below in conjunction with the specific application process.

Retention of functional integrity: The vector scalar computing unit is usually integrated inside the core (processor core). Its functions include RTL implementation of corresponding instructions in the instruction set, FMT data formatting, ECC, and internal register file (VRF, SAR) data flow. Control (local_bypass, global_bypass), decoding and other functions.

Computer modeling language used: Use software language to establish aperiodic accurate functional reference models for computing units implemented by hardware RTL, and its functional simulation will hardly take up the overall simulation time; use DPI interface (Direct Programming interface, direct programming interface) Perform in-depth inspection and determine its legality by inspecting the payload of the message), which can be connected to the verification environment of systemverilog (referred to as SV language, which is a language based on the Verilog language), and access the shared memory area. data. In the embodiment of the present invention, the computing unit modeling implemented in C language can be easily used to calibrate and verify the real machine of the target architecture server (such as Power server) using the embedded assembly instructions to call the actual instruction set. After the verification is completed, this The C model simulates the exact instruction function to be implemented.

Processing of vector data types: For the 128-bit vector data type in the Power instruction set (the basic data type in the vector supports fixed point, single and double precision floating point), the corresponding data type in the C model is implemented by a union to facilitate each unit. Instructions with multiple data are used.

Correctness calibration of calculation function instructions: Before establishing the reference model, the vector scalar calculation instructions (the C implementation of the corresponding instruction function of the instruction set) will be calibrated in advance using the Power server. The specific calibration process is an existing technology and will not be discussed here. Let’s go into details.

Input and output data types of the reference model: In the embodiment of the present invention, the computing unit reference model is implemented in C; the input and output signals are implemented in a structure. For the convenience of subsequent verification, the output structure is in the form of an embedded structure array. Register arrays with a large amount of data such as VRF and SAR are all output from the output structure, as shown by the dotted line in Figure 4, which facilitates the verification platform to query all internal theoretical values of the vector scalar calculation unit.

Data planning of the reference model: the design of the structural data of the interface of the reference model in the embodiment of the present invention; taking into account the signal type and bit width on the systemverilog side of the DPI interface, as well as the basic data type on the C function side, as well as VRF and SAR is a register array structure array with a large amount of data; the following interface data structure is used: data with a data size less than 4 bytes uniformly uses the 4 byte data type; the largest structure element is placed at the front of the structure, and the small one is placed at the back. After the order of elements is fixed, it is convenient for the systemverilog side to arrange its data structure reasonably.

Use of the reference model: The reference model constructed according to the reference model construction method of the processor computing unit provided by the embodiment of the present invention can be directly connected and called with the systemverilog verification environment using the DPI interface; after multiple calls to the pipeline in the simulation, the VRF can All calculation results are stored; the systemverilog side can easily access all VRF values in the reference model, which greatly facilitates verification.

Specifically, referring to the reference model in Figure 4, its application example process is as follows: first, initialize the reference model; then, detect whether the input signal interface module (IOP) is valid; if valid, load the data to the VRF module, and the VRF module outputs The corresponding data is given to the SAR module, and then the VSU module decodes the corresponding calculation function instructions, obtains the corresponding operands, calculates and executes the corresponding calculation function instructions, and finally writes the calculation results back to the VRF module, and passes the above output The signal interface module outputs the results.

Through the above-mentioned steps S1 to S6, the reference model construction method of the processor computing unit provided by the embodiment of the present invention has good consistency with the computing unit in the real processor, and can realize the calculation of the computing unit in the computing unit. The calculation process of all calculation instructions is completely simulated and verified, and the reference model can be used to solve the difficult problem of verifying the function of the calculation unit. The corresponding computing function instructions of the instruction set implemented through the C function can be checked and calibrated with the real machine of the target architecture server, and can provide accurate theoretical values as a reference for the RTL design of the computing unit to accurately verify the functional results; it can not only have real The accuracy of the machine hardware device can also be separated from the hardware device and used independently in verification. In addition, the reference model established through this construction method can access all the values of VRF and SAR inside the reference model from the DPI interface. While checking the results of specific instructions, it can also implement the function of detecting changes in VRF and other registers.

Example 2

An embodiment of the present invention provides a reference model construction device for a processor computing unit. As shown in Figure 5, the reference model construction device for a processor computing unit includes:

Function acquisition module 1 is used to acquire computing function instructions, control functions and interface functions of the processor computing unit. For details, please refer to the relevant description of step S1 in Embodiment 1.

The computing model building module 2 is used to establish the computing model of the processor computing unit according to the computing function instructions. For details, please refer to the relevant description of step S2 in Embodiment 1.

The control model configuration module 3 is used to configure the control model of the calculation model according to the control function. For details, please refer to the relevant description of step S3 in Embodiment 1.

The model interface configuration module 4 is used to configure the model interface of the computing model according to the interface function and generate a reference model of the processor computing unit. For details, refer to the relevant description of step S4 in Embodiment 1.

Through the cooperation of the above components, the reference model construction device of the processor computing unit provided by the embodiment of the present invention establishes the computing model of the processor computing unit according to the computing function instructions of the processor computing unit, and establishes the computing model of the processor computing unit based on the computing function instructions of the computing unit. The control function and interface function configure the corresponding control model and model interface for the above-mentioned computing model in turn, thereby establishing a reference model of the processor computing unit. Therefore, through the reference model established based on the actual computing function instructions, control functions and interface functions, the established reference model has good consistency with the computing unit in the real processor, and the calculation of all computing instructions in the computing unit can be realized. The process is fully simulated and verified, and the reference model can be used to solve the difficult problem of verifying the function of the computing unit.

Example 3

Embodiments of the present invention provide a non-transitory computer storage medium. The computer storage medium stores computer executable instructions. The computer executable instructions can execute the reference model construction method of the processor computing unit in any of the above method embodiments, wherein , the above storage media can be magnetic disks, optical disks, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), flash memory (Flash Memory), hard disk (HardDisk Drive, Abbreviation: HDD) or solid-state drive (Solid-State Drive, SSD), etc.; the storage medium may also include a combination of the above types of memories.

Those skilled in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed When doing so, it may include the processes of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

Example 4

An embodiment of the present invention provides a computer device, the schematic structural diagram of which is shown in Figure 6. The computer device includes: one or more processors 410 and a memory 420. In Figure 6, one processor 410 is taken as an example.

The above-mentioned computer device may also include: an input device 430 and an output device 440.

The processor 410, the memory 420, the input device 430 and the output device 440 may be connected through a bus or other means. In FIG. 6, connection through a bus is taken as an example.

The processor 410 may be a central processing unit (Central Processing Unit, CPU). The processor 410 may also be another general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field-Programmable Gate Array, FPGA), or Other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components and other chips, or combinations of the above types of chips. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

As a non-transitory computer-readable storage medium, the memory 420 can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the reference model construction method of the processor computing unit in the embodiment of the present application. Program instructions/modules, the processor 410 executes various functional applications and data processing of the server by running non-transient software programs, instructions and modules stored in the memory 420, that is, the processor computing unit that implements the above method embodiments Reference model construction method.

The memory 420 may include a storage program area and a storage data area, wherein the storage program area may store an operating system and an application program required for at least one function; the storage data area may store the processing device according to the reference model construction method of the processor computing unit. Use the created data, etc. In addition, memory 420 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 420 may optionally include a memory located remotely relative to the processor 410, and these remote memories may be connected to a reference model building device of the processor's computing unit through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.

The input device 430 may receive input numeric or character information and generate key signal input related to user settings and functional control of the processing device of the reference model building operation of the processor computing unit. The output device 440 may include a display device such as a display screen.

One or more modules are stored in the memory 420, and when executed by one or more processors 410, the methods shown in Figures 1-4 are performed.

The above-mentioned products can execute the methods provided by the embodiments of the present invention, and have corresponding functional modules and beneficial effects for executing the methods. For technical details that are not described in detail in the embodiments of the present invention, please refer to the relevant descriptions in the embodiments shown in FIGS. 1 to 4 .

Obviously, the above-mentioned embodiments are only examples for clear explanation and are not intended to limit the implementation. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. An exhaustive list of all implementations is neither necessary nor possible. The obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims (10)

1. A reference model construction method for a processor computing unit, which is characterized by including: Obtain the computing function instructions, control functions and interface functions of the processor computing unit; Establish a computing model of the processor computing unit according to the computing function instructions; Use a real processor to verify the computing model; when the verification passes, configure the control model of the computing model according to the control function; Configure the model interface of the computing model according to the interface function; Integrate the control model and the model interface with the computing model respectively to form a reference model of the processor computing unit; Perform simulation verification on the model interface of the reference model; when the simulation verification passes, determine the reference model that has passed the simulation verification as the reference model of the processor computing unit; The reference model includes: input signal interface module, output signal interface module, instruction decoding module, data channel control module, instruction execution module, VRF module, SAR module, error checking and correction module, and FMT module; The input signal interface module receives data and computer function instructions; The instruction decoding module receives the computing function instruction and decodes it to obtain the corresponding computing function instruction decoding; The instruction execution module receives the corresponding computing function instruction decoding output by the instruction decoding module and receives the operand output by the data channel control module, so as to perform the decoding according to the corresponding computing function instruction decoding and the Operand calculation executes corresponding calculation function instructions to obtain calculation results; The data channel control module receives the calculation results output by the instruction execution module and transmits them to the output signal interface module; The VRF module is used to load the data output by the input signal interface module and receive the calculation results output by the data channel control module; The SAR module is used to store the data output by the input signal interface module and the calculation results output by the VRF module; The error checking and correction module performs error checking and correction processing on the input data; The FMT module formats the input data; The output signal interface module outputs the calculation result. 2. The reference model construction method of the processor computing unit according to claim 1, characterized in that, establishing the computing model of the processor computing unit according to the computing function instructions includes: Obtain the parameter information of each of the calculation function instructions; Establish instruction models for each computing function instruction based on each of the parameter information; The instruction models are integrated according to the corresponding computing instructions to generate the computing model. 3. The reference model construction method of the processor computing unit according to claim 2, characterized in that establishing the computing model of the processor computing unit according to the computing function instructions further includes: Verify the computing model using a real processor; When the verification fails, return to the step of establishing instruction models for each computing function instruction based on each of the parameter information. 4. The method for building a reference model of a processor computing unit according to claim 3, further comprising: When the verification is passed, return to the step of configuring the control model of the calculation model according to the control function. 5. The method for building a reference model of a processor computing unit according to claim 1, further comprising: Conduct simulation verification on the model interface of the reference model; When the simulation verification fails, return to the step of establishing a computing model of the processor computing unit according to the computing function instruction. 6. The method for building a reference model of a processor computing unit according to claim 5, further comprising: When the simulation verification passes, the reference model that passes the simulation verification is determined as the reference model of the processor computing unit. 7. The method for building a reference model of a processor computing unit according to claim 1, further comprising: Obtain the verification function requirements of the processor computing unit; Configure a functional verification interface for the reference model according to the verification functional requirements. 8. A device for building a reference model of a processor computing unit, which is characterized in that it includes: Function acquisition module (1), used to acquire computing function instructions, control functions and interface functions of the processor computing unit; A computing model building module (2), used to establish a computing model of the processor computing unit according to the computing function instructions; The control model configuration module (3) is used to verify the computing model using a real processor; when the verification is passed, configure the control model of the computing model according to the control function; The model interface configuration module (4) is used to configure the model interface of the computing model according to the interface function; integrate the control model and the model interface with the computing model respectively to form a processor computing unit. Reference model; perform simulation verification on the model interface of the reference model; when the simulation verification passes, determine the reference model that has passed the simulation verification as the reference model of the processor computing unit; the reference model includes: an input signal interface module, an output Signal interface module, instruction decoding module, data channel control module, instruction execution module, VRF module, SAR module, error checking and correction module, and FMT module; the input signal interface module receives data and computer function instructions; the instruction translation The code module receives the computing function instruction and decodes it to obtain the corresponding computing function instruction decoding; the instruction execution module receives the corresponding computing function instruction decoding output by the instruction decoding module and receives the data channel The operands output by the control module are used to execute the corresponding computing function instructions according to the corresponding computing function instruction decoding and the operand calculation to obtain the computing results; the data channel control module receives the operation data output by the instruction execution module. The calculation results are transmitted to the output signal interface module; the VRF module is used to load the data output by the input signal interface module and receive the calculation results output by the data channel control module; the SAR module is used to store the The data output by the input signal interface module and the calculation result output by the VRF module; the error checking and correction module performs error checking and correction processing on the input data; the FMT module formats the input data; The output signal interface module outputs the calculation result. 9. A non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and when executed by a processor, the computer instructions implement any one of claims 1-7 The reference model construction method of the processor computing unit. 10. A computer device, characterized by comprising: at least one processor (410); and a memory (420) communicatively connected with the at least one processor (410), wherein, The memory (420) stores instructions executable by the at least one processor (410), and the instructions are executed by the at least one processor (410) to cause the at least one processor (410) to execute The reference model construction method of a processor computing unit according to any one of claims 1-7.