CN109817261A - A kind of PUF circuit and its control method based on resistive formula memory - Google Patents
A kind of PUF circuit and its control method based on resistive formula memory Download PDFInfo
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Abstract
本发明公开了一种基于阻变式存储器的PUF电路及其控制方法，其中PUF电路包括两个并行的传输通路和一个判决模块，两个所述传输通路的总输入端相互连接以共同输入同一输入信号，两个所述传输通路的总输出端分别连接到所述判决模块的输入端，所述判决模块的输出端为所述PUF电路的输出端，其中两个所述传输通路分别由多个延时模块串联连接组成，所述延时模块包括阻变式存储器以通过所述阻变式存储器控制延时。本发明提出的基于阻变式存储器的PUF电路及其控制方法，大大提高了阻变式存储器的CRP效率。
The invention discloses a PUF circuit based on a resistive variable memory and a control method thereof, wherein the PUF circuit includes two parallel transmission paths and a decision module, and the total input ends of the two transmission paths are connected to each other to jointly input the same Input signal, the total output ends of the two transmission paths are respectively connected to the input end of the decision module, and the output end of the decision module is the output end of the PUF circuit, wherein the two transmission paths are respectively composed of multiple The delay modules are connected in series, and the delay module includes a resistive variable memory to control the delay through the resistive variable memory. The PUF circuit based on the resistive variable memory and the control method thereof proposed by the present invention greatly improve the CRP efficiency of the resistive variable memory.
Description
Technical field
The present invention relates to technical field of circuit design more particularly to a kind of PUF circuits and its control based on resistance-variable storing device
Method processed.
Background technique
Physics unclonable function (Physically Unclonable Function, PUF) be it is a kind of physically not
The functional relation that can be cloned.The design principle of physics unclonable function circuit is existed in the fabrication process using integrated circuit
Technological fluctuation realize, the technological fluctuation in manufacturing process will lead to mutually isostructural circuit have working characteristics on it is inclined
By the deviation signal that core builds PUF circuit of mutually isostructural circuit circuit occurs for difference, and combines remaining periphery electricity
Road, such as the random jump of different transmission paths or signal are just able to design the circuit side PUF with different function characteristic
Case.Since the building of PUF is based on the variation of physical parameter in uncontrollable manufacturing process, even if PUF circuit is knowing
In the case where all circuit details and process environments, it is also not possible to produce identical PUF circuit, that is, have can not gram
Grand characteristic, therefore PUF circuit can prevent physical attacks.
As shown in Figure 1, PUF can be generated accordingly when an input stimulus (challenge) submits to a PUF circuit
Output response (response).This response is the physical function realization by above-mentioned complexity, and this physical function
It is unique for each equipment.If identical input stimulus is given, then establishing difference on the basis of same design
PUF example will provide respectively different output response.Input stimulus and output response are commonly known as CRP herein
(Challenge Response Pair) --- test response pair, and one group of CRP can be regarded as PUF and corresponding
The fingerprint of integrated circuit or equipment.
In field of encryption, PUF has higher safety compared to software cryptography as a kind of mode of encrypted physical, and
It may be used in the applications such as digital signature, data encryption, authentication and hardware intellectual property protection, by more next
More extensive concern.It provides a simple key generation mechanism in a very small hardware device, it is easy to
Build, but it is almost impossible be replicated, therefore the superior PUF design scheme of a performance has very well in information security field
Utilization prospect.
PUF has several main performance evaluation parameters: randomness (Randomness), uniqueness (Uniqueness) and can
By property (Reliability).
Randomness: the evaluation parameter describe a PUF circuit and obtain the ratio of " 0 " and " 1 " in output response be
It is not equalization, the chance for occurring " 0 " and " 1 " in the ideal case is impartial.Use rI, lIndicate the PUF with n output responses
The binary value of the i-th bit of first of output vector of example, randomness such as formula (1).
Ideally, the value of this parameter is 50%.Wherein, n is the digit of PUF example output response vector；M is
The total number of PUF example input vector.
Uniqueness: what the parameter indicated is the ability that a PUF example distinguishes itself with other PUF examples.When
When identical input stimulus is input to different PUF examples simultaneously, the output response of these PUF examples should be different, and
This parameter be then Hamming distance between piece between the output response by different PUF examples (inter-HammingDistance:
Inter-HD average value) defines.Ideally, uniqueness is expected to be 50%, it means that is giving identical input
In the case where excitation, from two or the response of several difference PUF examples will be averagely with the different bits of half.
If RiAnd RjIt is the output response vector of two different PUF examples, then under the conditions of identical input stimulus,
Uniqueness such as formula (2).
Wherein, HD (Ri, Rj) it is RiAnd RjBetween Hamming distance；K is the total number of PUF example；N is that the output of PUF example is rung
Answer the digit of vector.
Stability: what the parameter indicated is for the same PUF practical circuit, fortune identical in input stimulus but different
Under row environment, output response keeps stable ability.Reliability such as formula (3).
In the case where giving identical input stimulus, it is assumed that for i-th of PUF practical circuit, RiThen indicate circuit reality
The optimum value of example response, this optimum value measures in normal circumstances, that is, reference environment.Then input stimulus is kept not
Become, the output response that the PUF practical circuit is measured under different running environment is RI, t, q is to change environmental testing output response
The total degree of vector.HD(Ri, Rj, t) and it is then output response RiAnd Rj, Hamming distance between t.Ideally, reliability should
It is 100%, i.e., no bit reversal.
Traditional PUF circuit based on CMOS technology is broadly divided into three categories, ring oscillator (RO-ring
Oscillator) type PUF, decision device (arbiter) type PUF and memory type PUF, next simply introduces these types of biography
The PUF structure of system.
Ring oscillation type PUF: as the widely used one kind of weight, the basic knot of ring oscillation type PUF in PUF
Structure unit is ring oscillator.The basic structure of ring oscillator odd number phase inverter as shown in Fig. 2, be made of.Due to technique
There is variation in fluctuation, chip, internal gate delay and route difference can be deposited with the difference of chip individual in process of production
It in individual difference, even if the specific location at place is different inside identical chips, can also have differences, therefore each annular vibration
Swinging device can all be shaken with a respective specific frequency, and frequency is roughly the same between different oscillators but there is subtle
Difference.RO PUF is exactly the basic function that PUF is realized using this point, and basic structure schematic diagram is as shown in Figure 3.It should
The CRP of PUF increases according to N* (N-1) namely CRP efficiency is not high.
Adjudicate type PUF: judgement type PUF also referred to as arbitrate PUF, basic circuit structure as shown in figure 4, it by two
Symmetrical transmission path is formed, and has several multiple selector to can change the transmission path of signal on two paths.Because of work
Solid discrepant presence caused by skill fluctuation, so the transmission of the gate delay of each multiple selector and every section of transmission path
Delay has nuance.Wherein, input terminal X [1] of each of input stimulus as multiple selector everywhere, X
[2], X [N] controls the state of multiple selector, i.e. whether the node-node transmission path intersects, and then controls transmission path
Variation.When same pulse is input to two transmission paths simultaneously from left side, since the difference of delay will form sequencing
Reaching right side decision device (this decision device is made of a trigger), it is assumed that it is " 1 " that upper end path pulse, which first reaches then output,
It is " 0 " that lower path pulse, which first reaches then output, this is also finally obtained output response.The difference of input stimulus will form with
Corresponding transmission path is accordingly motivated, and then forms input stimulus and the corresponding output response of output response, and this is right
It should be related to be also uniquely corresponding with specific PUF circuit.It is the PUF of an output shown in Fig. 4, by multiple same circuits and one
It rises, so that it may be extended to the PUF of long number output.
Memory type PUF: here with SRAM type PUF citing, as shown in figure 5, a six pipe unit SRAM main parts are
It is made of two phase inverters, there are two stable state 0 state and one states for tool.But when just powering on also no progress write operation,
The state of SRAM is uncertain, it may be possible to 0 state, it is also possible to one state.And in fact, due to caused by technological fluctuation
Difference existing for transistor, this makes its threshold voltage etc., and there are nuances to cause one feedback that can be better than another, when upper
Experience is shaken several times after electricity, eventually stable some state rested in " 0 " or " 1 ".And which eventually settles at
A state for specific SRAM circuit be it is random, such property makes SRAM can be used for the design of PUF circuit.It is most simple
Single method is exactly using input stimulus as the input address of SRAM storage array, and the final state for reading sram cell is as defeated
It responds out, thus constitutes the basic structure of SRAM PUF.
The function of PUF circuit is as shown in Figure 1, its circuit realizes that needs are fluctuated by physical accidental.Since MOS device is to work as
Preceding leading semiconductor device, therefore existing PUF circuit relies primarily on the technological fluctuation randomness of MOS device and designs.Such as
Above-mentioned memory type, loop oscillation type adjudicate the PUF circuit of type and are the technological fluctuation randomness by MOS device and design
's.
The disclosure of background above technology contents is only used for auxiliary and understands design and technical solution of the invention, not necessarily
The prior art for belonging to present patent application, no tangible proof show above content present patent application the applying date
In disclosed situation, above-mentioned background technique should not be taken to the novelty and creativeness of evaluation the application.
Summary of the invention
The purpose of the present invention is to provide a kind of PUF circuit and its control method based on resistive formula memory, mentions significantly
The high CRP efficiency of resistive formula memory.
In order to achieve the above object, the invention adopts the following technical scheme:
One embodiment of the present of invention discloses a kind of PUF circuit based on resistive formula memory, parallel including two
Transmission channel and a judging module, total input terminal of two transmission channels are connected with each other to input same input letter jointly
Number, total output end of two transmission channels is connected respectively to the input terminal of the judging module, the judging module it is defeated
Outlet is the output end of the PUF circuit, and transmission channel described in two of them is made of the series connection of multiple time delay modules respectively,
The time delay module includes that resistive formula memory is delayed with being controlled by the resistive formula memory.
Preferably, the quantity for the time delay module that two transmission channels include is identical.
Preferably, the time delay module includes phase inverter and the delay circuit comprising the resistive formula memory, Mei Gesuo
The input terminal and output end for stating the phase inverter of multiple time delay modules in transmission channel are sequentially connected, the delay electricity
The output end on road is connected with the ground terminal of the phase inverter.
Preferably, the delay circuit includes the first multiple selector unit, the second multiple selector unit, multichannel distribution
Device unit and two parallel resistive formula memories, wherein the input terminal of the first multiple selector unit meets institute respectively
State the read voltage V_RRAM of resistive formula memory and the reset voltage V_reset of the resistive formula memory, first multichannel
The output end of selector unit is connected to the negative terminal of two resistive formula memories, the input terminal of the demultplexer unit
The anode of two resistive formula memories is connected, the output end of the demultplexer unit is grounded and connects respectively described the
The output end of the input terminal of two multiple selector units, the second multiple selector unit connects connecing for the phase inverter
Ground terminal.
Preferably, the first multiple selector unit includes one 2 and selects 1 multiple selector or two 2 are selected 1 multichannel to select
Select device.
Preferably, the demultplexer unit includes two 1 point of 2 demultplexers or 2 points of 3 multichannels distribution
Device.
Preferably, the second multiple selector unit selects 1 multiple selector including one 2.
Preferably, the delay circuit further includes current mirror, and the current mirror is connected to the second multiple selector list
Between the output end of member and the ground terminal of the phase inverter.
Preferably, the control terminal of the first multiple selector unit and the demultplexer unit is separately connected described
The control terminal at the master control end of transmission channel, the second multiple selector unit connects the input stimulus of the time delay module.
Another embodiment of the present invention discloses a kind of control methods to above-mentioned PUF circuit, comprising the following steps:
S1: so that the input terminal of the first multiple selector unit connects the reset voltage V_ of the resistive formula memory
Reset, the output end ground connection of the demultplexer, two resistive formula memories in the delay circuit are reset
For high-impedance state；
S2: so that the input terminal of the first multiple selector unit connects the read voltage V_ of the resistive formula memory
RRAM, the output end of the demultplexer connect the input terminal of the second multiple selector unit；
S3: step S1 and S2 are carried out to each time delay module in each of the PUF circuit transmission channel
Afterwards, same input signal is inputted to two transmission channels respectively, one can be obtained from the output end of the judging module
Output response.
It compared with prior art, the beneficial effects of the present invention are: PUF circuit proposed by the present invention is deposited based on resistive formula
Resistive formula memory is arranged in time delay module to be applied to PUF circuit the distribution of resistance stochastic volatility of reservoir, thus logical
It crosses time delay module and embodies the transmission delay that the random distribution difference of resistive formula memory resistance value is converted into signal and occur, obtain
The RRAM unit CRP efficiency of PUF circuit is very high, has obtained biggish promotion compared to existing PUF circuit.
In further embodiment, current mirror is also introduced in time delay module, can be stored resistive formula by current mirror
The difference of read current size caused by resistance value of the device read current amplification to increase resistive formula memory, keeps output effect brighter
It is aobvious, so that the work of PUF circuit is more stable.
Detailed description of the invention
Fig. 1 is the input stimulus and output response of PUF circuit；
Fig. 2 is the basic structure schematic diagram of ring oscillator；
Fig. 3 is the basic structure schematic diagram of ring oscillation type PUF；
Fig. 4 is the basic structure schematic diagram for adjudicating type PUF；
Fig. 5 is the basic structure schematic diagram of SRAM type PUF；
Fig. 6 is the MIM device architecture schematic diagram of resistive formula memory；
Fig. 7 is the snapback of resistive formula memory；
Fig. 8 is the height configuration resistance value distribution of resistive formula memory；
Fig. 9 is the structural schematic diagram of the PUF circuit based on RRAM of the preferred embodiment of the present invention；
Figure 10 is the structural schematic diagram of the time delay module in Fig. 9；
Figure 11 is the structural schematic diagram of the judging module in Fig. 9；
Figure 12 is the schematic diagram of the PUF circuit based on RRAM of an example of the invention；
Figure 13 is the schematic diagram of the time delay module in Figure 12；
Figure 14 is the randomness simulation result schematic diagram for 64 PUF circuits；
Figure 15 is the simulation result schematic diagram for the PUF circuit stability in present example；
Figure 16 is the occurrence probability schematic diagram of Hamming distance in the uniqueness test for 64 PUF circuits.
Specific embodiment
Below against attached drawing and in conjunction with preferred embodiment, the invention will be further described.
Resistive formula memory (Resistive RandomAccess Memory, RRAM) is as nonvolatile memory
One is great potential, RRAM realizes the storage of binary message using the reversible switching of resistivity of material.Permitted due to existing
The materials that resistivity reversible transformation more may be implemented are very more, so easily facilitating selection is in technique preparation simplicity and simultaneous
Hold the material of CMOS technology.RRAM storage unit operating rate is fast, structure is simple, information keeps stable, low in energy consumption, it is non-easy to have
The property lost, and it is easily achieved multilevel storage and three-dimensional integration, it is more conducive to integrating compared to other kinds of memory
The raising of density.RRAM such as programming power consumption, program voltage, read or write speed, the erasable time, with CMOS technology compatibility feature, every
Position cost and High Density Integration etc. all have advantage.
RRAM device uses the sandwich structure of MIM, and structure is very simple.Two metal layers (power on up and down as shown in Figure 6
Pole 91 and lower electrode 92) it is used as electrode, centre is resistive material 93.When to application one fixed width and one between upper and lower two electrodes
After the pulse voltage of tentering degree, intermediate resistive material can be turned between two steady resistance states of high-impedance state and low resistance state
It changes, multiple pulses by a small margin also can be used and be programmed operation.The I-V characteristic curve of resistive formula memory as shown in fig. 7,
It can be seen that it is with typical hysteresis characteristic；The snapback one is divided into 4 regions: low resistance state area, high-impedance state area and two
A transition region only just can be resetted or be programmed to resistive material after voltage amplitude is more than certain threshold value, and this is compiled
The amplitude and pulse width of journey voltage are related to material property.It is detected when with the burst pulse by a small margin for being not above threshold voltage
Resistive material resistance value size and when carrying out read operation, since pulse width and amplitude are all smaller, will not state to resistance into
Row changes, i.e., will not cause to change to the data of storage.Therefore, this read operation is non-Destructive readout.According to newest text
Report is offered, RRAM can obtain biggish switch resistance ratio, can be more than 106~107.
Although there are two stable states of high-impedance state and low resistance state in RRAM, but the resistance value of its high low resistance state exists at random
Property.As shown in figure 8,100 RRAM units are measured to obtain the resistance value distribution situation of its high low resistance state, it can from figure
The high-impedance state of RRAM is bigger than low resistance state resistance value random distribution range out.Although this is one unfavorable for memory application field
Factor limits the application of RRAM to a certain extent, but becomes an advantage, PUF circuit for the application of PUF circuit
Application foundation be exactly to introduce a kind of mechanism changed at random, therefore, by resistive formula memory in the preferred embodiment of the present invention
It is introduced into PUF circuit, this is also that a kind of new thinking is provided to PUF circuit design.
As shown in figure 9, the preferred embodiment of the present invention propose a kind of physics based on resistive formula memory (RRAM) can not
Clone function (PUF) circuit, including two transmission channels 100 and a judging module 200；Two transmission channels 100 it is total defeated
Enter end to be connected with each other to input same input signal jointly, total output end of two transmission channels 100 is connected respectively to judgement mould
The input terminal of block 200, the output end of judging module 200 are the output end of PUF circuit.Two of them transmission channel 100 is simultaneously
An identical signal is transmitted, the input terminal of judging module 200, judging module 200 are reached eventually by different delay competitions
For adjudicating the sequencing for transmitting signals to and reaching, to judge which transmission channel 100 transmits signal faster.Wherein C1,
C2 ..., C (2n) be PUF input terminal, and " output response " is the output end of PUF；Every transmission channel 100 is all prolonged by n
When module 10 be composed in series, every grade delay by RRAM element characteristics control.
The structure of the time delay module 10 of the present embodiment is as shown in Figure 10, the time delay module 10 include phase inverter 11 and comprising
The delay circuit of RRAM unit, the input terminal (V_ of the phase inverter 11 of the n time delay module 10 in each transmission channel 100
Pulse) and output end (delay pulse) is sequentially connected so that composition transmission channel 100 is connected in series in n time delay module 10；Instead
The power supply termination voltage Vdd of phase device 11, the ground terminal of phase inverter 11 are connected with the output end of delay circuit.Delay circuit includes two
A 2 select 1 multiple selector 121, two, 122, two 1 point of RRAM unit, 2 demultplexer to select 1 multiple selector for 123, one 2
124 and a current mirror 125, two RRAM units 122 be connected in parallel, two 2 are selected the input terminal of 1 multiple selector 121 to distinguish
Meeting V_RRAM and V_reset, (two of them 2 select the input " 0 " of 1 multiple selector 121 to hold and meet V_RRAM respectively, input " 1 " end
V_reset is met respectively), V_RRAM is the read voltage of RRAM unit 122, can carry out non-Destructive readout to RRAM unit 12；V_
Reset is the reset voltage of RRAM unit 122, can set high-impedance state for RRAM unit 122；Select 1 multiple selector for two 2
121 output end is separately connected the negative terminal of two RRAM units 122；The input terminal of two 1 point 2 demultplexers 123 connects respectively
The anode of two RRAM units 122 is connect, the output end of two 1 point 2 demultplexers 123 is grounded and connects respectively 2 and 1 multichannel is selected to select
Select the input terminal of device 124, two of them 1 divide the output " 0 " of 2 demultplexers 123 to hold to be separately connected 2 and select 1 multiple selector 124
Input terminal, output " 1 " end be grounded respectively；2 select the input " 0 " of 1 multiple selector 124 to terminate corresponding one of RRAM unit
Output " 0 " end (the upper surface of corresponding RRAM unit as shown in Figure 10) of 1 point of 2 demultplexer 123 of 122 anode, it is defeated
Enter " 1 " and terminates output " 0 " end for corresponding to 1 point of 2 demultplexer 123 of anode of another RRAM unit 122 (such as Figure 10 institute
Show the RRAM unit below corresponding), 2 select the input terminal of the output end connection current mirror 125 of 1 multiple selector 124, electric current
The ground terminal of the output end connection phase inverter 11 of mirror 125.Two of them 2 select 1 multiple selector 121 and two 1 point of 2 multichannel distribution
The control terminal of device 123 co-owns the same control terminal V_ctrl respectively, and 2 select the control terminal of 1 multiple selector 124 to connect delay
Module input stimulus C (corresponding in Fig. 9 C1, C2 ..., any one in C (2n)).
When V_ctrl is " 1 ", two 2 are selected 1 multiple selector 121 to be all switched to V_reset signal, and at the same time two
A 1 point of 2 demultplexer 123 is switched to GND, and two RRAM units 122 are reset to high-impedance state；When V_ctrl is " 0 ", two
A 2 select 1 multiple selector 121 to be switched to V_RRAM signal, and at the same time two 1 point 2 demultplexers 123 be all switched to
2 select on the connecting path of 1 multiple selector 124.And 2 select 1 multiple selector 124 control terminal be then input stimulus input
End selects the RRAM unit 122 of lower end when control terminal is " 1 ", when control terminal is " 0 ", selects RRAM unit above
122.Thus then the resistance of RRAM unit 122 is read in a manner of read current, then accesses the time delay module 10 of next stage,
And since time delay module 10 is additionally provided with a current mirror 125 and a phase inverter 11；On the one hand by current mirror 125 that RRAM is mono-
The read current signal of member 122 is connected with 11 ground terminal of phase inverter, on the other hand by the ratio of setting current mirror 125, can incite somebody to action
The read current of RRAM unit 122 amplifies the difference of read current size caused by the resistance value to increase RRAM unit device 122, makes to export
Effect is more obvious, and the work of PUF circuit is more stable.The resistance of RRAM unit 122 controls phase inverter by current mirror 125
The 11 charge and discharge time, to embody its randomness.
Each time delay module 10 passes through the input terminal (V_pulse) of phase inverter 11 and output end (delay pulse) successively phase
Even, and two parallel transmission channels 100, in conjunction with Fig. 9, time delay module 10 of the identical pulse signal from left end are formed
11 input terminal of phase inverter be input to two transmission channels 100, input terminal of the final output to judging module 200 simultaneously；Judgement
Module 200 obtains the output of response, the i.e. output response of PUF circuit according to the sequencing that pulse signal arrives, if upper end
Transmission channel pulse first reach, then judging module 200 exports " 1 ", on the contrary then export " 0 ".Wherein the judging module 200 be by
The trigger that two NAND gates are constituted is constituted, and the output response of PUF circuit, circuit diagram can be obtained by set time sampling
As shown in figure 11.
In order to generate an output response, the PUF circuit of the preferred embodiment of the present invention works according to the following steps:
1) programming/reset (reset) stage: because the resistance value of RRAM unit is more extensive in the random distribution of high-impedance state,
Therefore in the present embodiment, the randomness of the high-impedance state of RRAM unit is utilized in PUF circuit design.Firstly, by PUF circuit
In all RRAM unit be set as high resistant, i.e., V_ctrl is set as " 1 ".RRAM unit one terminates V_reset, another termination in this way
The equal reset of RRAM unit can be then high-impedance state by GND.It should be noted that this operation is simultaneously for all RRAM units
It is operated, the resistance value of each RRAM unit is just fixed up in PUF circuit after this operation, then just needs logical
Certain operation is crossed to read out the random distribution difference of its resistance value.
2) input stimulus configuration phase: after all RRAM units are all high-impedance state by reset, V_ctrl is arranged
For " 0 ".In this way RRAM unit just and program voltage V_reset and GND disconnection, then with read voltage V_RRAM and next stage multichannel
Distributor conducting.From next stage multiple selector input stimulus in this stage, each time delay module is inputted in password
One, such input stimulus then determines the access situation of RRAM unit on two accesses, and by the difference of RRAM unit resistance value
Situation is embodied in the specific delay difference of each time delay module.If PUF circuit consumes N number of RRAM unit, each delay in total
Module consumes 2, then this PUF circuit is N/4 grades, possesses N/2 time delay module in total.One group of input stimulus chooses PUF electric
N/2 RRAM unit in road is involved in work in N/2 RRAM unit of next stage, possesses N/2 input bit in total,
Therefore, the relationship of the CRP and RRAM element number of the PUF circuit can be by following formula (4).
CRP=2N/2 (4)
3) output response generates the stage: when having configured input stimulus, that is, the RRAM unit chosen is applied to each delay mould
Left end on block and then to two transmission paths inputs pulse signal a V_pulse, V_pulse and passes through upper and lower two
It is transmitted to two input terminals of judging module after parallel delay transport access, finally obtains court verdict, is i.e. one defeated
It responds out.The resistance value difference of RRAM unit can be presented as the read current difference of each RRAM unit by the process, then via electric current
Mirror and buffer (namely phase inverter role in time delay module) are presented as the delay difference of time delay module, final to embody
On court verdict.Since the resistance value of RRAM unit is there are randomness, there is also its randomnesss for output response, this is just PUF electricity
The encrypted physical function on road provides support.
Wherein, two 2 of the delay circuit in time delay module 10 shown in Fig. 10 select 1 multiple selector 121 respective respectively
A corresponding RRAM unit 122, in order to control RRAM unit and carry out resetting operation or read operation, this two 2 are selected more than 1
The function and logic (input and output) of the corresponding alternative of road selector 121 are the same, therefore in some other realities
It applies in example, this two 2 are selected 1 multiple selector 121 1 multiple selector 121 can also be selected to substitute only with one 2, are using one
A 2 when selecting 1 multiple selector 121, this 2 selects that the input terminal of 1 multiple selector 121 meets V_RRAM respectively and V_reset is (wherein defeated
Enter " 0 " end and meet V_RRAM respectively, input " 1 " end meets V_reset respectively), the connected common connection of the negative terminal of two RRAM units 122
It 2 selects in 1 multiple selector 121 at this.In addition, two 1 point 2 demultplexers 123 are also that respectively a corresponding RRAM is mono- respectively
Member 122, in order to the resistance value of RRAM unit is exported or shielded, when RRAM unit is in (reset) state of reset,
The resistance value of RRAM unit output be it is invalid, next circuit cannot be communicated to, needed to export invalid resistance value to GND, when
When in reading state, the resistance value of RRAM unit can export to (namely 2 select 1 multiple selector to next circuit
124)；In some other embodiments, 2 points of 3 multiple selector are can also be used to replace in two 1 point 2 demultplexers 123
In generation, wherein two input terminals of 2 point of 3 multiple selector are separately connected the anode of two RRAM units, three output ends connect respectively
Two input terminals of 1 multiple selector 124 are selected in ground and connection 2, and effect is realized with two 1 point 2 demultplexers 123
Effect as, details are not described herein.
Made furtherly with PUF circuit based on resistive formula memory of the specific example to the preferred embodiment of the present invention below
It is bright.
In this example, using core world SMIC65 technology library, using RRAM device model, in Cadence emulation tool
In emulated for this design scheme parameters, circuit diagram is as shown in figure 12.The road of setting delay in this example
Diameter is three-level, i.e., six time delay modules, the schematic diagram of time delay module are as shown in figure 13 altogether.
64 PUF circuits are directed to an output response result of an input stimulus as an example, as can be seen from Figure 14
The distribution of its output response has certain randomness.
For not isotopic number randomness emulation data final calculation result it is as shown in table 1, as can be seen from Table 1 it is each not
The stochastic pattern structure of the PUF circuit of isotopic number is all close to 50%, very close to ideal situation.
The randomness simulation result of the not isotopic number PUF circuit of table 1
As shown in figure 15 for the emulation data final calculation result of stability, as can be seen from the figure the PUF circuit is steady
It is qualitative to be higher than high-temperature condition (being higher than 320K) in low temperature condition (270K~320K) stability inferior, and in positive and negative 20K of room temperature or so
It is able to maintain 96% or more stability.
Figure 16 has counted the distribution situation of the Hamming distance between 64 PUF circuits, and table 2 is then each not isotopic number RRAM
PUF circuit uniqueness final calculation result, it can be seen that close to 50%, deviation does not surpass the uniqueness of the PUF circuit arrangement
0.8% is crossed, good uniqueness is possessed.
The uniqueness simulation result of the not isotopic number PUF circuit of table 2
Each producible CRP quantity of RRAM unit average in PUF circuit based on RRAM is defined as RRAM unit CRP
Efficiency.For example, RRAM element number used in this programme is n, since each time delay module puts into two RRAM units, according to
The input condition of input stimulus, every two RRAM unit must have one working in the reading process of PUF circuit, so its
CRP quantity in total is 2n/2, with exponential increase.By the CPR sum and RRAM of the scheme in this programme and other documents in table 3
Unit CRP efficiency compares.
Relationship and RRAM unit CRP efficiency between each scheme CRP quantity of table 3 and RRAM sum n
As can be seen that the solution of the present invention compares currently existing scheme from above table, not only CRP quantity is increased with index
It is long, it increased significantly compared to other amount of projects；And RRAM unit CRP efficiency is similarly higher.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those skilled in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, several equivalent substitute or obvious modifications can also be made, and performance or use is identical, all answered
When being considered as belonging to protection scope of the present invention.
Claims (10)
1. a kind of PUF circuit based on resistive formula memory, which is characterized in that sentence including two parallel transmission channels and one
Total input terminal of certainly module, two transmission channels is connected with each other to input same input signal, two transmission jointly
Total output end of access is connected respectively to the input terminal of the judging module, and the output end of the judging module is the PUF electricity
The output end on road, transmission channel described in two of them are made of the series connection of multiple time delay modules respectively, the time delay module packet
Resistive formula memory is included to be delayed to control by the resistive formula memory.
2. PUF circuit according to claim 1, which is characterized in that the delay mould that two transmission channels include
The quantity of block is identical.
3. PUF circuit according to claim 1 or 2, which is characterized in that the time delay module includes phase inverter and comprising institute
State the delay circuit of resistive formula memory, the phase inverter of multiple time delay modules in each transmission channel it is defeated
Enter end and output end is sequentially connected, the output end of the delay circuit is connected with the ground terminal of the phase inverter.
4. PUF circuit according to claim 3, which is characterized in that the delay circuit includes the first multiple selector list
The parallel resistive formula memory of member, the second multiple selector unit, demultplexer unit and two, wherein described first
The input terminal of multiple selector unit meets the read voltage V_RRAM and the resistive formula memory of the resistive formula memory respectively
Reset voltage V_reset, the output end of the first multiple selector unit is connected to two resistive formula memories
Negative terminal, the input terminal of the demultplexer unit connect the anode of two resistive formula memories, the demultplexer
The output end of unit is grounded and connects respectively the input terminal of the second multiple selector unit, the second multiple selector list
The output end of member connects the ground terminal of the phase inverter.
5. PUF circuit according to claim 4, which is characterized in that the first multiple selector unit includes one 2 choosing
1 multiple selector or two 2 select 1 multiple selector.
6. PUF circuit according to claim 4, which is characterized in that the demultplexer unit includes two 1 point more than 2
Distributor or 2 points of 3 demultplexers.
7. PUF circuit according to claim 4, which is characterized in that the second multiple selector unit includes one 2 choosing
1 multiple selector.
8. PUF circuit according to claim 4, which is characterized in that the delay circuit further includes current mirror, the electric current
Mirror is connected between the output end of the second multiple selector unit and the ground terminal of the phase inverter.
9. PUF circuit according to claim 4, which is characterized in that the first multiple selector unit and the multichannel
The control terminal of dispenser unit is separately connected the master control end of the transmission channel, the control of the second multiple selector unit
End connects the input stimulus of the time delay module.
10. the control method of the described in any item PUF circuits of a kind of pair of claim 4 to 9, which is characterized in that including following step
It is rapid:
S1: so that the input terminal of the first multiple selector unit connects the reset voltage V_ of the resistive formula memory
Reset, the output end ground connection of the demultplexer, two resistive formula memories in the delay circuit are reset
For high-impedance state；
S2: so that the input terminal of the first multiple selector unit connects the read voltage V_RRAM of the resistive formula memory,
The output end of the demultplexer connects the input terminal of the second multiple selector unit；
S3: right after being carried out step S1 and S2 to each time delay module in each of the PUF circuit transmission channel
Two transmission channels input same input signal respectively, can obtain one output from the output end of the judging module
Response.
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