CN109815157B - Programming command processing method and device - Google Patents

Abstract

The application provides a programming command processing method and device. A method of processing a programming command is provided, comprising: sending the address to the NVM chip, and moving the data in the memory to the NVM chip; releasing the data in the memory before the NVM chip indicates that the data is successfully recorded in the address; and querying the state of the NVM chip to obtain a processing result of the programming command.

Description

Programming command processing method and device

technical field

The present application relates to storage technology, in particular, to processing programming commands of NVM chips.

Background technique

Figure 1 shows a block diagram of a solid-state storage device. The solid state storage device 102 is coupled to the host for providing storage capabilities for the host. The host and the solid-state storage device 102 can be coupled in various ways, including but not limited to, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface, small computer system interface) , SAS (Serial Attached SCSI, Serial Attached SCSI), IDE (Integrated Drive Electronics, Integrated Drive Electronics), USB (Universal Serial Bus, Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe, high-speed peripheral component interconnection), NVMe (NVM Express, high-speed non-volatile storage), Ethernet, Fibre Channel, wireless communication networks, etc. connect the host and the solid-state storage device 102 . The host may be an information processing device, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The storage device 102 includes an interface 103 , a control unit 104 , one or more NVM chips 105 and a DRAM (Dynamic Random Access Memory, dynamic random access memory) 110 .

NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), etc. are common NVMs.

The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, and the like.

The control unit 104 is used for controlling data transfer between the interface 103, the NVM chip 105 and the DRAM 110, and also for storage management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control unit 104 can be implemented in various ways of software, hardware, firmware or a combination thereof. For example, the control unit 104 can be an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit) circuit) or a combination thereof. The control unit 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control unit 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110 . The FTL table and/or cached IO command data may be stored in DRAM.

The control unit 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that follows the interface protocol of the NVM chip 105 , to operate the NVM chip 105 and receive the command execution result output from the NVM chip 105 . Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

A memory target (Target) is one or more logic units (LUN, Logic UNit) in a NAND flash memory package that share a CE (, Chip Enable, chip enable) signal. One or more dies (Dies) may be included within a NAND flash memory package. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic cell can be accessed in parallel, while multiple logic cells within a NAND flash chip can execute commands and report status independently of each other.

Data is usually stored and read in pages on a storage medium. Instead, data is erased in blocks. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page (called a physical page) on a storage medium has a fixed size, eg 17664 bytes. Physical pages can also have other sizes.

In a solid-state storage device, FTL (Flash Translation Layer, flash memory translation layer) is used to maintain mapping information from logical addresses to physical addresses. The logical address constitutes the storage space of the solid-state storage device perceived by upper-layer software such as the operating system. The physical address is the address of the physical storage unit used to access the solid state storage device. In the related art, the address mapping can also be implemented using an intermediate address form. For example, a logical address is mapped to an intermediate address, and the intermediate address is further mapped to a physical address.

A table structure that stores mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid-state storage devices. Usually, the data item of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.

The FTL table includes a plurality of FTL table entries (or entries). In one case, the correspondence between a logical page address and a physical page is recorded in each FTL table entry. In another case, each FTL table entry records the correspondence between a plurality of consecutive logical page addresses and a plurality of consecutive physical pages. In yet another case, each FTL table entry records the correspondence between the logical block address and the physical block address. In still another case, the FTL table records the mapping relationship between logical block addresses and physical block addresses, and/or the mapping relationship between logical page addresses and physical page addresses.

Large blocks include physical blocks from each of multiple logical units (LUNs), also known as logical unit groups. Each logical unit can provide one physical block for a large block. For example, in the diagram of a large block shown in Figure 2, a large block is constructed on every 16 logical units (LUNs). Each chunk consists of 16 physical blocks each from 16 logical units (LUNs). In the example of FIG. 2, chunk 0 includes physical block 0 from each of the 16 logical units (LUNs), and chunk 1 includes physical block 1 from each logical unit (LUN). Chunks can also be constructed in a variety of other ways.

For example, page stripes are constructed in large blocks, and physical pages of the same physical address within each logical unit (LUN) constitute a "page stripe". In FIG. 2 , physical pages P0-0, physical pages P0-1, . It is used to store user data, and the physical pages P0-x are used to store checksum data calculated from all user data in the stripe. Similarly, in FIG. 2 , the physical page P2-0, the physical page P2-1 . . . and the physical page P2-x constitute a page stripe 2. The physical pages used to store parity data can be located anywhere in the page stripe. As yet another example, in FIG. 3A of the Chinese patent application with the application number of 201710752321.0 and the related description of FIG. 3A in the specification, there is provided yet another construction manner of a large block.

FIG. 3A is a schematic diagram of programming commands of a prior art NVM chip. The control unit (eg, the control unit 104 of FIG. 1 ) issues a programming command including commands, addresses and data to the NVM chip through pins, and writes data into the NVM chip. In Figure 3, a programming command that includes multiple clock cycles is shown. The cycle time on the left in Figure 3 is first, and the cycle time on the right is last. A set of signals is transmitted to the NVM chip through the DQ pin in each cycle. The "cycle type" row in Figure 3 shows the type (or meaning) of the signal transmitted per cycle, and the "DQ" row shows the signal transmitted per cycle. value of .

Taking the programming command as an example, the programming command includes three parts: address, data and status. In the address portion of the program command, indicated by "80h" on the DQ pin, followed by multiple (eg, 5) cycles of addresses (indicated by C1, C2, R1, R2, and R3) that indicate that the program command will The address of the NVM chip to write to. Next, the data to be written (represented by D0, D1, ... Dn) is transferred to the NVM chip, and the end of the data transfer is indicated by the signal "10h". After the NVM chip receives the "10h" command, it starts to execute the programming operation. The control unit 104 next queries the status of the NVM chip by issuing a "70h" command to the NVM chip, which gives the status to the control unit. The status indicates whether the execution of the programming command is complete.

FIG. 3B shows a schematic diagram of the control unit executing programming commands. The control unit is coupled to one or more NVM chips through flash memory channels. The NVM chip includes a page cache for buffering data to be programmed provided to the NVM chip or data to be read out from the NVM chip. The control unit also includes memory (for example, SRAM). The memory stores data to be written to the NVM chip (in FIG. 3B, indicated by the data in the dashed box in the SRAM). To perform the programming operation, the control unit sends the address portion of the programming command to the NVM chip according to the physical address to be written to the NVM chip. Next, the control unit transfers the data in the memory to the NVM chip as the data part of the programming command. In response to the completion of the data transfer, the data is stored in the page cache of the NVM chip. The control part also issues a command to the NVM chip to inquire whether the programming operation of the NVM chip is completed. If the status provided by the NVM chip indicates that the programming operation has not been completed, the control unit will later query the status of the NVM chip until the completion of the programming operation is confirmed, and the data in the memory is released. If the status indicates that the programming operation has failed, the control unit re-issues the programming command to the NVM chip using the data in the memory. Generally, after the NVM chip receives a command (“10h”) indicating that the data transmission is completed and the programming operation is started, it takes a period of time (denoted as “t”) until the programming operation is processed.

Optionally, the control unit is coupled to multiple NVM chips, and each LUN of the NVM chips can process programming commands in parallel. The control unit can thus issue programming commands to each of the plurality of LUNs simultaneously.

SUMMARY OF THE INVENTION

To improve the performance of the solid state storage device, the control unit processes multiple programming commands simultaneously. The data to be written to the NVM chip for each programming command is stored in memory (eg, the SRAM of Figure 3B). However, it takes a long time (for example, 1 ms) from the start of the programming command to the status of the query to the completion of the programming operation. During this time, the data to be written into the NVM chip is stored in the memory. The capacity of the memory needs to be large enough to accommodate multiple simultaneous programming commands, and the utilization rate of the memory is not high, and the corresponding storage space is released after the programming operation is processed.

According to a first aspect of the present application, there is provided a first method for processing a programming command according to the first aspect of the present application, comprising: sending an address to an NVM chip, and moving data in the memory to the NVM chip; instructing the NVM chip to instruct the data to be Before successfully recording the address, release the data in the memory; and query the state of the NVM chip to obtain the processing result of the programming command.

According to the first method for processing a programming command according to the first aspect of the present application, there is provided a second method for processing a programming command according to the first aspect of the present application, further comprising: in response to moving the data in the memory to the NVM chip, at the second backing up the data in the memory; and generating a second address in response to the status of the NVM chip indicating a program command processing failure, sending the second address to the NVM chip, and sending the backed up data to the NVM chip.

According to the first method for processing a programming command according to the first aspect of the present application, there is provided a third method for processing a programming command according to the first aspect of the present application, further comprising: in response to the state of the NVM chip indicating that the processing of the programming command fails, part programming Commands are sent to the NVM chip to instruct the NVM chip to program the data in the page cache.

According to the third method of processing a programming command according to the first aspect of the present application, there is provided a fourth method of processing a programming command according to the first aspect of the present application, wherein part of the programming command includes the second address and does not include the data to be programmed.

According to the third method of processing a programming command according to the first aspect of the present application, there is provided the fifth method of processing a programming command according to the first aspect of the present application, wherein the partial programming command instructs the NVM chip to generate the second address according to the address.

According to one of the third to fifth methods for processing a programming command according to the first aspect of the present application, there is provided a sixth method for processing a programming command according to the first aspect of the present application, wherein part of the programming command further indicates that data to be programmed is stored in a page cache address in .

According to the first method for processing a programming command according to the first aspect of the present application, there is provided a seventh method for processing a programming command according to the first aspect of the present application, further comprising: responding to the status of the NVM chip indicating that the processing of the programming command fails, from the NVM chip The page cache reads the data; sends the second address to the NVM chip, and sends the read data to the NVM chip; and query the state of the NVM chip again to obtain the data that records the data at the second address. The processing result of the programming operation.

According to the second method for processing a programming command according to the first aspect of the present application, there is provided an eighth method for processing a programming command according to the first aspect of the present application, further comprising: in response to the status of the NVM chip indicating that the processing of the programming command fails, also backup the The data is moved to the memory, and the backup data is moved from the memory to the NVM chip.

According to the second method of processing a programming command according to the first aspect of the present application, there is provided a ninth method of processing a programming command according to the first aspect of the present application, wherein the backed up data is moved from the second memory to the NVM chip.

According to the third, eighth or ninth method for processing a programming command according to the first aspect of the present application, there is provided a tenth method for processing a programming command according to the first aspect of the present application, further comprising: querying the state of the NVM chip again to obtain A processing result of a programming operation to record the data at the second address.

According to the first, seventh or tenth method for processing a programming command according to the first aspect of the present application, there is provided an eleventh method for processing a programming command according to the first aspect of the present application, further comprising: instructing programming in response to the state of the NVM chip If the command processing fails, redundant data is read from the page strip to which the address programmed by the failed programming command belongs, and the data is restored; the second address is sent to the NVM chip, and the restored data is sent to the NVM chip.

According to the eleventh method for processing a programming command according to the first aspect of the present application, there is provided the twelfth method for processing a programming command according to the first aspect of the present application, further comprising: querying the state of the NVM chip again to obtain the data The processing result of the programming operation at the second address is recorded.

According to a second aspect of the present application, there is provided a first method for processing a programming command according to the second aspect of the present application, comprising: sending an address to an NVM chip, and moving data in the memory to the NVM chip; indicating that the data has been successfully executed on the NVM chip Before recording the address, the memory space storing the data can be written with other data; and the state of the NVM chip is queried to obtain the processing result of the programming command.

According to a third aspect of the present application, there is provided a solid-state storage device according to the third aspect of the present application, comprising a control unit and an NVM chip, the control unit performing any one of the methods according to the first and second aspects of the present application.

According to a fourth aspect of the present application, there is provided a control component according to the fourth aspect of the present application for performing any one of the methods of the first and second aspects of the present application.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings.

1 is a block diagram of a solid-state storage device in the related art;

2 is a schematic diagram of a large block in the related art;

3A is a schematic diagram of a programming command of a prior art NVM chip;

Figure 3B shows a schematic diagram of the control component executing programming commands;

4A shows a schematic diagram of processing programming commands according to an embodiment of the present application;

FIG. 4B shows a flowchart of processing programming commands in the embodiment of FIG. 4A;

5A is a schematic diagram of a programming command according to yet another embodiment of the present application;

5B is a flowchart of processing programming commands according to yet another embodiment of the present application;

6A is a schematic diagram of a control component executing a programming command according to another embodiment of the present application;

FIG. 6B shows a flowchart of processing programming commands in the embodiment of FIG. 6A; and

FIG. 7 shows a flowchart of processing programming commands according to yet another embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of this application.

FIG. 4A shows a schematic diagram of processing programming commands according to an embodiment of the present application.

The control unit is coupled to the plurality of NVM chips. The control unit also includes memory (eg, SRAM). The memory stores data to be programmed into the NVM chip. The control unit issues programming commands to the NVM chip and transmits the data in the memory to the NVM chip. The NVM chip receives the data and stores it in the page cache. In response to recognizing that the data transfer is complete and being instructed to begin a programming operation (eg, receiving a "10h" command), the NVM chip writes the data in the page cache to the physical address provided by the control unit.

According to the embodiment of FIG. 4A of the present application, in the programming command, the control unit releases the storage space occupied by the transferred data in the memory as the data to be programmed is transferred to the NVM chip, so that the storage space can be allocated Used to store data for other programming commands, or other data. Therefore, the utilization rate of the memory is improved, and the time that the data of each programming command occupies the memory is greatly shortened.

If the control unit finds that the NVM chip performs the programming operation successfully, it can issue other operation commands to the NVM chip. If the control unit finds that the NVM chip fails to perform the programming operation, it re-allocates the storage space in the memory. A command or read command to read the page cache is issued to the NVM chip, and the data in the page cache of the NVM chip is read out and stored in the allocated storage space. and issue the program command again, instruct the NVM chip to the new physical address to which the program command is to be written, move the data in the newly allocated memory space to the page cache of the NVM chip, and instruct the NVM chip to start the program operation (for example, by " 10h" command). The control unit also queries the execution status of the programming operation of the NVM chip until it is confirmed that the programming operation is successfully executed.

FIG. 4B shows a flowchart for processing a programming command in the embodiment of FIG. 4A.

To execute programming commands, the control unit issues programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed, and sends the physical address to the NVM chip in a programming command. The control unit also moves the data to be programmed in the memory (eg, the SRAM of Figure 4A) to the NVM chip (410) as part of the programming command. In response to the data to be programmed being moved to the NVM chip, the control unit releases the memory space occupied by the data (420) so that the memory space can be allocated to other program command data. The control part queries the execution result of the program operation corresponding to the program command indicated by the NVM chip (430).

If the programming operation is performed successfully, the processing of the current programming command is completed, and the control unit may continue to process other programming commands (returning to step 410). If it is found that the processing of the current programming command fails, the control unit re-allocates the storage space in the memory (450), and issues a read command or a command to read the page cache to the NVM chip, so as to read the data to be programmed from the page cache of the NVM chip , and store the read data in the newly allocated storage space in the memory (460). And returning to step 410, the control component regenerates the programming command, and sends the data of the newly allocated storage space in the memory to the NVM chip through the new programming command. The control unit also provides the NVM chip with a new physical address in a new programming command to instruct the NVM chip to write the data to be programmed into the new physical address. Still optionally, if the programming operation corresponding to the new programming command still fails, steps 450 and 460 are continued to be repeated, and a new programming command is started through step 410 .

Optionally, the memory is external to the control unit and coupled to the control unit. For example, the memory is DRAM and has a larger capacity than SRAM in FIG. 4A.

FIG. 5A is a schematic diagram of a programming command according to yet another embodiment of the present application.

The program command according to the embodiment of FIG. 5A (referred to as a partial program command for the sake of clarity) is compared to the program command of FIG. 3B with the data portion removed. A partial program command includes an address portion, indicated by signal "80h" followed by addresses (by C1, C2, R1, R2, and R3). The address part indicates the physical address of the NVM chip to which the data to be programmed is to be written. In response to receiving the address portion of the program command, the NVM chip records the physical address.

Next, the control section transmits the command "10h" of the programming command to the NVM chip without transmitting the data to be programmed. The command "10h" indicates that the NVM chip can begin to perform a programming operation, and that the data to be programmed is the data in the page cache of the NVM chip. It will be understood that the command "10h" is for example only, and commands with other values may be used to indicate to the NVM chip that execution of the programming command can begin and that the data to be programmed is located in the page cache. In response to receiving the command "10h", the NVM chip starts a programming operation, writing the data in the page cache to the physical address of the previously recorded programming command. The NVM chip also maintains the execution status of the programming operation to indicate that the programming operation is being executed, that the programming operation has been executed successfully, or that the programming operation has failed to execute.

The control unit issues a command (indicated by "70h") to the NVM chip to query the state of the NVM chip after a period of time after issuing the "10h" command to the NVM chip, and learns the execution state of the programming operation from the obtained state.

Optionally, before the "10h" command of the partial programming command, an instruction to use the data in the page cache as the data to be programmed is further included. For example, consecutive commands "11h" and "10h" are used to instruct to use the data of the page cache as the data to be programmed. For another example, a separate command "12h" different from the program command is used to instruct to use the data of the page cache as the data to be programmed.

In an optional implementation manner, the NVM chip also provides a page cache release command. The control unit issues a page cache release command to the NVM chip to indicate to the NVM chip that data in its page cache may be discarded (eg, enter a low-power sleep mode). And until the page cache data is received by the NVM chip, the storage of the data in the page cache will be maintained.

In a still optional embodiment, the address portion of the programming command is simplified. In the plume of FIG. 5A, the address portion includes a physical address of 5 cycles (eg, 40 bits). In an alternative embodiment, the programming command instructs the NVM chip to generate a new physical address based on the physical address of the previous command. For example, the page address of the new physical address is incremented (eg, incremented by 1) from the page address of the previous command. Thereby, the clock cycle required for transmitting the programming command is reduced, and the processing delay of the programming command is reduced.

In yet another alternative embodiment, the page cache of the NVM chip has a larger size, eg, can accommodate multiple physical pages. In the partial programming command, the storage address of the data to be programmed in the page cache is indicated, so that the NVM chip records part of the data in the page cache in the physical address through the programming operation. In the program command, optionally, the address of the page cache for storing the data to be programmed is also indicated to the NVM chip.

5B is a flowchart of processing programming commands according to yet another embodiment of the present application.

To execute programming commands, the control unit issues programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed, and sends the physical address to the NVM chip in a programming command. The control unit also moves the data to be programmed in the memory to the NVM chip as part of the programming command (510). In response to the data to be programmed being moved to the NVM chip, the control unit releases the memory space occupied by the data (520) so that the memory space can be allocated to other program command data. The control unit queries the execution result of the program operation corresponding to the program command indicated by the NVM chip (530).

If the programming operation is performed successfully, the processing of the current programming command is completed, and the control unit may continue to process other programming commands (returning to step 510). If it is found that the processing of the current programming command fails, the control unit sends the partial programming command shown in FIG. 5A to the NVM chip (550). The partial programming command instructs the NVM chip to perform a programming operation on the data in the page cache, and records the data in the page cache to the new physical address of the NVM chip indicated by the partial programming command. Optionally, the control unit generates a new physical address for the partial programming command and sends it to the NVM chip. Still optionally, the partial programming command instructs the NVM chip to generate a new physical address based on the physical address of the previous programming command, eg, the page address of the new physical address is incremented (eg, incremented by 1) from the page address of the previous command.

In response to receiving the partial program command, the NVM chip initiates a program operation on the data in the page cache to write the new physical address indicated by the partial program command. In response to issuing the partial programming command, the control unit queries the NVM chip for the execution result of the programming command. If the partial programming command fails to be executed again, the control unit may issue the partial programming command to the NVM chip again until the NVM chip indicates that the partial programming command is successfully executed.

FIG. 6A is a schematic diagram of a control component executing a programming command according to another embodiment of the present application.

The control unit is coupled to the plurality of NVM chips. The control unit includes memory (eg, SRAM). The control unit is also coupled to the external DRAM. External DRAM can have larger capacity or higher storage density than SRAM memory.

The memory stores data to be programmed into the NVM chip. The control unit issues programming commands to the NVM chip and transmits the data in the memory to the NVM chip. In response to recognizing that the data transfer is complete and being instructed to begin a programming operation (eg, receiving a "10h" command), the NVM chip writes the data in the page cache to the physical address provided by the control unit.

According to the embodiment of FIG. 6A of the present application, along with transmitting the data to be programmed to the NVM chip, the control unit also transmits the data to be transmitted to the DRAM, and releases the storage space occupied by the transmitted data in the memory, The memory space can thus be allocated to store data for other programming commands, or other data. The data in DRAM is used as backup data to be used when the NVM chip fails to execute. Therefore, the utilization rate of the memory is improved, and the time that the data of each programming command occupies the memory is greatly shortened.

If the control unit finds that the NVM chip performs the programming operation successfully, it can issue other operation commands to the NVM chip. If the control unit finds that the NVM chip fails to perform the programming operation, it re-allocates the storage space in the memory. And move the data to be programmed from the DRAM to the allocated storage space of the memory. and issue the programming command again, instructing the NVM chip to the new physical address to which the programming command is to be written, moving the data in the newly allocated storage space to the NVM chip, and instructing the NVM chip to start executing the programming operation (for example, via the "10h" command ). The control unit also queries the execution status of the programming operation of the NVM chip until it is confirmed that the programming operation is successfully executed.

Optionally, if the control unit finds that the NVM chip fails to perform the programming operation, there is no need to re-allocate storage space in the memory, but the to-be-programmed data stored in the DRAM is moved to the NVM chip during the process of issuing a programming command to the NVM chip again. Thus, the process of transferring data from DRAM to SRAM memory is omitted.

FIG. 6B shows a flowchart for processing a programming command in the embodiment of FIG. 6A.

To execute programming commands, the control unit issues programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed, and sends the physical address to the NVM chip in a programming command. The control unit also moves the data to be programmed in the memory (eg, the SRAM of FIG. 6A ) to the NVM chip as part of the programming command, and the data to be programmed by the control unit to the memory (eg, FIG. 6A ) external to the control unit. 6A DRAM) (610) as backup data. In response to the data to be programmed being moved to the NVM chip, the control unit releases the memory space occupied by the data (620) so that the memory space can be allocated to other program command data. The control unit queries the execution result of the program operation corresponding to the program command indicated by the NVM chip (630).

If the programming operation is performed successfully, the processing of the current programming command is completed, and the control unit may continue to process other programming commands (returning to step 610). If it is found that the processing of the current programming command fails, the control component sends the programming command to the NVM chip again, and transmits the backup data in the external memory to the NVM chip as the data to be programmed (650). Optionally, the backup data in the external memory is transferred directly to the NVM chip. As another implementation manner, the backup data in the external memory is first moved to the memory (SRAM) by the control component, and then moved from the memory (SRAM) to the NVM chip. And return to step 630 to query the execution result of the programming operation. If the programming operation still fails, steps 650 and 630 continue to be repeated.

FIG. 7 shows a flowchart of processing programming commands according to yet another embodiment of the present application. In order to further reduce the occupation of memory in processing programming commands.

To execute programming commands, the control unit issues programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed, and sends the physical address to the NVM chip in a programming command. The control unit also moves the data to be programmed in the memory (eg, the SRAM of Figure 6A) to the NVM chip (710) as part of the programming command. In response to the data to be programmed being moved to the NVM chip, the control unit releases the memory space occupied by the data (720) so that the memory space can be allocated to other program command data. In the embodiment according to FIG. 7 , after the data to be programmed into the NVM chip is transmitted to the NVM chip, the control unit releases the storage space occupied by the data, and does not include backup data.

The control unit queries the execution result of the program operation corresponding to the program command indicated by the NVM chip (730).

If the programming operation is performed successfully, the processing of the current programming command is completed, and the control unit may continue to process other programming commands (returning to step 710). If it is found that the processing of the current programming command fails, the control unit reads data from the page strip (see also FIG. 2 ) to which the physical address of the programming command belongs, so as to restore the data to be written by the current programming command. The control unit also moves the page stripe restored data to the NVM chip in the newly generated programming command (750). And return to step 730 to query the execution result of the programming operation. If the programming operation still fails, step 750 and step 730 are continued to be repeated.

Embodiments according to the present application also provide a program stored on a readable medium, which, when executed by a controller of a solid-state storage device, causes the solid-state storage device to execute any one of the processing methods provided by the embodiments of the present application.

Although the preferred embodiments of the present application have been described, additional changes and modifications to these embodiments may occur to those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the preferred embodiment and all changes and modifications that fall within the scope of this application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (4)

1. A method of processing a programming command, comprising:

sending the address to the NVM chip, and moving the data in the memory to the NVM chip;

releasing the data in the memory before the NVM chip indicates that the data is successfully recorded in the address; and

inquiring the state of the NVM chip to obtain a processing result of the programming command; wherein,

reading redundant data from a page strip to which a programmed address of a program command which fails to process belongs in response to the state of the NVM chip indicating that the program command fails to process, and recovering the data; generating a second address, sending the second address to the NVM chip, and sending the recovered data to the NVM chip.

2. The method of claim 1, further comprising:

and querying the state of the NVM chip again to obtain a processing result of the programming operation of recording the data at the second address.

3. A method of processing a programming command, comprising:

sending the address to the NVM chip, and moving the data in the memory to the NVM chip;

before the NVM chip indicates that the data is successfully recorded at the address, the memory space storing the data can be written with other data; and

querying the state of the NVM chip to obtain the processing result of the program command, wherein,

reading redundant data from a page strip to which a programmed address of a program command which fails to process belongs in response to the state of the NVM chip indicating that the program command fails to process, and recovering the data; and sending the second address to the NVM chip, and sending the recovered data to the NVM chip.

4. A control means for performing the method according to any one of claims 1-3.

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