CN109802006A - A kind of crystalline epitaxial structure and growing method - Google Patents

Description

A kind of crystal epitaxial structure and growth method

technical field

The invention relates to the technical field of semiconductor devices, in particular to a crystal epitaxial structure and a growth method.

Background technique

Epitaxial growth refers to a method of extending and growing a single crystal thin film on a crystal surface with a certain crystallographic orientation and according to a certain crystallographic direction. Epitaxial growth can be used to grow homo- and hetero-epitaxial thin films with steep or graded composition or impurity distribution. The development of epitaxy technology is of great significance for improving the quality of semiconductor materials and device performance, as well as for the development of new materials and new devices.

In recent years, with the development of compound semiconductor device performance, the need to grow high-quality epitaxial layer structures with lattice mismatch on substrates has become more and more urgent. The traditional epitaxial growth method is to directly grow the lattice mismatched structure on the front side of the substrate. Due to the mismatch of lattice constants, the epitaxial material layer will inevitably be strained, and the strain needs to be eliminated by dislocations, but the occurrence of dislocations will be significantly reduced. Material quality and device performance.

Therefore, how to eliminate the strain during the growth of mismatched epitaxial materials is particularly important to reduce the dislocation density and improve the crystal quality of the lattice mismatched structure.

SUMMARY OF THE INVENTION

Therefore, the technical problem to be solved by the present invention is how to eliminate the strain during the growth of the mismatched epitaxial material, so as to provide a crystal epitaxial structure and a growth method.

The above-mentioned technical purpose of the present invention is achieved through the following technical solutions:

A crystal epitaxial growth method, comprising the following steps:

S1, forming a lattice matching layer on the first surface of the substrate;

S2, forming a first lattice mismatch layer on the second surface of the substrate, where the first lattice mismatch layer includes a lattice gradient layer and a lattice stabilization layer;

S21, forming the lattice gradient layer on the second surface of the substrate;

S22, forming the lattice stabilization layer on the lattice gradient layer;

S3, forming a second lattice mismatch layer on the lattice matching layer, where the second lattice mismatch layer includes a lattice transition layer and a lattice mismatch function layer;

S31, forming the lattice transition layer on the lattice matching layer;

S32, forming the lattice mismatch functional layer on the lattice transition layer;

Wherein, the lattice constants of the first lattice mismatch layer, the substrate and the second lattice mismatch layer monotonically increase or decrease monotonically.

Further, the lattice matching layer includes a first sub-cell layer, a first tunnel junction, a second sub-cell layer and a second tunnel junction; the step of forming the lattice matching layer on the first surface of the substrate ,include:

S11, forming the first sub-cell layer on the first surface of the substrate;

S12, forming the first tunnel junction on the first sub-cell layer;

S13, forming the second sub-cell layer on the first tunnel junction;

S14, forming the second tunnel junction on the second sub-cell layer.

Further, before the step of forming the lattice matching layer on the first surface of the substrate, the method further includes:

S01, forming a buffer layer and an etching peeling layer on the substrate in sequence.

Further, before the step of forming the lattice matching layer on the first surface of the substrate, the method further includes:

S02, polishing the first surface and the second surface of the substrate.

Further, the thickness of the substrate is 300 μm.

The present invention also provides a crystal epitaxial structure, comprising:

a substrate having opposing first and second surfaces;

A lattice matching layer and a second lattice mismatching layer are arranged on the first surface in sequence, the second lattice mismatching layer includes a lattice transition layer and a lattice mismatching functional layer, the lattice transition layer a layer is arranged on the lattice matching layer, and the lattice mismatch functional layer is arranged on the lattice transition layer;

A first lattice mismatch layer is provided on the second surface, the first lattice mismatch layer includes a lattice gradient layer and a lattice stabilization layer, and the lattice gradient layer is provided on the substrate. On the second surface, the lattice stabilization layer is disposed on the lattice graded layer;

Wherein, the lattice constants of the first lattice mismatch layer, the substrate and the second lattice mismatch layer monotonically increase or decrease monotonically.

Further, the lattice matching layer includes a first sub-cell layer, a first tunnel junction, a second sub-cell layer, and a second tunnel junction sequentially disposed on the first surface of the substrate.

Further, the thickness of the substrate is 300 μm.

The technical scheme of the present invention has the following advantages:

In the crystal epitaxial growth method provided by the present invention, before the second lattice mismatch layer is formed on the first surface of the substrate, the first lattice mismatch layer is formed on the second surface of the substrate in advance, and the first lattice mismatch is ensured. The lattice constants of the coordination layer, the substrate and the second lattice mismatched layer are monotonically increasing or decreasing. Therefore, the formation of the first lattice mismatch layer effectively changes the strain state of the substrate and the lattice matching layer, thereby effectively weakening the strain generated when the second lattice mismatch layer is formed, and suppressing the generation of dislocations , improve the quality of the crystal epitaxial structure, and then improve the performance of semiconductor devices.

In the crystal epitaxial growth method provided by the present invention, the step of forming the first lattice mismatch layer includes firstly forming a lattice gradient layer on the second surface of the substrate, and then forming a lattice stabilization layer on the lattice gradient layer. This ensures that the lattice constant of the first lattice mismatched layer gradually changes from the lattice gradient layer to the lattice constant of the lattice stable layer, avoiding the direct jump of the lattice constant of the first lattice mismatched layer to the lattice stable layer The lattice constant of .

In the crystal epitaxial growth method provided by the present invention, the step of forming the second lattice mismatch layer includes first forming a lattice transition layer on the lattice matching layer, and then forming a lattice mismatch functional layer on the lattice transition layer. This ensures that the lattice constant of the second lattice mismatch layer gradually transitions from the lattice transition layer to the lattice constant of the lattice mismatch functional layer, avoiding the direct jump of the lattice constant of the second lattice mismatch layer to the lattice constant of the lattice mismatch functional layer. The lattice constant of the lattice-mismatched functional layer.

The crystal epitaxial growth method provided by the present invention further comprises the steps of sequentially forming a buffer layer and an etching peeling layer on the substrate before forming the lattice matching layer. The formation of the etching peeling layer is conducive to removing the etching peeling layer and the structural layer on the side away from the second lattice mismatching layer through an etching process after the preparation of the second lattice mismatching layer is completed.

In the crystal epitaxial growth method provided by the present invention, the first surface and the second surface of the substrate are polished, which helps to form a structural layer on both the first surface and the second surface, and reduces the thickness of the substrate .

In the crystal epitaxial structure provided by the present invention, by disposing the first lattice mismatch layer on the second surface of the substrate, the strain states of the substrate and the lattice matching layer are effectively changed, thereby effectively weakening the second lattice mismatch layer. The strain generated during the formation suppresses the generation of dislocations, improves the quality of the crystal epitaxial structure, and further improves the performance of the semiconductor device.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

1 is a schematic structural diagram of a substrate provided by the present invention;

2 is a process flow diagram of forming a lattice matching layer on a substrate in the crystal epitaxial growth method provided by the present invention;

3 is a process flow diagram of forming a first lattice mismatch layer on the second surface of the substrate in the crystal epitaxial growth method provided by the present invention;

4 is a process flow diagram of forming a second lattice mismatch layer on the lattice matching layer in the crystal epitaxial growth method provided by the present invention;

FIG. 5 is a flow chart of the crystal epitaxial growth method provided by the present invention.

Description of reference numbers:

1, substrate; 11, first surface; 12, second surface; 2, lattice matching layer; 21, first sub-cell layer; 22, first tunnel junction; 23, second sub-cell layer; 24, The second tunneling junction; 3. the first lattice mismatch layer; 31, the lattice gradient layer; 32, the lattice stabilization layer; 4, the second lattice mismatch layer; 41, the lattice transition layer; 42, the crystal Lattice mismatch functional layer; 5. Buffer layer; 6. Corrosion peeling layer.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

Example 1

The embodiment of the present invention provides a crystal epitaxial growth method for preparing a GaInP/GaAs/InGaAs flip-chip triple-junction solar cell. As shown in Figure 1-5, it includes the following steps:

Step S1 , forming a lattice matching layer 2 on the first surface 11 of the substrate 1 . The lattice constant of the lattice matching layer 2 is the same as that of the substrate 1 .

In this embodiment, the substrate 1 is selected from but not limited to GaAs, InP, InAs and other substrate materials.

As a preferred embodiment, the lattice matching layer 2 includes a first sub-cell layer 21 , a first tunnel junction 22 , a second sub-cell layer 23 and a second tunnel junction 24 . Step S11 includes the following steps:

Step S11 , forming a first sub-cell layer 21 on the first surface 11 of the substrate 1 . The first sub-cell layer 21 is a GaInP sub-cell layer.

Step S12 , forming a first tunnel junction 22 on the first sub-cell layer 21 . The first tunnel junction 22 is a GaInP layer and an AlGaAs layer.

Step S13 , forming a second sub-cell layer 23 on the first tunnel junction 22 . The second sub-cell layer 23 is a GaAs sub-cell layer.

Step S14 , forming a second tunnel junction 24 on the second sub-cell layer 23 . The second tunnel junction 24 is a GaInP layer and an AlGaAs layer.

Step S2 , forming a first lattice mismatch layer 3 on the second surface 12 of the substrate 1 . The second surface 12 and the first surface 11 of the substrate 1 are two surfaces on the substrate 1 that face away from each other.

As a preferred embodiment, the first lattice mismatch layer 3 includes a lattice gradient layer 31 and a lattice stabilization layer 32 . Step S2 includes the following steps:

Step S21 , forming a lattice gradient layer 31 on the second surface 12 of the substrate 1 .

Wherein, the lattice graded layer 31 is an InGaP lattice graded layer 31 with a graded In composition, and the In composition may show an increasing trend or a decreasing trend.

As a preferred embodiment, the In composition can be reduced from 52% to 16%.

Step S22 , forming a lattice stabilization layer 32 on the lattice gradient layer 31 . The lattice stabilization layer 32 is an InGaP lattice stabilization layer 32 .

Therefore, it is ensured that the lattice constant of the first lattice mismatch layer 3 is gradually changed from the lattice gradient layer 31 to the lattice constant of the lattice stabilization layer 32, and the lattice constant of the first lattice mismatch layer 3 is prevented from jumping directly. to the lattice constant of the lattice stabilization layer 32 .

Step S3 , forming a second lattice mismatch layer 4 on the lattice matching layer 2 . The second lattice mismatch layer 4 includes a lattice transition layer 41 and a lattice mismatch function layer 42 . Step S13 includes the following steps:

Step S31 , forming a lattice transition layer 41 on the lattice matching layer 2 .

The lattice transition layer 41 is an InGaP lattice transition layer 41 with a graded In composition, and the In composition may show a decreasing trend or an increasing trend. However, it needs to be ensured that the gradation trend of the In composition of the InGaP lattice transition layer 41 is opposite to that of the InGaP lattice gradation layer 31 .

As a preferred embodiment, when the In composition of the InGaP lattice transition layer 31 is reduced from 52% to 16%, the In composition of the InGaP lattice transition layer 41 is increased from 52% to 81%.

Step S32 , forming a lattice mismatch functional layer 42 on the lattice transition layer 41 . The lattice mismatch functional layer 42 is an InGaAs sub-cell layer.

Therefore, it is ensured that the lattice constant of the second lattice mismatch layer 4 is gradually transitioned from the lattice transition layer 41 to the lattice constant of the lattice mismatch functional layer 42 , and the lattice constant of the second lattice mismatch layer 4 is avoided. Jump directly to the lattice constant of the lattice mismatch functional layer 42 .

In this embodiment, the lattice constants of the first lattice mismatch layer 3 , the substrate 1 and the second lattice mismatch layer 4 exhibit a monotonically increasing or monotonically decreasing trend.

In the crystal epitaxial growth method provided by the embodiment of the present invention, before the second lattice mismatch layer 4 is formed on the first surface 11 of the substrate 1, the first lattice mismatch layer 3 is formed on the second surface 12 of the substrate 1 in advance , and ensure that the lattice constants of the first lattice mismatch layer 3 , the substrate 1 and the second lattice mismatch layer 4 monotonically increase or decrease monotonically. Therefore, the formation of the first lattice mismatch layer 3 effectively changes the strain state of the substrate 1 and the lattice matching layer 2, thereby effectively reducing the strain generated when the second lattice mismatch layer 4 is formed, and suppressing the The generation of dislocations improves the quality of the crystal epitaxial structure, thereby improving the performance of semiconductor devices.

It should be noted that the thickness of the first lattice mismatch layer 3 can be adjusted according to the actual situation, and the strain state of the substrate 1 and the lattice matching layer 2 can also be changed by adjusting the thickness, so as to further realize the The strain generated when the lattice mismatch layer 4 is formed is weakened.

As a preferred embodiment, before step S1, it also includes:

Step S01 , forming a buffer layer 5 and an etching peeling layer 6 on the substrate 1 in sequence.

Among them, the buffer layer 5 is a GaAs layer, and the etching peeling layer 6 is an AlGaAs layer. The formation of the etching peeling layer 6 is conducive to removing the etching peeling layer 6 and the structural layer on the side away from the second lattice mismatching layer 4 by an etching process after the preparation of the second lattice mismatching layer 4 is completed.

As a preferred embodiment, before step S1, it also includes:

Step S02 , polishing the first surface 11 and the second surface 12 of the substrate 1 . This helps to form structural layers on both the first surface 11 and the second surface 12 , and reduces the thickness of the substrate 1 .

As a preferred embodiment, the thickness of the substrate 1 is 300 μm. As an alternative embodiment, the thickness of the substrate 1 can also be other values, all of which can achieve the purpose of the present invention and belong to the protection scope of the present invention.

It should be noted that the preparation of each layer in this embodiment may be completed by a metal organic chemical vapor phase epitaxy (MOVPE) device or a molecular beam epitaxy (MBE) device.

Example 2

Embodiments of the present invention provide a crystal epitaxial structure, specifically a GaInP/GaAs/InGaAs flip-chip triple-junction solar cell structure. As shown in FIGS. 1-4 , it includes a substrate 1 , a lattice matching layer 2 , a first lattice mismatching layer 3 and a second lattice mismatching layer 4 . in,

The substrate 1 has a first surface 11 and a second surface 12 opposite to each other, that is, the first surface 11 and the second surface 12 are two surfaces on the substrate 1 that face away from each other. Also, the first surface 11 and the second surface 12 are polished surfaces.

As a preferred embodiment, the thickness of the substrate 1 is 300 μm.

In this embodiment, the substrate 1 is selected from but not limited to GaAs, InP, InAs and other substrate materials.

The lattice matching layer 2 and the second lattice mismatching layer 4 are sequentially disposed on the first surface 11 . The lattice constant of the lattice matching layer 2 is the same as that of the substrate 1 .

As a preferred embodiment, the lattice matching layer 2 includes a first sub-cell layer 21 , a first tunnel junction 22 , a second sub-cell layer 23 and a second tunnel junction 24 . The first subcell layer 21 is a GaInP subcell layer, the first tunnel junction 22 is a GaInP layer and an AlGaAs layer, the second subcell layer 23 is a GaAs subcell layer, and the second tunnel junction 24 is a GaInP layer and an AlGaAs layer.

As a preferred embodiment, the second lattice mismatch layer 4 includes a lattice transition layer 41 and a lattice mismatch functional layer 42 which are sequentially stacked and disposed on the lattice matching layer 2 . The lattice transition layer 41 is an InGaP lattice transition layer 41 with a graded In composition, and the In composition may show a decreasing trend or an increasing trend. The lattice mismatch functional layer 42 is an InGaAs sub-cell layer.

As a preferred embodiment, the In composition of the InGaP lattice transition layer 41 is increased from 52% to 81%.

Therefore, it is ensured that the lattice constant of the second lattice mismatch layer 4 is gradually transitioned from the lattice transition layer 41 to the lattice constant of the lattice mismatch functional layer 42 , and the lattice constant of the second lattice mismatch layer 4 is avoided. Jump directly to the lattice constant of the lattice mismatch functional layer 42 .

The first lattice mismatch layer 3 is disposed on the second surface 12 . The first lattice mismatch layer 3 includes a lattice gradient layer 31 and a lattice stabilization layer 32 which are sequentially stacked and disposed on the second surface 12 . in,

The lattice graded layer 31 is an InGaP lattice graded layer 31 with a graded In composition, and the In composition may show an increasing trend or a decreasing trend. However, it needs to be ensured that the In composition gradient trend of the InGaP lattice transition layer 31 is opposite to the In composition gradient trend of the InGaP lattice transition layer 41 .

As a preferred embodiment, when the In composition of the InGaP lattice transition layer 41 is increased from 52% to 81%, the In composition of the InGaP lattice graded layer 31 is decreased from 52% to 16%.

The lattice stabilization layer 32 is an InGaP lattice stabilization layer 32 .

Therefore, it is ensured that the lattice constant of the first lattice mismatch layer 3 is gradually changed from the lattice gradient layer 31 to the lattice constant of the lattice stabilization layer 32, and the lattice constant of the first lattice mismatch layer 3 is prevented from jumping directly to The lattice constant of the lattice stabilization layer 32 .

In this embodiment, the lattice constants of the first lattice mismatch layer 3 , the substrate 1 and the second lattice mismatch layer 4 exhibit a monotonically increasing or monotonically decreasing trend.

It should be noted that, in this embodiment, the first lattice mismatch layer 3 is formed before the second lattice mismatch layer 4 is formed.

In the crystal epitaxial structure provided by the present invention, by disposing the first lattice mismatch layer 3 on the second surface 12 of the substrate 1, the strain states of the substrate 1 and the lattice matching layer 2 are effectively changed, thereby effectively weakening the second The strain generated when the lattice mismatch layer 4 is formed suppresses the generation of dislocations, improves the quality of the crystal epitaxial structure, and further improves the performance of the GaInP/GaAs/InGaAs flip-chip triple junction solar cell.

As a preferred embodiment, a buffer layer 5 and an etching peeling layer 6 are further disposed between the first surface 11 of the substrate 1 and the lattice matching layer 2 . Among them, the buffer layer 5 is a GaAs layer, and the etching peeling layer 6 is an AlGaAs layer. The provision of the etching isolation layer is helpful for removing the etching peeling layer 6 and the structural layer on the side away from the second lattice mismatch layer 4 through the etching process subsequently.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (8)

1. A method for epitaxial growth of a crystal, comprising the steps of:

s1, forming a lattice matching layer (2) on the first surface (11) of the substrate (1);

s2, forming a first lattice mismatch layer (3) on the second surface (12) of the substrate (1), wherein the first lattice mismatch layer (3) comprises a lattice gradual change layer (31) and a lattice stable layer (32);

s21, forming the lattice-graded layer (31) on the second surface (12) of the substrate (1);

s22, forming the lattice stabilization layer (32) on the lattice gradual change layer (31);

s3, forming a second lattice-mismatched layer (4) on the lattice-matched layer (2), wherein the second lattice-mismatched layer (4) comprises a lattice transition layer (41) and a lattice-mismatched functional layer (42);

s31, forming the lattice transition layer (41) on the lattice matching layer (2);

s32, forming the lattice-mismatched functional layer (42) on the lattice transition layer (41);

wherein the lattice constants of the first lattice-mismatched layer (3), the substrate (1), and the second lattice-mismatched layer (4) are monotonically increasing or monotonically decreasing.

2. A method of epitaxial growth of a crystal according to claim 1, characterized in that the lattice matching layer (2) comprises a first subcell layer (21), a first tunnel junction (22), a second subcell layer (23) and a second tunnel junction (24); the step of forming a lattice matching layer (2) on a first surface (11) of a substrate (1) comprises:

s11, forming the first sub-battery layer (21) on the first surface (11) of the substrate (1);

s12, forming the first tunnel junction (22) on the first sub-battery layer (21);

s13, forming the second sub-battery layer (23) on the first tunnel junction (22);

s14, forming the second tunnel junction (24) on the second sub-battery layer (23).

3. A method of epitaxial growth of a crystal according to claim 1 or 2, characterized in that it further comprises, before the step of forming a lattice matching layer (2) on the first surface (11) of the substrate (1):

s01, forming a buffer layer (5) and an etch release layer (6) on the substrate (1) in sequence.

4. A method of epitaxial growth of a crystal according to claim 1 or 2, characterized in that it further comprises, before the step of forming a lattice matching layer (2) on the first surface (11) of the substrate (1):

s02, polishing the first surface (11) and the second surface (12) of the substrate (1).

5. A method for epitaxial growth of a crystal according to any of claims 1-4, characterized in that the thickness of the substrate (1) is 300 μm.

6. An epitaxial structure, comprising:

a substrate (1) having opposing first (11) and second (12) surfaces;

the lattice matching layer (2) and the second lattice mismatched layer (4) are sequentially arranged on the first surface (11), the second lattice mismatched layer (4) comprises a lattice transition layer (41) and a lattice mismatched functional layer (42), the lattice transition layer (41) is arranged on the lattice matching layer (2), and the lattice mismatched functional layer (42) is arranged on the lattice transition layer (41);

a first lattice-mismatched layer (3) provided on the second surface (12), the first lattice-mismatched layer (3) including a lattice-graded layer (31) and a lattice-stabilized layer (32), the lattice-graded layer (31) being provided on the second surface of the substrate (1), the lattice-stabilized layer (32) being provided on the lattice-graded layer (31);

wherein the lattice constants of the first lattice-mismatched layer (3), the substrate (1), and the second lattice-mismatched layer (4) are monotonically increasing or monotonically decreasing.

7. A crystal epitaxial structure according to claim 6, characterized in that the lattice matching layer (2) comprises a first sub-cell layer (21), a first tunnel junction (22), a second sub-cell layer (23) and a second tunnel junction (24) sequentially arranged on the first surface (11) of the substrate (1).

8. A crystal epitaxial structure according to claim 6, characterized in that the thickness of the substrate (1) is 300 μm.