CN109801963A

CN109801963A - Semiconductor device and forming method thereof

Info

Publication number: CN109801963A
Application number: CN201711143483.0A
Authority: CN
Inventors: 林信志; 周钰杰
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2017-11-17
Filing date: 2017-11-17
Publication date: 2019-05-24
Anticipated expiration: 2037-11-17
Also published as: CN109801963B

Abstract

The present invention provides a kind of semiconductor device and forming method thereof.The semiconductor device includes substrate and the first Group III-V semiconductor layer being set on substrate.First Group III-V semiconductor layer includes fin structure, and above-mentioned fin structure includes top surface, the first side wall and the second sidewall relative to above-mentioned the first side wall.Above-mentioned semiconductor device also includes the second Group III-V semiconductor layer being set in the first Group III-V semiconductor layer.First Group III-V semiconductor layer and the second Group III-V semiconductor layer include different material, and second Group III-V semiconductor layer cover the top surface, the first side wall and second sidewall of above-mentioned fin structure, to form heterogeneous engagement along the top surface, the first side wall and second sidewall of above-mentioned fin structure.Above-mentioned semiconductor device also includes the gate electrode being set in the second Group III-V semiconductor layer.The present invention can increase heterozygous contact area, therefore can increase the area of Two-dimensional electron cloud and improve device efficiency.

Description

Semiconductor device and forming method thereof

Technical field

The embodiment of the present invention relates to a kind of semiconductor device and forming method thereof, and particularly with regard to a kind of high electronics Mobility transistor (High electron mobility transistor, HEMT) or high hole mobility transistor (High Hole mobility transistor, HHMT).

Background technique

Semiconductor device has been widely used in various electronic products, for example, such as high power devices, personal electricity Brain, mobile phone and digital camera ... etc..The manufacture of semiconductor device is usually that pass through deposited in sequential on a semiconductor substrate exhausted Edge layer or dielectric layer material, conductive and semiconductor layer material are then formed by using photoetching process patterning each Kind material layer, uses and forms circuit component and component on this semiconductor substrate.

Wherein, high electron mobility transistor or high hole mobility transistor are because having high output voltage, high collapse electricity The advantages that pressure and be widely used in high power devices.

However, existing high electron mobility transistor or high hole mobility transistor there are still some disadvantages rather than Various aspects are all satisfactory.

Summary of the invention

The embodiment of the present invention provides a kind of semiconductor device.Above-mentioned semiconductor device includes substrate and is set to above-mentioned base The first Group III-V semiconductor layer on plate.Above-mentioned first Group III-V semiconductor layer includes fin structure (fin structure), And above-mentioned fin structure includes top surface, the first side wall and the second sidewall relative to above-mentioned the first side wall.Above-mentioned semiconductor Device also includes the second Group III-V semiconductor layer being set in above-mentioned first Group III-V semiconductor layer.Above-mentioned first III-V Race's semiconductor layer and above-mentioned second Group III-V semiconductor layer include different material, and above-mentioned second Group III-V semiconductor layer is covered The top surface, the first side wall and second sidewall for stating fin structure are covered, along the top surface of above-mentioned fin structure, the first side Wall and second sidewall form heterogeneous engagement (heterojunction).Above-mentioned semiconductor device also includes being set to above-mentioned second Gate electrode in Group III-V semiconductor layer.

The embodiment of the present invention also provides a kind of forming method of semiconductor device.The above method includes providing substrate and shape At the first Group III-V semiconductor layer on aforesaid substrate.Above-mentioned first Group III-V semiconductor layer includes fin structure, and above-mentioned Fin structure includes top surface, the first side wall and the second sidewall relative to above-mentioned the first side wall.The above method also includes shape At the second Group III-V semiconductor layer in above-mentioned first Group III-V semiconductor layer.Above-mentioned first Group III-V semiconductor layer with it is upper Stating the second Group III-V semiconductor layer includes different material, and above-mentioned second Group III-V semiconductor layer covers above-mentioned fin structure Top surface, the first side wall and second sidewall, along the top surface, the first side wall and second sidewall of above-mentioned fin structure Form heterogeneous engagement.The above method also includes forming gate electrode in above-mentioned second Group III-V semiconductor layer.

The present invention can increase heterozygous contact area, therefore can increase the area of Two-dimensional electron cloud and improve device effect Energy.

Detailed description of the invention

The embodiment of the present invention is described in detail below in conjunction with institute's accompanying drawings.It should be noted that various features are not necessarily made to scale and draw It makes and is only to illustrate illustration.In fact, the size of element may be through zooming in or out, clearly to show implementation of the present invention The technical characteristic of example.

Fig. 1, Fig. 2, Fig. 3, Fig. 4 A, Fig. 5 A are a series of partial perspective view, to illustrate first embodiment of the invention The forming method of high electron mobility transistor 10.

Fig. 4 B is the hatching X along Fig. 4 A₁-X₂Show the high electron mobility transistor of first embodiment of the invention 10 process section.

Fig. 5 B is the hatching Y along Fig. 5 A₁-Y₂Show the high electron mobility transistor of first embodiment of the invention 10 fragmentary cross-sectional view.

Fig. 5 C is the partial perspective view for showing high electron mobility transistor 10 ' according to some embodiments of the invention.

Fig. 5 D is the hatching Y along Fig. 5 C₁-Y₂Show some high electron mobility transistor 10 ' for applying example of the present invention Fragmentary cross-sectional view.

Fig. 6 A is the partial perspective view for showing high hole mobility transistor 20 according to a second embodiment of the present invention.

Fig. 6 B is the hatching X along Fig. 6 A₁-X₂Show the high hole mobility transistor of second embodiment of the invention 20 fragmentary cross-sectional view.

Fig. 6 C is the hatching Y along Fig. 6 A₁-Y₂Show the high hole mobility transistor of second embodiment of the invention 20 fragmentary cross-sectional view.

Fig. 6 D is the partial perspective view for showing high hole mobility transistor 20 ' according to some embodiments of the invention.

Fig. 6 E is the hatching Y along Fig. 6 D₁-Y₂Show the high hole mobility transistor of some embodiments of the invention 20 ' fragmentary cross-sectional view.

Drawing reference numeral

10~vague and general type high electron mobility transistor；

10 '~enhancement type high electron mobility transistor；

100~substrate；

200~the first Group III-V semiconductor layers；

202~fin structure；

202T~fin structure top surface；

202S1~fin structure the first side wall；

202S2~fin structure second sidewall；

402~the second Group III-V semiconductor layers；

404~Two-dimensional electron cloud；

502~insulating layer；

504~gate electrode；

506~source/drain electrodes；

508~the first doping Group III-V semiconductor layers；

20~vague and general high hole mobility the transistor of type；

20 '~enhanced high hole mobility transistor；

600~substrate；

602~the first Group III-V semiconductor layers；

604~fin structure；

604T~fin structure top surface；

604S1~fin structure the first side wall；

604S2~fin structure second sidewall；

606~the second Group III-V semiconductor layers；

608~the first doping Group III-V semiconductor layers；

610~insulating layer；

612~gate electrode；

614~source/drain electrodes；

616~two dimension electric hole cloud；

618~the second doping Group III-V semiconductor layers；

W~width；

H~height；

t₁~thickness；

X₁-X₂~hatching；

Y₁-Y₂~hatching.

Specific embodiment

Disclosure below provides many different embodiments or example to implement the different characteristic of this case.It is below to take off Reveal the particular example of each component of description and its arrangement mode, to simplify explanation.Certainly, these specific examples are not used To limit.If being formed in above a second feature for example, the embodiment of the present invention describes a fisrt feature, that is, indicate It may be the embodiment directly contacted with above-mentioned second feature comprising above-mentioned fisrt feature, also may include supplementary features It is formed between above-mentioned fisrt feature and above-mentioned second feature, and contact above-mentioned fisrt feature may directly with second feature Embodiment.In addition, following disclosed different examples may reuse identical reference symbol and/or label.These are heavy It is to be not limited to have between the different embodiments discussed and/or structure specific for simplification and clearly purpose again Relationship.

It should be appreciated that additional operating procedure may be implemented in the method before, between or later, and in the side In the other embodiments of method, the operating procedure of part can be substituted or omit.

In addition, may wherein use with space correlation word, such as " in ... lower section ", " lower section ", " lower ", " on Side ", " higher " and similar word, these space correlation words are (a little) element or spy in illustrating for ease of description Relationship between sign and another (a little) elements or features, these space correlation words include the device in or in operation Orientation described in different direction and schema.When device is diverted different direction (be rotated by 90 ° or other orientation), then Wherein used space correlation adjective will also be explained according to the orientation after steering.

The high electron mobility transistor (HEMT) or high hole mobility transistor (HHMT) of the embodiment of the present invention include Group III-V semiconductor layer with fin structure.Above-mentioned fin structure can increase Two-dimensional electron cloud (two-dimensional Electron gas, 2DEG) or two-dimentional electric hole cloud (two-dimensional hole gas, 2DHG) area, therefore have Preferable device efficiency.

[first embodiment: high electron mobility transistor]

Fig. 1 is the partial perspective view of the initial step of the high electron mobility transistor forming method of the present embodiment.Firstly, As shown in Figure 1, providing substrate 100.In this present embodiment, substrate 100 is sapphire substrate (sapphire), but the present invention is not It is limited according to this.For example, substrate 100 may include elemental semiconductor, such as: silicon or germanium.In some embodiments, substrate 100 It may include compound semiconductor, such as: SiC, GaAs, InAs or InP.In some embodiments, substrate 100 may include alloy half Conductor, such as: SiGe, SiGeC, GaAsP or GaInP.In some embodiments, substrate 100 can be monocrystal substrate, multilager base plate (multi-layer substrate), gradient substrate (gradient substrate), other substrates appropriate or above-mentioned group It closes.In some embodiments, substrate 100 also may include semiconductor on insulator (semiconductor on insulator, SOI) substrate (such as: germanium substrate on SOI silicon substrate or insulating layer), above-mentioned semiconductor on insulator substrate may include bottom Plate, the buried oxide being set on above-mentioned bottom plate and the semiconductor layer being set in above-mentioned buried oxide.

In some embodiments, substrate 100 may include buffer layer (not being illustrated in figure), to avoid or reduce because of substrate Lattice between 100 and semiconductor layer thereon mismatches defect caused by (lattice mismatch).For example, Above-mentioned buffer layer may include AlN, AlGaN, other materials appropriate or combinations of the above.

Then, as shown in Fig. 2, forming the first Group III-V semiconductor layer 200 on substrate 100.In some embodiments In, the first Group III-V semiconductor layer 200 may include undoped III-V group semi-conductor material.For example, in the present embodiment In, the first Group III-V semiconductor layer 200 is formed by undoped GaN, but the present invention is not limited according to this.Some other Embodiment in, the first Group III-V semiconductor layer 200 also may include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other III-V materials or combinations of the above appropriate.In some embodiments, it can be used outside molecular beam Prolong method (molecular-beam epitaxy, MBE), Metalorganic chemical vapor deposition method (metalorganic chemical Vapor deposition, MOCVD), hydride vapour phase epitaxy method (hydride vapor phase epitaxy, HVPE), its His method or combinations of the above appropriate form the first Group III-V semiconductor layer 200 on substrate 100.

Then, as shown in figure 3, the first Group III-V semiconductor layer 200 is patterned, to form one or more fin structures 202.For example, low-pressure chemical vapor deposition process (low-pressure chemical vapor can be used Deposition, LPCVD), plasma auxiliary chemical vapor deposition technique (plasma-enhanced chemical vapor Deposition, PECVD), other techniques or combinations of the above appropriate in the first Group III-V semiconductor layer 200 formed packet Include the curtain layer of hard hood (not being illustrated in figure) of such as silicon nitride, silica material, then with photoetching process (such as: photoresist apply Cloth (resist coating), soft baking (soft baking), exposure (exposure), postexposure bake (post- Exposure baking), development (developing)) patterned photoresist is formed on above-mentioned curtain layer of hard hood, then use Above-mentioned patterned photoresist serves as etching mask and performs etching technique (such as: wet etching, dry etching) on patterning State curtain layer of hard hood.Then, can be used the change curtain layer of hard hood of above-mentioned pattern serve as etching mask perform etching technique (such as: wet type Etching, dry etching) the first Group III-V semiconductor layer 200 of etching, to form one or more fin structures 202.Citing and Speech, above-mentioned dry etch process may include plasma etch process or reaction equation ion etch process.

It should be understood that for brevity, the present embodiment is illustrated by taking two fin structures 202 as an example, however this Invention is not limited according to this, and also visual design requirement forms the fin structure 202 of other quantity to relevant technical staff in the field.

It in some embodiments, can be in formation isolation structure (not being illustrated in figure) on substrate 100.For example, can make With chemical vapour deposition technique (such as: sub-atmospheric pressure chemical vapour deposition technique (sub-atmospheric chemical vapor Deposition, SACVD), high density plasma CVD method (high-density plasma chemical Vapor deposition, HDPCVD) dielectric material is formed in the first Group III-V semiconductor layer 200 and its fin structure 202 On, the technique being then such as etched back to removes extra dielectric material, to form isolation structure between fin structure 202. In some embodiments, the top surface of above-mentioned isolation structure is lower than the top surface 202T of fin structure 202.For example, above-mentioned Isolation structure may include silica, silicon nitride, fire sand, other materials appropriate of carbon silicon oxynitride or combinations of the above.

Please continue to refer to Fig. 3, fin structure 202 can have top surface 202T, two opposite the first side wall 202S1 and Two side wall 202S2.In some embodiments, the second Group III-V semiconductor layer formed in subsequent technique is (such as Fig. 4 A institute The second Group III-V semiconductor layer 402 shown) covering fin structure 202 top surface 202T, the first side wall 202S1 and second Side wall 202S2, therefore the area of Two-dimensional electron cloud (2DEG) can be increased and promote the efficiency of high electron mobility transistor, Yu Hou Text will be explained in.

As shown in figure 3, fin structure 202 has height h and width w.In some embodiments, width w and height h Ratio (also that is, w/h) can not form Two-dimensional electron cloud on the first side wall 202S1 and second sidewall 202S2 less than 0.2. In some other embodiments, the ratio of width w and height h is greater than 10, and can not form Two-dimensional electron cloud in top surface On 202T.Therefore, in the present embodiment, the ratio of width w and height h is 0.2 to 10, to avoid above-mentioned because of width w and height h Ratio it is too big or too small caused by disadvantage.For example, height h can be 0.1 to 2 μm, and width w can be 0.1 to 2 μm.

In some embodiments, on the direction of the side wall perpendicular to fin structure 202, two adjacent fin structures 202 Distance (or pitch) d can be 0.04 to 10 μm.

Then, as shown in fig. 4 a and fig. 4b, the second Group III-V semiconductor layer 402 is formed in the first Group III-V semiconductor layer On 200.Specifically, Fig. 4 B is sectional view depicted in hatching X1-X2 along Fig. 4 A, and hatching X1-X2 on the whole on Perpendicular to the side wall of fin structure 202.

In some embodiments, the second Group III-V semiconductor layer 402 includes different with the first Group III-V semiconductor layer 200 Material to form a heterogeneous engagement, and Two-dimensional electron cloud 404 can be formed in the first Group III-V semiconductor layer 200, can filled When the carrier of high electron mobility transistor.In some embodiments, the second Group III-V semiconductor layer 402 includes undoped III-V group semi-conductor material.For example, in the present embodiment, the second Group III-V semiconductor layer 402 is by undoped AlGaN It is formed, therefore a heterogeneous engagement can be collectively formed with the first Group III-V semiconductor layer 200 is formed by by undoped GaN, But the present invention is not limited according to this.In some other embodiments, the second Group III-V semiconductor layer 402 also may include GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other III-V materials or combinations of the above appropriate.It lifts For example, it can be used that molecular beam epitaxy, Metalorganic chemical vapor deposition method, hydride vapour phase epitaxy method, other are appropriate Method or combinations of the above form the second Group III-V semiconductor layer 402 on the first Group III-V semiconductor layer 200.

As shown in Figure 4 B, the second Group III-V semiconductor layer 402 covers the fin of the first Group III-V semiconductor layer 200 simultaneously Top surface 202T, the first side wall 202S1 and the second sidewall 202S2 of structure 202.In other words, compared to traditional plane Device, the second Group III-V semiconductor layer 402 of the high electron mobility transistor of the embodiment of the present invention and the first iii-v half Conductor layer 200 has biggish contact area, therefore can increase the area of Two-dimensional electron cloud, so that the height electricity of the embodiment of the present invention Transport factor transistor can have biggish electric current and lifting device efficiency in operation.For example, some implementations of the present invention The electric current of the high electron mobility transistor of example in operation is 2 to 5 times of conventional planar device.

In some embodiments, as shown in Fig. 4 A, Fig. 4 B, the second Group III-V semiconductor layer 402 is conformally formed in first On the fin structure 202 of Group III-V semiconductor layer 200.In other words, in these embodiments, between fin structure 202 Space is not filled up by the second Group III-V semiconductor layer 402, therefore the subsequent gate electrode that is formed by may extend into fin structure In space between 202 (gate electrode 504 as shown in Figure 5A), and gate electrode and the second Group III-V semiconductor can be increased Contact area between layer 402 enables gate electrode more effectively to control electric current in device operation.

In some embodiments, as shown in Figure 4 B, the thickness t1 of the second Group III-V semiconductor layer 402 can for 0.005 to 0.1μm。

Then, as shown in Figure 5A, insulating layer 502 is formed on the second Group III-V semiconductor layer 402, can be protected down The film layer of side simultaneously provides physical isolation and structural support.For example, insulating layer 502 may include SiO2, SiN3, SiON, Al2O3, AlN, polyimide (polyimide, PI), benzocyclobutene (benzocyclobutene, BCB), polybenzoxazoles (polybenzoxazole, PBO), other insulating materials or combinations of the above.In some embodiments, chemical gaseous phase can be used Sedimentation (such as: Metalorganic chemical vapor deposition method), method of spin coating (spin-coating), other methods appropriate or Combinations of the above forms insulating layer 502.In some embodiments, insulating layer 502 is through chemical mechanical grinding (chemical Mechanical polishing, CMP) technique and have flat top surface.

Then, as shown in Figure 5A, gate electrode 504 is formed on the second Group III-V semiconductor layer 402, and in grid 504 two sides of electrode form source electrode/drain electrode 506, to form the high electron mobility transistor 10 of the present embodiment.One In a little embodiments, as shown in Figure 5A, gate electrode 504 is in addition to the 2nd III-V on the top surface 202T of covering fin structure 202 Race's semiconductor layer 402 more covers the second Group III-V semiconductor layer 402 on the side wall 202S1 and 202S2 of fin structure 202. In other words, in these embodiments, contact area between gate electrode 504 and the second Group III-V semiconductor layer 402 compared with Greatly, gate electrode 504 is enabled more effectively to control electric current in device operation.

For example, gate electrode 504 may include metal material, metal silicide, polysilicon, other conduction materials appropriate Material or combinations of the above.For example, source/drain electrodes 506 may include Ti, Al, Au, Pd, other metal materials appropriate, Its alloy or combinations of the above.In some embodiments, photoetching process and etching technics can be carried out, with the shape in insulating layer 502 At the groove for corresponding to gate electrode 504 and corresponding to the groove of source electrode/drain electrode 506, then with chemical gaseous phase Sedimentation, physical vaporous deposition (such as evaporation or sputtering), plating, atomic layer deposition method, other methods appropriate or above-mentioned Be combined in above-mentioned groove insert conductive material to form gate electrode 504 and source electrode/drain electrode 506.

B referring to figure 5. shows the high electron mobility transistor of the present embodiment along the hatching Y1-Y2 of Fig. 5 A 10 fragmentary cross-sectional view.Specifically, hatching Y1-Y2 is perpendicular to hatching X1-X2 above-mentioned.As shown in Figure 5 B, high electronics Mobility transistor 10 is the semiconductor device of vague and general type (depletion mode, that is, normally-on), and gate electrode The fin structure 202 of 504 lower sections may act as a channel region, and the fin structure 202 of 504 two sides of gate electrode then may act as source Pole/drain region.

In summary, the high electron mobility transistor of the present embodiment includes having the Group III-V semiconductor of fin structure Layer.Above-mentioned fin structure can increase heterozygous contact area, therefore can increase the area of Two-dimensional electron cloud and improve device Efficiency.

Some change case of the present embodiment presented below.In some embodiments, as shown in Fig. 5 C, Fig. 5 D, high electronics is moved The first doping iii-v is more provided between the gate electrode 504 of shifting rate transistor 10 ' and the second Group III-V semiconductor layer 402 Semiconductor layer 508, so that high electron mobility transistor 10 ' is enhanced (enhanced mode, that is, normally-off) Semiconductor device.

In some embodiments, the first doping Group III-V semiconductor layer 508 may include the Group III-V semiconductor of p-type doping Material may include magnesium, other admixtures appropriate or combinations of the above.For example, in the present embodiment, the first doping III- V race semiconductor layer 508 is formed by the GaN (P-GaN) that p-type is adulterated, but the present invention is not limited according to this.In some other realities Apply in example, first doping Group III-V semiconductor layer 508 also may include p-type doping AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other III-V materials or combinations of the above appropriate.

For example, dopant concentration of the above-mentioned admixture in the first doping Group III-V semiconductor layer 508 can be 1E15/cm3 To 1E20/cm3.

In some embodiments, molecular beam epitaxy, metallochemistry can be used before the step of forming insulating layer 502 Vapour deposition process, hydride vapour phase epitaxy method, other methods or combinations of the above appropriate form undoped iii-v and partly lead Body blanket layer on the second Group III-V semiconductor layer 402, and using as ion implanting technique by admixture be flowed into it is above-mentioned not The Group III-V semiconductor blanket layer that a doping is formed in the Group III-V semiconductor blanket layer of doping, then patterns above-mentioned mix Miscellaneous Group III-V semiconductor blanket layer is to form the first doping Group III-V semiconductor layer 508.For example, above-mentioned pattern chemical industry Skill may include photoetching process, etching technics, other techniques or combinations of the above appropriate.In some other embodiments, also The mode of (in-situ) in situ doping can be used to form the first doping Group III-V semiconductor layer 508.

Since enhancement type high electron mobility transistor 10 ' also includes the Group III-V semiconductor layer with fin structure, because This its also there is the biggish Two-dimensional electron cloud of area and device efficiency can be improved.

[second embodiment: high hole mobility transistor]

Fig. 6 A, Fig. 6 B, Fig. 6 C are the part isometrics for showing the high hole mobility transistor 20 of vague and general type of the present embodiment Figure and fragmentary cross-sectional view.Specifically, Fig. 6 B is the vague and general high hole mobility of type depicted in the hatching X1-X2 along Fig. 6 A The fragmentary cross-sectional view of transistor 20, and Fig. 6 C is the vague and general high hole mobility of type depicted in the hatching Y1-Y2 along Fig. 6 A The fragmentary cross-sectional view of transistor 20.

As shown in Fig. 6 A, Fig. 6 B and Fig. 6 C, the vague and general high hole mobility transistor 20 of type may include substrate 600, be set to The first Group III-V semiconductor layer 602 on substrate 600, the second iii-v being set in the first Group III-V semiconductor layer 602 Semiconductor layer 606, first be set in the second Group III-V semiconductor layer 606 adulterate Group III-V semiconductor layer 608, are set to Insulating layer 610 in first doping Group III-V semiconductor layer 608 and is set to 612 two sides of gate electrode at gate electrode 612 Source/drain electrodes 614.

For example, substrate 600 can be the same as or similar to the substrate 100 of previous embodiment.For example, insulating layer 610 Can be the same as or similar to the insulating layer 502 of previous embodiment, and can be used the same as or similar to the side for being previously formed insulating layer 502 Formula forms insulating layer 610.For example, gate electrode 612 and source/drain electrodes 614 can be the same as or similar to aforementioned implementations The gate electrode 504 and source electrode/drain electrode 506 of example, and can be used the same as or similar to being previously formed gate electrode 504 Gate electrode 612 and source/drain electrodes 614 are formed with the mode of source electrode/drain electrode 506.

In some embodiments, the second Group III-V semiconductor layer 606 includes different with the first Group III-V semiconductor layer 602 Material, to form a heterogeneous engagement, and partly led in being provided with the first doping iii-v in the second Group III-V semiconductor layer 606 Body layer 608 may act as high hole mobility transistor to form two-dimentional electric hole cloud 616 (as shown in Fig. 6 A, Fig. 6 B, Fig. 6 C) Carrier.

As shown in Fig. 6 A, Fig. 6 B and Fig. 6 C, the first Group III-V semiconductor layer of the vague and general high hole mobility transistor 20 of type 602 also include fin structure 604, and the second Group III-V semiconductor layer 606 and the first doping Group III-V semiconductor layer 608 are covered The top surface 604T of lid fin structure 604 and two opposite the first side wall 604S1 and 604S2, therefore two-dimentional electric hole can be increased The area of cloud 616, and promote the efficiency of the high hole mobility transistor 20 of vague and general type.

In some embodiments, the first Group III-V semiconductor layer 602 and the second Group III-V semiconductor layer 606 respectively may be used Including in previous embodiment undoped III-V group semi-conductor material (such as: GaN, AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other III-V materials or combinations of the above appropriate), and the first doping iii-v Semiconductor layer 608 may include in previous embodiment p-type doping III-V group semi-conductor material (such as: p-type doping GaN, AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other III-V materials appropriate or above-mentioned group It closes).For example, in the present embodiment, the first Group III-V semiconductor layer 602 includes undoped AlGaN, the second iii-v Semiconductor layer 606 includes undoped GaN, and the first doping Group III-V semiconductor layer 608 then includes the GaN (P- of p-type doping GaN)。

In some embodiments, the dopant concentration in the first doping Group III-V semiconductor layer 608 can be for 1E13/cm3 extremely 1E22/cm3。

In some embodiments, the step of forming above-mentioned Group III-V semiconductor layer may include molecular beam epitaxy, metallization Vapour deposition process, hydride vapour phase epitaxy method, other methods or combinations of the above appropriate are formed.For example, it can be used Ion implanting or the mode adulterated in situ form the first doping Group III-V semiconductor layer 608.

In some embodiments, as shown in Fig. 6 A and Fig. 6 B, the second Group III-V semiconductor layer 606 is conformally formed in On the fin structure 604 of one Group III-V semiconductor layer 602, and the first doping Group III-V semiconductor layer 608 is also conformally formed In in the second Group III-V semiconductor layer 606.In other words, in these embodiments, space between fin structure 604 not by Second Group III-V semiconductor layer 606 and the first doping Group III-V semiconductor layer 608 are filled up, therefore gate electrode 612 can prolong Increase in the space extended between fin structure 604 gate electrode 612 and first doping Group III-V semiconductor layer 608 it Between contact area, enable gate electrode 612 device operation when more effectively control electric current.

In summary, the high hole mobility transistor of the vague and general type of the present embodiment includes the iii-v with fin structure Semiconductor layer.Above-mentioned fin structure can increase heterozygous contact area, therefore can increase the area of two-dimentional electric hole cloud and mention High device efficiency.

Some change case of the present embodiment presented below.In some embodiments, as shown in 6D, 6E figure, high electronics is moved The second doping is more provided between the gate electrode 612 of shifting rate transistor 20 ' and the first doping Group III-V semiconductor layer 608 Group III-V semiconductor layer 618, so that high hole mobility transistor 20 ' is enhanced semiconductor device.

In some embodiments, the second doping Group III-V semiconductor layer 618 may include the Group III-V semiconductor of n-type doping Material may include silicon, oxygen, other admixtures appropriate or combinations of the above.For example, in the present embodiment, the first III-V Race's semiconductor layer 602 is formed by undoped AlGaN, and the second Group III-V semiconductor layer 606 is formed by undoped GaN, First doping Group III-V semiconductor layer 608 is formed by the GaN that p-type is adulterated, and the second doping Group III-V semiconductor layer 618 is then It is formed by the GaN of n-type doping, but the present invention is not limited according to this.In some other embodiments, the second doping III-V Race's semiconductor layer 618 also may include AlGaN, AlN of n-type doping, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, Other III-V materials or combinations of the above appropriate.

For example, dopant concentration of the above-mentioned admixture in the second doping Group III-V semiconductor layer 618 can be 1E15/cm3 To 1E20/cm3.

In some embodiments, molecular beam epitaxy, metallochemistry can be used before the step of forming insulating layer 610 Vapour deposition process, hydride vapour phase epitaxy method, other methods or combinations of the above appropriate form undoped iii-v and partly lead Body blanket layer is injected above-mentioned admixture using the technique such as ion implanting on the first doping Group III-V semiconductor layer 608 The Group III-V semiconductor blanket layer of a doping is formed in above-mentioned undoped Group III-V semiconductor blanket layer, then pattern Change the Group III-V semiconductor blanket layer of above-mentioned doping to form the second doping Group III-V semiconductor layer 618.For example, above-mentioned Patternized technique may include photoetching process, etching technics, other techniques or combinations of the above appropriate.In some other implementation In example, also the mode adulterated in situ can be used to form the second doping Group III-V semiconductor layer 618.

Since enhanced high hole mobility transistor 20 ' also includes the Group III-V semiconductor layer with fin structure, Therefore it also has the two-dimentional electric hole cloud of larger area and device efficiency can be improved.

Aforementioned interior text outlines the feature of many embodiments, allow in the art related technical personnel from each side Face is better understood by the embodiment of the present invention.Related technical personnel are, it is to be appreciated that and can be easily with the present invention in the art Other techniques and structure are designed or modified based on embodiment, and identical purpose is reached with this and/or reaches and is situated between herein The identical advantage such as the embodiment to continue.In the art related technical personnel it will also be appreciated that these equal structures without departing from The spirit and range of the embodiment of the present invention.It, can under the premise of without departing substantially from the spirit and range of the embodiment of the present invention Various changes, displacement or modification are carried out to the embodiment of the present invention.

In addition, each claim of this exposure can be an other embodiment, and the range of this exposure includes this exposure Each claim and the mutual combination of each embodiment.

Claims

1. A semiconductor device, comprising:

a substrate;

a first III-V semiconductor layer disposed on the substrate, wherein the first III-V semiconductor layer includes a fin structure, and the fin structure includes a top surface, a first sidewall and a a second side wall of the first side wall;

a second group III-V semiconductor layer disposed on the first group III-V semiconductor layer, wherein the first group III-V semiconductor layer and the second group III-V semiconductor layer comprise different materials, and The second III-V semiconductor layer covers the top surface, the first sidewall and the second sidewall of the fin structure to be along the top surface, the first sidewall and the second sidewall of the fin structure The second sidewall forms a heterojunction; and

A gate electrode is disposed on the second group III-V semiconductor layer.

2 . The semiconductor device of claim 1 , wherein the second group III-V semiconductor layer is conformally disposed on the first group III-V semiconductor layer. 3 .

3. The semiconductor device of claim 1, further comprising:

A first doped III-V semiconductor layer is disposed between the second III-V semiconductor layer and the gate electrode.

4 . The semiconductor device of claim 3 , wherein the first doped group III-V semiconductor layer is conformally disposed on the second group III-V semiconductor layer. 5 .

5 . The semiconductor device of claim 3 , wherein the first doped III-V semiconductor layer comprises a P-type doped III-V semiconductor. 6 .

6. The semiconductor device of claim 5, wherein the first group III-V semiconductor layer comprises GaN, the second group III-V semiconductor layer comprises AlGaN, and the first group III-V semiconductor layer is doped The layers include P-type doped GaN.

7. The semiconductor device of claim 5, wherein the first group III-V semiconductor layer comprises AlGaN, the second group III-V semiconductor layer comprises GaN, and the first group III-V semiconductor layer is doped The layers include P-type doped GaN.

8. The semiconductor device of claim 3, further comprising:

A second doped III-V semiconductor layer is disposed between the first doped III-V semiconductor layer and the gate electrode.

9 . The semiconductor device of claim 8 , wherein the first doped III-V semiconductor layer comprises a P-type doped III-V semiconductor, and the second doped III-V semiconductor layer. 10 . Including N-type doped III-V semiconductors.

10. The semiconductor device of claim 9, wherein the first group III-V semiconductor layer comprises AlGaN, the second group III-V semiconductor layer comprises GaN, and the first group III-V semiconductor layer is doped The layer includes P-type doped GaN, and the second doped III-V semiconductor layer includes N-type doped GaN.

11. A method for forming a semiconductor device, comprising:

providing a substrate;

forming a first group III-V semiconductor layer on the substrate, wherein the first group III-V semiconductor layer includes a fin structure, and the fin structure includes a top surface, a first sidewall and relative to the a second side wall of the first side wall;

forming a second group III-V semiconductor layer on the first group III-V semiconductor layer, wherein the first group III-V semiconductor layer and the second group III-V semiconductor layer comprise different materials, and the A second III-V semiconductor layer covers the top surface, the first sidewall and the second sidewall of the fin structure to be along the top surface, the first sidewall and the second sidewall of the fin structure The two sidewalls form a heterojunction; and

A gate electrode is formed on the second III-V semiconductor layer.

12 . The method of claim 11 , wherein the second group III-V semiconductor layer is conformally formed on the first group III-V semiconductor layer. 13 .

13. The method for forming a semiconductor device according to claim 11, wherein after forming the second III-V semiconductor layer and before forming the gate electrode, further comprising:

A first doped III-V semiconductor layer is formed on the second III-V semiconductor layer.

14 . The method of claim 13 , wherein the first doped III-V semiconductor layer is conformally formed on the second III-V semiconductor layer. 15 .

15 . The method of claim 13 , wherein the first doped III-V semiconductor layer comprises a P-type doped III-V semiconductor. 16 .

16 . The method of claim 15 , wherein the first group III-V semiconductor layer comprises GaN, the second group III-V semiconductor layer comprises AlGaN, and the first doped III- The group V semiconductor layer includes P-type doped GaN.

17 . The method of claim 15 , wherein the first group III-V semiconductor layer comprises AlGaN, the second group III-V semiconductor layer comprises GaN, and the first doped III- The group V semiconductor layer includes P-type doped GaN.

18. The method for forming a semiconductor device as claimed in claim 13, further comprising: after forming the first doped III-V semiconductor layer and before forming the gate electrode:

A second doped III-V semiconductor layer is formed on the first doped III-V semiconductor layer.

19 . The method of claim 18 , wherein the first doped III-V semiconductor layer comprises a P-type doped III-V semiconductor, and the second doped III-V semiconductor layer. 20 . The group semiconductor layer includes N-type doped group III-V semiconductors.

20. The method of claim 19, wherein the first group III-V semiconductor layer comprises AlGaN, the second group III-V semiconductor layer comprises GaN, and the first doped III- The group V semiconductor layer includes P-type doped GaN, and the second doped group III-V semiconductor layer includes N-type doped GaN.