CN109616477A - Array substrate, method for preparing array substrate and display terminal - Google Patents
Array substrate, method for preparing array substrate and display terminal Download PDFInfo
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- CN109616477A CN109616477A CN201811549375.8A CN201811549375A CN109616477A CN 109616477 A CN109616477 A CN 109616477A CN 201811549375 A CN201811549375 A CN 201811549375A CN 109616477 A CN109616477 A CN 109616477A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 127
- 239000002184 metal Substances 0.000 claims abstract description 127
- 239000010409 thin film Substances 0.000 claims abstract description 23
- 239000010408 film Substances 0.000 claims description 54
- 239000004973 liquid crystal related substance Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 11
- 239000012528 membrane Substances 0.000 claims description 10
- 238000002360 preparation method Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 19
- 230000000694 effects Effects 0.000 abstract description 9
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- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 4
- 229910003437 indium oxide Inorganic materials 0.000 description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 4
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- 238000005240 physical vapour deposition Methods 0.000 description 2
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- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
本发明涉及一种阵列基板、制备阵列基板的方法和显示终端；阵列基板包括：基底，设置有薄膜晶体管；屏蔽金属，设置于基底上，且对薄膜晶体管的沟道予以遮挡；像素电极，设置于屏蔽金属之上；其中，屏蔽金属在基底上的投影与像素电极在基底上的投影之间具有预设间隙。这就确保了屏蔽金属与像素电极之间不会有电场线分布，极大地消除了电场的边缘效应，从而使像素电极边缘处不会产生暗纹问题。
The invention relates to an array substrate, a method for preparing the array substrate and a display terminal; the array substrate comprises: a base provided with a thin film transistor; a shielding metal provided on the base and shielding the channel of the thin film transistor; a pixel electrode provided with on the shielding metal; wherein, there is a predetermined gap between the projection of the shielding metal on the substrate and the projection of the pixel electrode on the substrate. This ensures that there is no electric field line distribution between the shielding metal and the pixel electrode, which greatly eliminates the edge effect of the electric field, so that the problem of dark streaks does not occur at the edge of the pixel electrode.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of array substrate, prepare the method for array substrate and show
Show terminal.
Background technique
As society continues to develop, LCD technology (Liquid Crystal Display, abbreviation LCD) has replaced yin
Extreme ray imaging technique (Cathode Ray Tube, abbreviation CRT) becomes mainstream.
Generally, liquid crystal display panel includes color membrane substrates and the array substrate with the color membrane substrates to box, in the coloured silk film
Liquid crystal is provided between substrate and array substrate.
The pixel electrode that traditional array substrate generally comprises shielding metal and is set on shielding metal, however,
After array substrate is powered, in pixel electrode, by the side of close shield metal, there may be dark lines, influence display effect.
Summary of the invention
Based on this, it is necessary to the method and display terminal that a kind of array substrate is provided, prepares array substrate, to reduce display
The problem of dark line.
A kind of array substrate, can be applied in liquid crystal display panel, and the array substrate includes:
Substrate is provided with thin film transistor (TFT)；
Metal is shielded, is set in the substrate, and the channel of the thin film transistor (TFT) is blocked；
Pixel electrode is set on the shielding metal；
Wherein, it is described shielding metal on the substrate projection with the projection of the pixel electrode on the substrate it
Between have prepsetting gap.
0≤D≤10 μm in one of the embodiments, D are the prepsetting gap.
The array substrate further includes the insulating layer being set on the shielding metal in one of the embodiments,；Institute
Pixel electrode is stated to be set on the insulating layer；
Wherein, the shielding metal is ring structure, and the hollow region that the pixel electrode passes through the ring structure is thrown
On shadow to the substrate.
The material of the shielding metal includes at least one of molybdenum, copper and silver in one of the embodiments,.
A method of preparing array substrate, comprising:
The substrate for being provided with thin film transistor (TFT) is provided；
The preparation shielding metal above the substrate；The shielding metal hides the channel of the thin film transistor (TFT)
Gear；
Pixel electrode is prepared above the shielding metal；
Wherein, it is described shielding metal on the substrate projection with the projection of the pixel electrode on the substrate it
Between have prepsetting gap.
The step of preparing pixel electrode above the be set forth in shielding metal in one of the embodiments, comprising:
Transparent conductive film is prepared above the shielding metal；
The pixel electrode is prepared according to the transparent conductive film.
The projection of the transparent conductive film on the substrate and the pixel electrode exist in one of the embodiments,
Projection section overlapping in the substrate；Described the step of pixel electrode is prepared according to the transparent conductive film, comprising:
Part Chong Die with the shielding metal in the transparent conductive film is removed using etching technics, described in obtaining
Pixel electrode.
The shielding metal is the cyclic structure with hollow region in one of the embodiments,；
Wherein, the prepsetting gap is the internal diameter and/or the reduction pixel electrode by increasing the hollow region
Size is formed.
A kind of display terminal, comprising:
Apparatus body, including multiple function elements；
Display panel is covered on the apparatus body, and is connect with the multiple function element；
Wherein, the display panel includes the array substrate as described in Claims 1-4 any one.
The display panel further includes color membrane substrates and liquid crystal layer in one of the embodiments,；
Wherein, the two sides of the liquid crystal layer are arranged in the color membrane substrates and the array substrate.
It in above-mentioned array substrate, prepares in the method and display terminal of array substrate, by changing shielding metal and pixel
The relative position of electrode, so that shielding projection and pixel electrode of the metal in substrate in base on the direction for being parallel to substrate
There is prepsetting gap between projection on bottom, namely be not overlapped, it is ensured that do not have electric field between shielding metal and pixel electrode
Line distribution, substantially eliminates the edge effect of electric field, so that pixel electrode edge be made not lead to the problem of dark line.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of array substrate in one embodiment；
Fig. 2 is the structural schematic diagram of array substrate in traditional technology；
Fig. 3 is the flow chart that the method for array substrate is prepared in one embodiment；
Fig. 4 to Fig. 5 is the Structure and Process schematic diagram that array substrate is prepared in one embodiment.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
The present embodiment provides a kind of array substrate, especially a kind of array substrate being arranged in liquid crystal display panel.Tool
Body, which can include at least the substrate for being provided with thin film transistor (TFT), shielding metal and pixel electrode；Wherein, shield
It covers metal and can be and be arranged in substrate and the channel of thin film transistor (TFT) is blocked, to avoid generating illumination leakage current.
Pixel electrode can be setting above shielding metal.Particularly, different film layer knots should be located at by shielding metal and pixel electrode
It in structure and mutually staggers, namely shielding metal should have one in the projection in substrate and pixel electrode between the projection in substrate
The gap of default size.
It will be understood by those skilled in the art that substrate, shielding metal and pixel electrode are merely to realize the object of the invention
In the process, the minimum film layer structure having needed for array substrate, however, in order to enable array substrate have the function of it is richer,
Array substrate in above-described embodiment can also increase the film layer structure either function of other function according to actual needs
Device.
In the above-described embodiments, pixel electrode needs to be arranged above shielding metal, and guarantees pixel electrode and shielding
Metal is located in different film layer structures.It is understood, however, that pixel electrode and shielding metal between can be set just like
Other film layer structures such as insulating layer.In one embodiment, it is also possible to upper one layer that pixel electrode is formed in shielding metal
In film layer, at this point, it should be understood that in order to guarantee projection and barrier film layer projection on substrate of the pixel electrode in substrate it
Between have a prepsetting gap, shielding metal should be located in same film layer structure with other devices, and pixel electrode can be formed in this
On other devices.
In above-mentioned array substrate, by changing the relative position of shielding metal and pixel electrode, so that being parallel to base
On the direction at bottom, shielding metal has prepsetting gap in the projection in substrate and pixel electrode between the projection in substrate,
It not being overlapped, it is ensured that shielding metal and pixel electrode can not constitute capacitance structure, this is allowed for after array substrate is powered,
Electric field line distribution is not had between shielding metal and pixel electrode, the edge effect of electric field is substantially eliminated, to make pixel
The marginal portion of electrode will not lead to the problem of dark line.
In one embodiment, can will shield projection and pixel electrode projection on substrate of the metal in substrate it
Between prepsetting gap be indicated with D, it is clear that D is greater than equal to 0 μm, in order to guarantee to go out to be unlikely in the gap to generate light leakage
Problem, therefore D can also be set less than or equal to 10 μm.
In one embodiment, in order to enable barrier film layer can have good shielding character, metal material can be used
Material preparation barrier film layer.In general, the shielding character of the metals such as molybdenum, copper, silver is more preferable with respect to for other metals, therefore can be with
Barrier film layer is prepared using the pure metal either alloy of molybdenum, copper, silver.However, in a preferred embodiment, using copper
Standby barrier film layer is a preferably selection, this is because copper is more easy to get with respect to other metals, and just with the standby shielding gold of copper
Belong in contrast more cheap, there are better economic benefits.
In one embodiment, in order to enable pixel electrode light transmission, the material of pixel electrode can be indium tin oxide
(ITO).When the material of pixel electrode is indium tin oxide, pixel electrode can have higher conductivity, higher visible
Light transmission rate, higher mechanical hardness and good chemical stability.Certainly, in other embodiments, the material of pixel electrode
It may be indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium (IGO) or aluminum zinc oxide (AZO)
Deng.
In one embodiment, array substrate can also include the insulating layer being set on shielding metal；Pixel electrode can
To be arranged on which insulating layer.Shielding metal can also be ring structure, there is a hollow region in the ring structure.Pixel electricity
Pole can be set above shielding metal at the position of the corresponding hollow region, namely make projection of the pixel electrode in substrate can
To pass through the hollow region.
The present embodiment provides a kind of method for preparing array substrate, this method can be used for preparing the battle array in above-described embodiment
Column substrate.The above method may include following step:
Step S1: the substrate for being provided with thin film transistor (TFT) is provided.
Specifically, substrate can be prepared, first in order to form each film layer structure in subsequent substrate again.
Step S2: in preparation shielding metal in substrate；Shielding metal blocks the channel of thin film transistor (TFT).
Specifically, after preparing substrate, shielding metal can be formed on the substrate, also, the shielding metal can be to thin
The channel of film transistor is blocked to prevent illumination leakage current.It will be understood by those skilled in the art that this step is specific
Including but not limited to: the direct whole face of metal will be shielded and be formed in substrate, shielding metal and other devices are collectively formed in base
On bottom and the shielding metal and other devices are located in same film layer structure.
Step S3: transparent conductive film is prepared above shielding metal.
Specifically, it after forming shielding metal, can be prepared in any film layer being located above shielding metal transparent
Conductive film.It will be understood by those skilled in the art that transparent conductive film and shielding metal are located in different film layer structures
, also, one layer, two or more layers other film layer structures can be set between transparent conductive film and shielding metal.
Step S4: pixel electrode is prepared according to transparent conductive film.
It specifically, can be using the including but not limited to etching technics such as wet etching after foring transparent conductive film
Transparent conductive film is performed etching, and part overlapped with shielding metal in transparent conductive film is removed, and
Finally make projection of the projection of remaining transparent conductive film namely pixel electrode in substrate with shielding metal in substrate
Between have prepsetting gap.
In the method for above-mentioned preparation array substrate, by changing the relative position of shielding metal and pixel electrode, so that
On the direction for being parallel to substrate, shielding metal has between the projection in substrate pre- in the projection in substrate and pixel electrode
If gap, namely be not overlapped, it is ensured that shielding metal and pixel electrode can not constitute capacitance structure, this allows for working as array substrate
After energization, electric field line distribution is not had between shielding metal and pixel electrode, substantially eliminates the edge effect of electric field, from
And the marginal portion of pixel electrode is made not lead to the problem of dark line.
The present embodiment provides the methods of another preparation array substrate, and can specifically include: preparation is provided with film crystal
The substrate of pipe；Metal is shielded in preparation in substrate, shielding metal is the cyclic structure with hollow region, and to thin film transistor (TFT)
Channel blocked；Pixel electrode is prepared above shielding metal.It in the present embodiment, can be by increasing hollow region
Internal diameter and/or the size for reducing pixel electrode are come so that shielding projection and pixel electrode throwing on substrate of the metal in substrate
There is prepsetting gap between shadow.
Specifically, in one embodiment, it can be traditionally used for being formed the light shield for shielding metal by increasing, so that shape
At shielding metal phase for traditional shielding metal the hollow region with larger inner diameter, this is allowed for perpendicular to substrate
Direction on, pixel electrode can be located at the hollow region in, ensure that pixel electrode and shielding metal between do not have overlapping.
In other embodiments, it can also be traditionally used for forming the light shield of pixel electrode by reduction, so that the pixel electrode formed
There is smaller size, this is allowed in a direction that is perpendicular to the base, and pixel electrode can for relatively traditional pixel electrode
To be located in the hollow region shielded on metal, it ensure that and not have overlapping between pixel electrode and shielding metal.
In order to make those skilled in the art fully understand the present invention, the present invention is further expalined below in conjunction with attached drawing
Explanation.
Fig. 1 is the structural schematic diagram of array substrate in one embodiment, as shown in Figure 1, the present embodiment provides a kind of arrays
Substrate is applied in liquid crystal display panel, which may include the base for being provided with thin film transistor (TFT) (not shown)
Bottom 10, shielding metal 11 and pixel electrode 12.Wherein, shielding metal 11 can be set on the substrate 10, and pixel electrode 12 can be with
Setting is above shielding metal 11.
In one embodiment, shielding metal 11 can directly whole face coat on the substrate 10, can also be with such as black
Other devices such as light shielding block (not shown) are located in same film layer structure.
In one embodiment, pixel electrode 12 is located in different film layer structures from shielding metal 11, also, vertical
In on the direction that substrate 10 extends, the projection of pixel electrode 12 on the substrate 10 and the projection on the substrate 10 of shielding metal 11 it
Between there is the gap of default size, that is, shielding metal 11 does not form capacitive junctions with pixel electrode 12 when array substrate is powered
Structure.However, those skilled in the art should know be also provided with buffer layer between pixel electrode 12 and shielding metal 11
The film layer structures such as (not shown), insulating layer (not shown), as long as shielding metal 11 does not form electricity with pixel electrode 12
Hold structure, namely when being powered, shields between metal 11 and pixel electrode 12 without electric field line formation.
Such as the structural schematic diagram that Fig. 2 is array substrate in traditional technology.As shown in Fig. 2, in the conventional technology, array substrate
It may include shielding metal 20 and the pixel electrode 21 above shielding metal.Specifically, metal 20 and pixel electrode are shielded
There is lap, that is to say, that shielding metal and pixel electrode form capacitance structure, this is allowed in array base between 21
After plate is powered, electric field line can be generated between barrier film layer and pixel electrode.However, being located at pixel due to the edge effect of electric field
The electric field line of 21 edge of electrode will change original linear, become bending, this allows for being distributed in the bending electric field
Liquid crystal (not shown) at line and the liquid crystal toppling direction being distributed at linear electric field line are inconsistent, to cause bright dark
Difference, namely dark line is generated in the edge.
And as shown in Figure 1, in the above-described embodiments, by changing the relative position of shielding metal and pixel electrode, so that
On the direction extended perpendicular to the substrate, shield projection and pixel electrode projection on substrate of the metal in substrate it
Between there is prepsetting gap, namely be not overlapped, it is ensured that do not have electric field line distribution between shielding metal and pixel electrode, greatly
The edge effect of electric field is eliminated, so that pixel electrode edge be made not lead to the problem of dark line.
In one embodiment, in order to which the edge effect for eliminating as much as electric field is shielded on the direction for being parallel to substrate 10
The prepsetting gap D covered between the projection of projection and pixel electrode 12 on the substrate 10 of metal 11 on the substrate 10 should be as far as possible
Greatly.However, if the prepsetting gap is excessive, and the problem of be easy to produce light leakage.Therefore D can be set more than or equal to 0 μm, and be less than etc.
In 10 μm；For example, 0,2 μm, 4 μm, 6 μm, 8 μm or 10 μm etc..
In one embodiment, shielding metal 11 can be the metal materials such as molybdenum, copper, silver so that shielding metal 11 can be more
Play shielding action well.In other embodiments, the material of pixel electrode 12 is also possible to ITO.
Fig. 3 is the flow chart that the method for array substrate is prepared in one embodiment.As shown in figure 3, based on the above embodiment
In array substrate, the present embodiment provides a kind of method for preparing array substrate, this method be may include steps of:
Step S1: the substrate for being provided with thin film transistor (TFT) is provided.
Specifically, Fig. 4 to Fig. 5 is the Structure and Process schematic diagram that array substrate is prepared in one embodiment, as shown in figure 4,
Substrate 40 can be by such as glass material, metal material or including polyethylene terephthalate (PET), poly- naphthalenedicarboxylic acid second
Suitable material is formed in the plastic material of diol ester (PEN) or polyimides etc., and film crystalline substance can be set in substrate
Body pipe (not shown).
Step S2: in preparation shielding metal in substrate；Shielding metal blocks the channel of the thin film transistor (TFT).
Specifically, screen can be formed by PVD (physical vapor deposition, including vapor deposition and sputter etc.) method on the substrate 40
Metal 41 is covered, and the shielding metal 41 should be able to block the channel of thin film transistor (TFT), to avoid illumination leakage current is generated.
Step S3: transparent conductive film is prepared above shielding metal.
In some embodiments, after forming shielding metal 41, buffer layer can first be sequentially formed on shielding metal 41
42, the devices film layer such as insulating layer 43, then transparent conductive film 44 is formed on insulating layer 43.Wherein, transparent conductive film 44 can
To use transparent conductive metal material such as indium tin oxide (ITO), so that transparent conductive film has high conductivity, high
Visible light transmittance, high mechanical hardness and good chemical stability.In other embodiments, the material of transparent conductive film 44
Matter may be indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium (IGO) or aluminum zinc oxide
(AZO)。
Step S4: pixel electrode is prepared according to transparent conductive film.
In one embodiment, passivation layer 45 can be formed on transparent conductive film 44, wherein be parallel to substrate 40
Direction on, have between the projection and the projection on the substrate 40 of shielding metal 41 of passivation layer 45 on the substrate 40 one it is default between
Gap.
In one embodiment, wet etching can be carried out to transparent conductive film 44, thus by transparent conductive film 44
The partial etching that upper unpassivated layer 45 covers falls, to form pixel electrode 50 as shown in Figure 5.It is possible to further incite somebody to action
Passivation layer 45 removes.As a result, on the direction for being parallel to substrate 40, the projection on the substrate 40 of shielding metal 41 and pixel electrode
There is above-mentioned prepsetting gap between 50 projection on the substrate 40.
In the above-described embodiments, by successively forming shielding metal and pixel electrode, so that in the direction for being parallel to substrate
On, shielding metal has prepsetting gap in the projection in substrate and pixel electrode between the projection in substrate, namely is not overlapped,
It ensures and does not have electric field line distribution between shielding metal and pixel electrode, substantially eliminate the edge effect of electric field, thus
Pixel electrode edge is set not lead to the problem of dark line.
The present embodiment provides a kind of liquid crystal display panels, can specifically include: array substrate, color membrane substrates and liquid crystal layer；
Wherein, the two sides of liquid crystal layer are arranged in color membrane substrates and array substrate.The array substrate can also specifically include: substrate, setting
There is thin film transistor (TFT)；Metal is shielded, is set in substrate, and the channel of thin film transistor (TFT) is blocked；Pixel electrode, setting
On shielding metal；Wherein, shielding metal has between the projection in substrate pre- in the projection in substrate and pixel electrode
If gap.
The present embodiment provides a kind of display terminal, which can be mobile phone, computer, wrist-watch etc. with display function
Electronic equipment, further, which can specifically include: apparatus body, including multiple function elements；Liquid crystal display
Panel is covered on apparatus body, and is connect with multiple function elements.Specifically, liquid crystal display panel can be covered on equipment
For showing picture on ontology；It is also provided with the function elements such as brightness regulation key, power key on apparatus body, and can be with
It is connect with liquid crystal display panel, with display brightness, the switch etc. for controlling liquid crystal display panel.In the present embodiment, liquid crystal display
Panel can specifically include: array substrate, color membrane substrates and liquid crystal layer；Wherein, color membrane substrates and array substrate are arranged in liquid crystal
The two sides of layer.The array substrate can also specifically include: substrate is provided with thin film transistor (TFT)；Metal is shielded, substrate is set to
On, and the channel of thin film transistor (TFT) is blocked；Pixel electrode is set on shielding metal；Wherein, shielding metal is in base
Projection and pixel electrode on bottom have prepsetting gap between the projection in substrate.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of array substrate, which is characterized in that the array substrate includes:
Substrate is provided with thin film transistor (TFT)；
Metal is shielded, is set in the substrate, and the channel of the thin film transistor (TFT) is blocked；
Pixel electrode is set on the shielding metal；
Wherein, have between the projection of projection and the pixel electrode on the substrate of the shielding metal on the substrate
There is prepsetting gap.
2. array substrate according to claim 1, which is characterized in that 0≤D≤10 μm, D are the prepsetting gap.
3. array substrate according to claim 1, which is characterized in that the array substrate further includes being set to the shielding
Insulating layer on metal；The pixel electrode is set on the insulating layer；
Wherein, the shielding metal be ring structure, the pixel electrode pass through the ring structure hollow region project to
In the substrate.
4. array substrate according to claim 1, which is characterized in that the material of the shielding metal includes molybdenum, copper and silver
At least one of.
5. a kind of method for preparing array substrate characterized by comprising
The substrate for being provided with thin film transistor (TFT) is provided；
The preparation shielding metal above the substrate；The shielding metal blocks the channel of the thin film transistor (TFT)；
Pixel electrode is prepared above the shielding metal；Wherein, the shielding metal projection on the substrate with it is described
There is prepsetting gap between the projection of pixel electrode on the substrate.
6. according to the method described in claim 5, preparing pixel electrode it is characterized in that, being set forth in above the shielding metal
Step, comprising:
Transparent conductive film is prepared above the shielding metal；
The pixel electrode is prepared according to the transparent conductive film.
7. according to the method described in claim 6, it is characterized in that, the projection of the transparent conductive film on the substrate with
The projection section overlapping of the pixel electrode on the substrate, it is described that pixel electrode is prepared according to the transparent conductive film
Step, comprising:
Part Chong Die with the shielding metal in the transparent conductive film is removed, using etching technics to obtain the pixel
Electrode.
8. according to the method described in claim 5, it is characterized in that, the shielding metal is the cyclic annular knot with hollow region
Structure；
Wherein, the prepsetting gap is the size of the internal diameter and/or the reduction pixel electrode by increasing the hollow region
It is formed.
9. a kind of display terminal characterized by comprising
Apparatus body, including multiple function elements；
Display panel is covered on the apparatus body, and is connect with the multiple function element；
Wherein, the display panel includes the array substrate as described in Claims 1-4 any one.
10. display terminal as claimed in claim 9, which is characterized in that the display panel further includes color membrane substrates and liquid crystal
Layer；
Wherein, the two sides of the liquid crystal layer are arranged in the color membrane substrates and the array substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811549375.8A CN109616477A (en) | 2018-12-18 | 2018-12-18 | Array substrate, method for preparing array substrate and display terminal |
| PCT/CN2018/123870 WO2020124638A1 (en) | 2018-12-18 | 2018-12-26 | Array substrate, method for manufacturing array substrate, and display terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811549375.8A CN109616477A (en) | 2018-12-18 | 2018-12-18 | Array substrate, method for preparing array substrate and display terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109616477A true CN109616477A (en) | 2019-04-12 |
Family
ID=66009796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811549375.8A Pending CN109616477A (en) | 2018-12-18 | 2018-12-18 | Array substrate, method for preparing array substrate and display terminal |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109616477A (en) |
| WO (1) | WO2020124638A1 (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030043328A1 (en) * | 2001-09-05 | 2003-03-06 | Hisaaki Hayashi | Plane display element |
| US20080062342A1 (en) * | 2003-06-24 | 2008-03-13 | Song Hong S | Liquid crystal display panel |
| CN101276078A (en) * | 2007-03-29 | 2008-10-01 | Nec液晶技术株式会社 | Liquid crystal display device |
| US20110063535A1 (en) * | 2009-09-11 | 2011-03-17 | Hannstar Display Corp. | Pixel structure of liquid crystal display panel |
| CN103676375A (en) * | 2013-12-09 | 2014-03-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof |
| CN104880879A (en) * | 2015-06-19 | 2015-09-02 | 京东方科技集团股份有限公司 | COA array substrate and manufacturing method and display device thereof |
| CN106019750A (en) * | 2016-08-10 | 2016-10-12 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
| CN108803179A (en) * | 2018-07-26 | 2018-11-13 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2638713B2 (en) * | 1992-07-16 | 1997-08-06 | 株式会社フロンテック | Active matrix liquid crystal display |
| CN102033367B (en) * | 2009-09-25 | 2013-05-08 | 北京京东方光电科技有限公司 | Display substrate and manufacturing method thereof |
| CN104597643A (en) * | 2015-01-30 | 2015-05-06 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof, and display device |
-
2018
- 2018-12-18 CN CN201811549375.8A patent/CN109616477A/en active Pending
- 2018-12-26 WO PCT/CN2018/123870 patent/WO2020124638A1/en not_active Ceased
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030043328A1 (en) * | 2001-09-05 | 2003-03-06 | Hisaaki Hayashi | Plane display element |
| US20080062342A1 (en) * | 2003-06-24 | 2008-03-13 | Song Hong S | Liquid crystal display panel |
| CN101276078A (en) * | 2007-03-29 | 2008-10-01 | Nec液晶技术株式会社 | Liquid crystal display device |
| US20110063535A1 (en) * | 2009-09-11 | 2011-03-17 | Hannstar Display Corp. | Pixel structure of liquid crystal display panel |
| CN103676375A (en) * | 2013-12-09 | 2014-03-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof |
| CN104880879A (en) * | 2015-06-19 | 2015-09-02 | 京东方科技集团股份有限公司 | COA array substrate and manufacturing method and display device thereof |
| CN106019750A (en) * | 2016-08-10 | 2016-10-12 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
| CN108803179A (en) * | 2018-07-26 | 2018-11-13 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
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|---|---|
| WO2020124638A1 (en) | 2020-06-25 |
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Application publication date: 20190412 |