CN1096029C - DASD capacity in excess of 528 megabytes apparatus and method for personal computers - Google Patents

Abstract

This disclosure relates to translating cylinder-head-sector (CHS) addressing of digital data written to or read from a DASD so as to accommodate DASD storage capacities in excess of the approximately five hundred twenty eight megabyte capacity limit imposed by Interrupt 13 design in an Industry Standard Architecture personal computer system. A CHS (cylinder-head-sector) address in a first frame of reference which meets the restraints of Interrupt 13 design in the ISA BIOS is translated to a CHS address in a second frame of reference which meets the physical characteristics of a DASD which is otherwise outside the restraints of Interrupt 13 design in the ISA BIOS.

Description

DASD device and method with a capacity exceeding 528 megabytes in a personal computer

In many sectors of modern society today, personal computer systems, especially the IBM personal computer, are widely used to provide computing power. Usually a personal computer system can be defined as a desktop computer, a tower computer, or a portable microcomputer, which includes a system unit with a single system processor with volatile and nonvolatile memory, a display, a keyboard , one or more floppy disk drives, a fixed disk storage, and an optional printer or plotter. A prominent feature of these systems is the use of a motherboard, or system plane, to electrically connect the many components. These systems are primarily designed for single-user use to provide a single source of computing power and are inexpensively purchased by individuals or small businesses. Examples of such personal computer systems are IBM's PCAT, PS/1, PS/2, and THINKPAD systems.

These systems can be divided into two broad families. The first family, often called Family I Mod-els, used the system and bus architecture represented by the IBM PC AT and other "IBM compatible" machines. The second family is called Family II Models, and they use IBM's Microchannel bus architecture represented by IBM's PS/2 Models 50 through 95. Family Imodels initially used the INTEL8088 or 8086 microprocessor as the system processor. These processors are capable of accessing one megabyte of random access memory (also known as RAM, the non-volatile memory used as working memory in personal computer systems). Family IImodels use high-speed INTEL80286, 80386, 80486, and Pentium microprocessors. These microprocessors can work in real address mode to emulate slower IN-TEL8086 microprocessors, and can also operate in protected mode. This mode extends the memory addressing range of one megabyte to 4GB for some models. Essentially, the real-address mode feature of the 80286, 80386, and 80486 processors provides hardware compatibility for software on the 8086 and 8088 processors.

Since the "Family I" personal computer systems were designed to conform to the standards followed by large segments of the personal computer industry, these systems have come to be known as "Industry Standard Architecture" or ISA systems. These standards include certain runtime calls used by the control programs that implement system functions. These control programs are often referred to as the "Basic Input/Output System" or BIOS, and ISA systems follow the BIOS design presented in the IBM BIOS data sheet. For the purposes of disclosing the present invention, a significant portion of the above material is that which pertains to interrupt 13 operations, which appear on pages 2-58 and in the material cited thereafter. Interrupt 13 specifies the mode of operation for addressing of ISA systems and fixed disk or direct access storage devices (also known as DASD), examples of which are large storage capacity, fixed rotating magnetic (or other) media disk drives or hard drive or hard drive. These DASDs differ from "floppy" disks in that the latter's magnetic (or other) media is removable rather than fixed.

DASDs for ISA personal computer systems are also known as "attachable to AT" or "ATA" drives. In systems designed earlier, DASD was typically used with a controller separate from the drive. Communication of digital data between the DASD and the rest of the computer system is controlled by a controller, which in early designs was a card or add-in board that fits in a socket on an input/output or I/O bus (see The Winn Rosch Hardware Bible Simon & Schuster, New York, 1989, p. 475). The operation of the controller is to find the address of the digital data written to or read from the rotating disk of the DASD through the tracks (here also referred to as cylinders) and sectors. Furthermore, since DASDs normally have a multitude of disks or boards stacked together and serviced by a multitude of heads, the addressing operation is performed by the head that will access the desired cylinder portion or sector. This addressing is called cylinder-head-sector or CHS addressing.

Due to certain limitations of the interrupt 13 design, the ISA personal computer system expects to address 1024 cylinders and up to 256 heads. However, DASD designs do not always easily meet these requirements. Alternatively, DASD designers and manufacturers can provide more cylinders and heads than the maximum expected for interrupt 13 designs. Under normal circumstances, ATA DASD has 16 heads. However, the addressing of cylinders is limited to 1024, the sector size per track is inherently limited to 63, and each sector is limited to 512 bytes, which limits the addressability of this 16-head ATA DASD. Limited to 528,482,304 bytes (1024×16×63×512).

As the ISA personal computer system continues to develop, another solution to DASD control appears. This includes Integrated Drive Electronics (herein also referred to as IDE) type devices in which the electronics are integral to the DASD structure rather than mounted on the controller board. This eliminates the need for the IDE DASD to be installed with a separately provided controller board, thereby saving a slot or socket on the I/O bus. Another solution used by some systems is: install the DASD controller directly on the system motherboard or flat panel, and also install the DASD separately from the separately provided controller plug-in board, thus saving I/O A slot or socket on a bus. Neither of these methods solves the problem of addressing beyond 1024 cylinders in such drives when using the previous CHS data.

As advances are made in the design domain, so are advances in the design and manufacture of DASDs. As a result, there have been drives whose capacity exceeds the ceiling of about 528 megabytes. It is therefore important to be able to satisfactorily address such drive capacities.

This disclosure involves scaling the addressing of digital data written to or read from a DASD to accommodate the storage capacity of the DASD beyond the limit imposed by interrupt 13 of approximately 528 megabytes.

The invention disclosed herein allows the CHS addressing capability to be satisfactorily extended to address DASD beyond the approximately 528 megabyte capacity limited by the interrupt 13 design by using a control program running on the microprocessor and the DASD, The latter is used to inquire about the number of existing cylinders from the DASD; determine whether the number of cylinders exceeds 1024, and when it exceeds, repeatedly divide the number of existing cylinders by 2 until the quotient is less than 1024, and record the number of repetitions at the same time Divide by 2 times; then establish the first base frame of cylinder-head-sector data, which can have up to 1024 cylinders and 256 heads; establish cylinder-head-sector data The second reference page frame, the number of cylinders that the latter can have can be greater than 1024, and the number of heads can be as much as the same as the number of existing heads of DASD; and the storage address digital data exchanged between the first and second reference negative frames are performed scaling; to exchange data within the full storage capacity of said DASD. The scaling operation is done by repeatedly dividing the existing cylinder number by 2.

The present invention provides a kind of computer system, it is characterized in that comprising:

A rotating media direct access storage device (DASD) for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each of said cylinders being divided into a third predetermined number of sectors, and said head exchanges digital data with said sectors of said cylinder,

The DASD has an address of digital data therein determined using cylinder-head-sector storage address data,

said cylinders and said heads and said sectors together define a storage capacity of said device which exceeds 528,482,304 bytes of digital data,

a microprocessor for processing digital data, said microprocessor controlling digital data exchange with said DASD using cylinder-head-sector storage address data, and

a control program accessible by said microprocessor for controlling the flow of digital data into and out of said DASD,

The microprocessor accesses the control program and loads the control program, and runs under the control of the control program,

The control program is further configured as

querying the DASD for the first predetermined number of cylinders,

determining that the first predetermined number of cylinders exceeds 1024,

Repeatedly divide the first predetermined number by 2 until the quotient is less than 1024, and simultaneously register the number of times N of repeated division,

establishing a first datum frame for cylinder-head-sector data, said first datum frame having a range of up to 1024 cylinders and a range of up to 256 head counts,

establishing a second reference frame for cylinder-head-sector data, said second reference frame having an extent greater than 1024 cylinders and an extent up to said second predetermined number of heads, and,

converting the storage address digital data exchanged between the first and second reference frame so that the data exchange can be performed within the total storage capacity of the DASD, the conversion is performed using a number N of times, the The number of times is the number of repetitions of dividing the first predetermined value by 2,

where the number of cylinders obtained from the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads to obtain the number of cylinders and heads of the second reference frame number;

The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame.

A method of operating a computer system having:

a rotating media direct access storage device DASD for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each cylinder being divided into a third predetermined number of sectors, The magnetic head and the sector of the cylinder exchange digital data, and the DASD has a digital data address determined by using the cylinder-head-sector CHS data. The cylinder, the magnetic head and the sector together determine the storage capacity of the DASD. The storage capacity exceeds 528,482,304 bytes of numeric data,

A microprocessor for processing digital data, the microprocessor uses cylinder-head-sector storage address data to control digital data exchange with DASD, and

A control program accessible by the microprocessor to control the flow of digital data to and from the DASD,

The method is characterized in comprising the following steps:

access control program through the microprocessor,

Load the control program, and perform the following operations under the control of the control program:

Query DASD for the first predetermined number of cylinders,

determining that the first predetermined number of cylinders exceeds 1024,

Repeatedly dividing the first predetermined number by 2 until the quotient is less than 1024, and simultaneously registering the number of times N of this division,

establishing a first reference frame for the CHS data, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads,

establishing a second reference frame for the CHS data, the second reference frame having a range greater than 1024 cylinders and a range up to a second predetermined number of heads, and

Scaling the CHS storage address digital data exchanged between the first and second reference page frames so as to exchange data within the total storage capacity of the DASD, said scaling step using the number N of repetitions of the first predetermined number divided by 2 to complete.

Part of the purpose of the present invention has been described, when further explaining below in conjunction with accompanying drawing, other purposes also will show, in the accompanying drawing:

Figure 1 is a perspective view of a personal computer embodying the present invention;

2 is an exploded perspective view of some components of the personal computer in FIG. 1, including a chassis, a casing, a direct access storage device (DASD) and a panel, to explain the relationship between these components;

Figure 3 is a schematic diagram of certain components of the personal computer of Figures 1 and 2;

Figure 4 is a schematic diagram of another arrangement of components of the personal computer of Figures 1 and 2 to explain another organization of these components;

Fig. 5 is a flowchart of certain operational steps of the present invention in practice using the personal computer of Figs. 1 to 4;

FIG. 6 is a flowchart of certain other operational steps of the present invention in practice using the personal computer of FIGS. 1 to 4; and

FIG. 7 is a flowchart of additional operational steps of the present invention in practice using the personal computer of FIGS. 1-4.

Accompanying drawing has shown the preferred embodiment of the present invention, will explain the present invention more fully below in conjunction with accompanying drawing, should understand at the beginning of carrying out the following explanation; People familiar with technology in relevant field can revise the present invention explained and The advantageous results of the invention are still obtained. Accordingly, the following explanations should be understood as a broad guiding disclosure for those skilled in the relevant art, rather than as a limitation of the present invention.

Referring now more particularly to the drawings, a personal computer system embodying the present invention is shown and generally designated 10 in FIG. As mentioned above, the computer 10 may have a display 12, a keyboard 12 and a printer or plotter 14 connected thereto. The computer 10 has a housing 15 (FIG. 2) consisting of a decorative outer surface 16 and an inner shield 18 which, together with the housing 19, forms an enclosed shielded space for housing data processing and Storage unit for processing and storing digital data. At least some of these components are mounted on a multi-layer planar board or motherboard 20, which is mounted on the chassis 19 and is used to electrically interconnect the components of the computer 10, except for In addition to the aforementioned, there are other connected components such as floppy disk drives, various forms of direct access storage devices, auxiliary boards or cards, and the like.

The chassis 19 has a base plate 22, a front panel 24, and a rear panel 25 (FIG. 2). Panel 24 provides at least one socket (four sockets in the illustrated example) for accommodating a data storage device, such as a magnetic or optical disk drive, backup tape drive, or the like. In the illustrated example, a pair of upper sockets 26, 28 and lower sockets 29, 30 are provided. One of the upper bays 26 is used to accommodate a first size external device drive (such as a known 3.5 inch drive), while the other upper bay 28 is used to accommodate a drive of a selected one of two sizes (such as a 3.5 and a 5.25 inch drive). ), while the two lower seats are designed to accommodate only one size drive (3.5 inches). A fixed disk DASD is indicated at 90 in FIG. 1 and is known to receive, store and transmit data.

Before applying the above structure to the present invention, it is instructive to review the general operation of personal computer system 10. Referring to FIG. 3, this is a block diagram of a first type of personal computer system for explaining the different components of a computer system such as system 10 according to the present invention, including components mounted on a flat panel 20 and the connection between the panel and the personal computer system. Connections between I/O slots and other hardware. The system processor 32 connected to the flat board includes a microprocessor, and the latter is connected to the memory control unit 36 by the high-speed CPU local bus 34 through the bus control timing unit 35, and the control unit 36 is connected to the volatile random access memory. Access memory (RAM) 38. Any suitable microprocessor may be used, one suitable microprocessor being the 80386 sold by INTEL.

Although the present invention will be explained below in conjunction with the system block diagrams of FIGS. 3 and 4 , it should be understood at the beginning of the following explanation that the apparatus and method according to the present invention are intended to be used in other hardware configurations of flat panels. For example, the system processor can be an Intel 80286 or 80486 microprocessor.

Referring now to FIG. 3 , CPU local bus 34 (including data, address and control lines) is used to connect microprocessor 32 , math coprocessor 39 , cache controller 40 , and cache memory 41 . Also connected to the CPU local bus is a cache memory 42 . Cache 42 is itself connected to a lower speed (compared to the CPU local bus) system bus 44, which also includes address, data and control lines. The system bus 44 is connected to the cache 42 and also to the caches 51,68. System bus 44 is also connected to bus control timing unit 35 and DMA unit 48 . The DMA unit 48 includes a central arbitration unit 49 and a DMA controller 50 . Cache 51 provides an interface between system bus 44 and an optional bus such as ISA bus 52 . Connected to the bus 52 are a plurality of I/O slots 54 for accommodating ISA adapter boards which may further connect to I/O devices or memory.

Arbitration control bus 55 connects DMA controller 50 and central arbitration unit 49 to I/O slot 54 and floppy disk adapter 56 . Also connected to system bus 44 is memory control unit 36 which consists of memory controller 59 , address demultiplexer 60 , and data cache 61 . The memory control unit 36 is further connected to a random access memory represented by a RAM card 38 . Memory controller 36 includes logic for mapping addresses to and from microprocessor 32 into specific areas of RAM 38 . The storage controller 36 also generates a ROM selection read signal (ROMSEL) for enabling or disabling the ROM 64 to work. Although the microprocessor system is shown with a basic one megabyte RAM card, it should be understood that optional memory cards 65-67 can be used to connect additional memory as shown in FIG.

The latch buffer 68 is used to connect the system bus 44 and the plane I/O bus 69 . Planar I/O bus 69 includes address, data, and control lines, respectively. Connected next to planar I/O bus 69 is a set of various I/O adapters and other components, such as display adapter 70 (for driving display 11), CMOS clock 72, non-volatile CMOS memory here referred to as NVRAM RAM 74, RS232 adapter 76, parallel adapter 78, numerous timers 80, floppy disk adapter 56, interrupt controller 84, and read-only memory 64, the stored BIOS control program in the read-only memory 64 is used in the I/O device and An interface is provided between the operating systems of the microprocessor 32 . The BIOS stored in the ROM64 can be copied into the RAM38 to reduce the execution time of the BIOS. ROM 64 is further responsive to memory controller 36 (via the ROMSEL signal). If memory controller 36 enables ROM 64 to function, the BIOS is executed from ROM. If the memory controller 36 disables the ROM 64, the ROM does not respond to address queries from the microprocessor 32 (ie, executes the BIOS from RAM).

Clock 72 is used to calculate date and time, while NVRAM is used to store system configuration data. That is, NVRAM contains values that describe the current configuration of the system. For example, NVRAM contains information describing the capacity of fixed or floppy disks, the type of display, the amount of memory, time, date, and so on. It is particularly important that NVRAM contains one item of data (possibly only one bit), which is used by storage controller 36 to determine whether to run BIOS from ROM or RAM, and to determine whether RAM needs to be re-applied as BIOSRAM. Also, when specific configuration programs such as SET Configuration are executed, these data are stored in NVRAM. The purpose of the SET Configura-tion program is to store values that reflect system configuration characteristics into NVRAM.

As mentioned above, the computer has a housing designated 15 which together with housing 19 forms an enclosed, shielded space for housing the above mentioned microcomputer components. The casing is made up of a single compression-molded part made of plastic synthetic material, i.e. an outer decorative cover 16 and a thin metal lining 18 of the same shape as the decorative cover. However, the enclosure can also be produced by other known methods, and the application of the invention is not limited to the described enclosure cover.

Another arrangement of an ISA personal computer is shown in FIG. 4, which shows a personal computer system block diagram of the various components of another arrangement of a computer system, such as system 10, in accordance with the present invention. Components shown in FIG. 4 which are similar in function to components in FIG. 3 described above are also given the same reference numerals with the addition of 100. For example, the functions of microprocessor 132 shown in FIG. 4 and microprocessor 32 shown in FIG. 3 are substantially similar. CPU 132 is connected via high-speed CPU local bus 134 to bus interface control unit 135, to volatile random access memory (RAM) 138, denoted as a single in-line memory card (SIMMS), and to basic input stored in CPU 132. BIOS ROM164 for instructions of /output operation. BIOS ROM 164 includes the BIOS used as an interface between the I/O devices and the operating system of microprocessor 132. Instructions stored in ROM164 can be copied to RAM138 to reduce BIOS execution time.

CPU local bus 134 (including data, address and control lines) is also used to connect microprocessor 132 with math coprocessor 139 and DASD controller 185 . Those familiar with computer design and operation know that the DASD controller can be connected to read only memory (ROM) 186, RAM 188, and various types of external devices as appropriate for the I/O connections shown on the right side of the figure.

Bus interface controller (BIC) 135 connects CPU local bus 134 to I/O bus 152 . BIC 135 utilizes bus 152 to connect to an optional feature bus, such as an ISA bus with a number of I/O slots that can accommodate adapter cards 190, which in turn can connect to I/O devices or memory (not shown). I/O bus 152 includes address, data and control lines.

Next to the I/O bus 152 are various I/O components, such as a video signal processor 191 connected to video RAM (VRAM), which can be used to store graphics information (designated at 192) and store image information (designated at 192). at 194). Video signals exchanged with processor 191 may be sent through digital-to-analog converter (DAC) 195 to a monitor or other display device. It is also possible to directly connect the VSP 191 to what is here called a natural image input/output, which may be in the form of a video recorder, video player, video camera, etc. I/O bus 152 is also connected to digital signal processor (DSP) 196, to which instruction RAM 198 and data RAM 199 are connected for storing software instructions for DSP 196 to process signals and for storing data used in such processing operations. DSP 196 also handles audio input and output through audio controller 200 and other signals through analog interface controller 201 . Finally, the I/O bus 152 is connected to an input/output controller 202 which is connected to an electrically erasable programmable read-only memory (EEPROM) 204 and exchanges input and output information with commonly used peripherals through the latter and serial ports, which Common peripherals include a floppy disk drive, printer or plotter 14, keyboard 12, mouse or pointing device.

Either of the two different schemes of personal computer organization explained heretofore may use DASDs with cylinder counts and head counts that are within interrupt 13 design expectations. That is, the number of cylinders may be 1024 or less, and the number of heads may be 256 or less. In this case, the normal operation of the personal computer system will not encounter difficulties. The result is to interrogate the characteristics of the DASD and store that part of the information as part of the system configuration. The operation of the system under normal use is the prior art well known. While DASDs in fact have 16 heads (usually ATA DASDs), the result limits the amount of DASD memory available for CHS addressing to 528,482,304 bytes of digital data.

An important salient feature of the present invention is that CHS addressing within the expected value range of the interrupt 13 design can be used to address ATA DASDs with a cylinder count exceeding 1024, a head count of 16, and a storage capacity of digital data Numeric data exceeding 528,482,304 bytes. According to the present invention, this is accomplished by scaling between reference frame frames used for CHS addressing.

According to the present invention, a first reference frame for CHS addressing is established with a cylinder count exceeding 1024 and a head count corresponding to the actual head count in the drive being used and addressed. As previously stated, this number is typically 16 heads for the common type of drive encountered in implementing the present invention in an actual operating personal computer system. However, the number of heads may be other than 16 but any predetermined value chosen by the DASD designer. The first reference frame corresponds to the actual characteristics of the DASD used.

A second base frame for CHS addressing is also established, with the number of cylinders and heads conforming to the interrupt 13 design convention. That is, the number of cylinders of the second reference frame is not greater than 1024, and the number of heads is not greater than 256.

The present invention contemplates scaling CHS-addressed data exchanged between two reference page frames to exchange data within the full storage capacity of the DASD used. This conversion is accomplished by establishing a specific relationship between the addressing of the first reference frame and the addressing of the second reference frame.

The following discussion will deal with methods of establishing two reference frames and performing conversions between them. However, as a prerequisite, note that setup and scaling are available for every type of DASD control encountered. More specifically, the invention to be described is applicable to DASDs controlled by a controller card installed in the I/O bus socket; to IDE type DAS-Ds; and to Addressable DASD. Note that in each example there is a microprocessor running with CHS addressing. In the case of a combination DASD/controller card, the addressing microprocessor is typically placed on the card. For IDE DASD, the addressing microprocessor is generally integrated with DASD. For DASDs directly controlled by the system CPU, the microprocessor used is the system CPU. In addition, in each case there is a control program stored in a location accessible by the microprocessor and loaded into the microprocessor, the control program and the microprocessor cooperate to perform addressing operations. This control program may generally be referred to herein as a basic input/output system, or BIOS, or the control program may be part of such a system. The BIOS of the personal computer system may comprise the main BIOS referred to in the above discussion of the system configuration explained in FIGS. Or the device BIOS, such as may be stored as part of the IDE DASD; or part of the main BIOS as previously described. The present invention contemplates that the control program to be mentioned below may be any of these different types.

In either of these examples, the system used in the present invention has a rotating media direct access storage device (DASD) 90 for receiving, storing and transmitting digital data. DASD has a first predetermined number of cylinders and a second predetermined number of heads, and each cylinder is divided into a third predetermined number of sectors. It will be seen that the head exchanges digital data with, writes to or reads data from, the sectors of the cylinder according to the CHS addressing signal. According to the present invention, cylinders, heads, and sectors together determine the storage capacity of a DASD in excess of 528,482,304 bytes of digital data.

As noted in the above discussion, the system has a microprocessor for processing digital data and for controlling the exchange of cylinder-head-sector memory address data with DASD digital data. The system also has a control program accessible to the microprocessor for controlling the flow of digital data to and from the DASD. In operation, the microprocessor accesses the control program, loads the control program, and completes a series of operations under the control of said control program, allowing data to be exchanged within the full storage capacity of the DASD.

The completed operation includes establishing the first and second reference frames mentioned above, and then performing conversion between them. Before establishing the reference frame, the system follows the steps shown in FIG. 5 to determine the conversion factor to be used. These steps include interrogating the number of cylinders available in the DASD and then determining if the number of cylinders is greater than 16,384. The numbers that follow are the maximum values that can be addressed in a particular embodiment described herein, and may vary if the embodiment differs in detail from that described herein. If the number is larger, the number 16,384 is used in the following steps. If not, the number queried is available. The next step is to set the registers used to hold the conversion coefficients to a value of zero. It is then determined whether the number of cylinders is greater than 1024, which is the upper limit suggested by the interrupt 13 design described above. If the number of cylinders is equal to or less than 1024, the conversion factor register retains its zero count value and no conversion is required. If greater than 1024, divide the number of cylinders by 2. The best way to do division is to use a "shift right" instruction. After the division operation, the count value of the conversion coefficient register is increased by 1. The process returns to ask the number of cylinders, which is now the quotient of the previous division operation. If it is still greater than 1024, then divide the quotient of the number of cylinders by 2, add 1 to the registered conversion factor, and repeat like this Process of division/increment until the quotient of the number of cylinders is less than 1024. Now, because the quotient is less than 1024, the count value stored in the register is the conversion coefficient (also marked with "N" here) to be used later. Conversion coefficients may also be stored as part of the system configuration data held in NVRAM, as appropriate.

Once the conversion factor has been determined, the aforementioned base frame can be set. One such page frame may be set by an operation as described in FIG. 6 to obtain driver parameters for the DASD. As shown, cylinder and head counts can be obtained from DASD, or by querying from previously stored values. The conversion factor is then used to convert the number of cylinders by dividing the number of cylinders by the power of the conversion factor of 2, which is the divisor used in the process of determining the conversion factor described earlier. Another way to account for this conversion is to shift the number of cylinders to the right by this number of bits by the conversion factor. Expressed algorithmically,

After the conversion, the number of cylinders = the number of cylinders/2 ^N Then use the conversion factor to convert the number of heads, multiply the number of heads by the power of the conversion factor of 2 (or move the number of heads to the left by the number of bits of the conversion factor number). Expressed algorithmically,

The number of magnetic heads after conversion = the number of magnetic heads × 2 ^N The conversion operation has been completed here, and the converted number of cylinders and magnetic heads will be sent back for CHS addressing of DASD.

It should be noted that the number of cylinders in DASD is an integer and cannot be a fraction. Fractional cylinders resulting from conversion shall be discarded. That is, a drive with 2001 cylinders and 16 heads would be considered to have 1000 cylinders and 32 heads. Half of the BIOS cylinder is "lost". If such a DASD addresses cylinder 0 head 20 through the BIOS using constraints designed by interrupt 13, the actual DASD will access cylinder 1 head 4.

As a working example, it is assumed that a system is equipped with a DASD having 2000 cylinders and 16 heads whose total storage capacity is 1,032,192,000 bytes of digital data (2000×16×63×512). At this time, the conversion factor is 1 (2000 is divided by 2 once, and the quotient is 1000, which is less than 1024).

The second reference frame is established by the DASD itself and has a range beyond 1024 cylinders and up to a predetermined number of heads, which is the number of heads the actual drive is equipped with. In the above example (and as with most ATA DASDs), that number is 16.

The conversion between the two reference frames is done as explained in Figure 7, by the control program working with the microprocessor as described above. More specifically, in order to exchange data within the total storage capacity of the DASD, the storage address digital data exchanged between the first and second reference frame should be converted, the conversion is the number of uses (N), also That is, use 2 to repeatedly divide the number of cylinders to complete. When performing this conversion, the stored data must first be queried to determine whether the stored conversion factor is not equal to zero. If it is zero, no conversion is required and CHS addressing operations can proceed as originally intended by the interrupt 13 design. If it is greater than zero, the number of cylinders in the drive command is multiplied by the conversion factor N of 2 to the power of this many. The algorithm is expressed as follows:

Number of cylinders after conversion = number of cylinders after conversion × 2 ^N The number of heads after conversion is then divided by the actual number of heads in DASD, and the remainder of this division is considered as the number of heads after conversion. The quotient of this division is logically ORed with the scaled cylinder number, and the result is considered to be the addressed cylinder number.

As pointed out above, the determination, conversion and conversion of the conversion coefficient can be the common function of the system BIOS and the system CPU; it can be the common function of the controller card BIOS and the controller microprocessor; it can also be the IDE BIOS and the IDE microprocessor common functions. In all cases, the effect of the conversion is the same: CHS addresses in the first base frame that comply with the constraints designed by Interrupt 13 in ISABIOS are converted to CHS addresses in the second base frame that satisfy the actual DASD characterization requirements, while The actual feature requirements of DASD are beyond the constraints of the interrupt 13 design in the ISA BIOS.

The preferred embodiments of this invention have been set forth in the drawings and description of technical performance, and although specific terms have been used, the description given has used terms in terms of attributes and description only and not for purposes of limitation.

Claims (51)

1. A computer system, characterized in that it comprises: A rotating media direct access storage device (DASD) for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each of said cylinders being divided into a third predetermined number of sectors, and said head exchanges digital data with said sectors of said cylinder, The DASD has an address of digital data therein determined using cylinder-head-sector storage address data, said cylinders and said heads and said sectors together define a storage capacity of said device which exceeds 528,482,304 bytes of digital data, a microprocessor for processing digital data, said microprocessor controlling digital data exchange with said DASD using cylinder-head-sector storage address data, and a control program accessible by said microprocessor for controlling the flow of digital data into and out of said DASD, The microprocessor accesses the control program and loads the control program, and runs under the control of the control program, The control program is further configured as querying the DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, Repeatedly divide the first predetermined number by 2 until the quotient is less than 1024, and simultaneously register the number of times N of repeated division, establishing a first datum frame for cylinder-head-sector data, said first datum frame having a range of up to 1024 cylinders and a range of up to 256 head counts, establishing a second reference frame for cylinder-head-sector data, said second reference frame having a range greater than 1024 cylinders and a range up to said second predetermined number of heads and, converting the storage address digital data exchanged between the first and second reference frame so that the data exchange can be performed within the total storage capacity of the DASD, the conversion is performed using a number N of times, the The number of times is the number of repetitions of dividing the first predetermined value by 2, where the number of cylinders obtained from the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads to obtain the number of cylinders and heads of the second reference frame number; The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame. 2. The computer system according to claim 1, characterized in that it comprises a memory unit for receiving and storing said control program, said memory unit being operatively connected to said microprocessor for said microprocessor to access said the control program. 3. The computer system of claim 2, wherein said storage unit comprises a read-only memory device. 4. The computer system according to claim 2, wherein said storage unit comprises a non-volatile random access memory device and said computer system comprises a power supply operatively associated with said non-volatile random access memory device. The access storage device is connected to activate said non-volatile random access storage device and maintain said control program stored therein. 5. The computer system of claim 1, wherein said DASD is an integrated driver electronics DASD and said microprocessor and said control program are integral with said DASD. 6. The computer system according to claim 1, characterized in that comprising a motherboard for supporting and connecting electrical components of said computer system, characterized in that said microprocessor is mounted on said motherboard and said control Programs are on the motherboard for access by the microprocessor. 7. The computer system according to claim 6, wherein said microprocessor is a system processor of said computer system, and said computer system includes a basic input/output system BIOS program, and said control program includes within the BIOS program. 8. The computer system according to claim 6, characterized in that comprising a storage unit for receiving and storing said control program, said storage unit being installed on said DASD controller card, and operating with said micro The processor is connected for the microprocessor to access the control program. 9. The computer system of claim 8, wherein said storage unit comprises a read-only memory device. 10. The computer system according to claim 8, wherein said storage unit comprises a non-volatile random access memory device, and said computer system comprises a power supply operatively associated with said non-volatile A random access memory device is connected for energizing said non-volatile random access memory device and maintaining said control program stored therein. 11. A computer system, characterized in that it comprises: An integrated drive electronics rotary media direct access storage device IDE DASD for receiving, storing and transmitting digital data having a first predetermined number of cylinders and a second predetermined number of heads each The cylinder is divided into a third predetermined number of sectors and the head exchanges digital data with the sectors of the cylinder. The IDE DASD has an address of digital data therein determined by cylinder-head-sector storage address data, said cylinders and said heads and said sectors together determine the storage capacity of said device exceeding 528,482,304 bytes of digital data, A microprocessor for processing digital data, the microprocessor and the IDE DASD form an integral body, and utilize cylinder-head-sector storage address data to control the exchange of digital data with the IDE DASD, and a control program integrated with said ID DASD, said control program being accessible by said microprocessor for controlling the flow of digital data into said DASD and out of said IDE DASD, The microprocessor accesses the control program, loads the control program, and runs it under the control of the control program, The control program is further configured to: querying the DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, Repeatedly divide the first predetermined number by 2 until the quotient is less than 1024, and simultaneously store the repetition number N of this division, establishing a first reference frame for cylinder-head-sector data, the first reference frame having a range of up to 1024 cylinders and a range of up to 256 head counts, establishing a second reference frame for cylinder-head-sector data, said second reference frame having a range greater than 1024 cylinder counts and a range up to said second predetermined head count, and converting the storage address digital data exchanged between said first and second reference frame to exchange data within the total storage capacity of said DASD by repeatedly dividing said first predetermined number by 2 times N to complete, Wherein the number of cylinders obtained by the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads, thereby obtaining the number of cylinders and the number of heads of the second reference frame, The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame. 12. The computer system according to claim 11, characterized in that it comprises a storage unit for receiving and storing said control program, said storage unit is integral with said IDEDASD, and operates with said microprocessor connected for the microprocessor to access the control program. 13. The computer system of claim 12, wherein said storage unit comprises a read-only memory device. 14. The computer system according to claim 12, wherein said storage unit comprises a non-volatile random access memory device, and said computer system comprises a power supply operatively associated with said non-volatile A random access memory device is connected for energizing said non-volatile random access memory device and maintaining said control program stored therein. 15. A computer system, characterized in that it comprises: a motherboard for supporting and connecting the electrical components of said computer system, an input/output channel defined in said motherboard and comprising a channel socket, A rotating media direct access storage device DASD for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each of said cylinders being divided into third predetermined the number of sectors to enable said head to exchange digital data with said sector of said cylinder, The DASD has a digital data address therein determined using cylinder-head-sector storage address data, said cylinders together with said heads and said sectors determine the storage capacity of said device, said storage capacity exceeding 528,482,304 bytes of digital data, a DASD controller card installed in said channel socket, a microprocessor for processing digital data, said microprocessor is installed on said DASD controller card, and uses cylinder-head-sector storage address data to control digital data exchange with said DASD, a control program residing on said controller card and accessible by said microprocessor for controlling the flow of digital data into and out of said DASD, The microprocessor accesses the control program and loads the control program, and runs under the control of the control program, The control program is further configured to: querying the DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, The first predetermined number is repeatedly divided by 2 until the quotient is less than 1024, and the number N of repeating this division is registered simultaneously, establishing a first reference frame for cylinder-head-sector data, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference frame for cylinder-head-sector data, said second reference frame having an extent greater than 1024 cylinders and an extent up to said second predetermined head data, and converting the storage address digital data exchanged between said first and second reference frame to exchange data within the total storage capacity of said DASD by repeatedly dividing said first predetermined number by 2 times N to complete, where the number of cylinders obtained from the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads to obtain the number of cylinders and heads of the second reference frame number, The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame. 16. The computer system according to claim 15, characterized in that comprising a storage unit for receiving and storing said control program, said storage unit being mounted on said DASD controller card and operating with said micro The processor is connected for the microprocessor to access the control program. 17. The computer system of claim 16, wherein said storage unit comprises a read-only memory device. 18. The computer system according to claim 16, wherein said storage unit comprises a non-volatile random access memory device, and said computer system comprises a power supply operatively associated with said non-volatile A random access memory device is connected for energizing said non-volatile random access memory device and maintaining said control program stored therein. 19. A computer system, characterized in that it comprises: a motherboard for supporting and connecting the electrical components of said computer system, A rotating media direct access storage device DASD for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each of said cylinders being divided into a third predetermined number sector and said head exchanges digital data with said sector of said cylinder, The DASD has a digital data address therein determined using cylinder-head-sector storage address data, said cylinders and said heads and said sectors together determine the storage capacity of said device, said storage capacity exceeding 528,482,304 bytes of digital data, a microprocessor for processing digital data, said microprocessor is installed on said motherboard, and uses cylinder-head-sector storage address data to control digital data transformation with said DASD, a control program residing on said motherboard and accessible by said microprocessor for controlling the flow of digital data into and out of said DASD, The microprocessor accesses the control program and loads the control program, and runs under the control of the control program, The control program is further configured to: querying the DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, The first predetermined number is repeatedly divided by 2 until the quotient is less than 1024, and the number of times for repeating this division is registered at the same time, establishing a first reference frame for cylinder-head-sector data, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a master second reference frame for cylinder-head-sector data, said second reference frame having a range greater than 1024 cylinders and a range up to said second predetermined number of heads, and converting the storage address digital data exchanged between said first and second reference frame to exchange data within the total storage capacity of said DASD by repeatedly dividing said first predetermined number by 2 times N to complete, where the number of cylinders obtained from the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads to obtain the number of cylinders and heads of the second reference frame number, The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame. 20. The computer system according to claim 19, characterized in that comprising a storage unit for receiving and storing said control program, said storage unit being mounted on said DASD controller card and operating with said micro The processor is connected for the microprocessor to access the control program. 21. The computer system of claim 20, wherein said storage unit comprises a read-only memory device. 22. The computer system according to claim 20, wherein said storage unit comprises a non-volatile random access memory device, and said computer system comprises a power supply operatively associated with said non-volatile A random access storage device is connected for energizing said non-volatile random access storage device and maintaining said control program stored therein. 23. The computer system according to claim 20, wherein said microprocessor is a system processor of said computer system, said computer system further comprising a basic input/output system BIOS program, and said control program is included in said In the BIOS program described above. 24. A personal computer system having a high speed system processor compatible with application software and operating system software designed to execute on a lower speed system processor, said personal computer system comprising: a high-speed microprocessor for processing digital data, said microprocessor having real address and protected modes of operation, electrically connected to the high-speed data bus; Non-volatile memory electrically connected to a lower speed data bus; A bus controller for providing communication between a high-speed data bus and a lower-speed data bus; Volatile memory electrically connected to a high-speed data bus; A storage controller electrically connected to the volatile memory and the nonvolatile memory, the storage controller controlling the volatile memory, the nonvolatile memory and the high-speed microprocessor Control the communication between devices; A rotating media direct access storage device DASD for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each of said cylinders being divided into a third predetermined number of sectors zone and said head exchanges digital data with said sector of said cylinder, The DASD has a digital data address therein determined using cylinder-head-sector storage address data, said cylinders together with said heads and said sectors determine the storage capacity of said device, said storage capacity exceeding 528,482,304 bytes of digital data, said microprocessor controls digital data exchange with said DASD using cylinder-head-sector memory address data, and a control program accessible by said microprocessor for controlling the flow of digital data into and out of said DASD, The microprocessor accesses the control program and loads the control program, and runs under the control of the control program, The control program is further configured to: querying the DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, The first predetermined number is repeatedly divided by 2 until the quotient is less than 1024, and the number N of repeating this division is registered simultaneously, establishing a first reference frame for cylinder-head-sector data, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference frame for cylinder-head-sector data, said second reference frame having a range greater than 1024 cylinders and a range up to said second predetermined number of heads, and converting the storage address digital data exchanged between the first and second reference page frames so as to exchange data within the total storage capacity of the DASD, the conversion is by repeatedly dividing the first predetermined number by 2 times to complete, where the number of cylinders obtained from the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads to obtain the number of cylinders and heads of the second reference frame number, The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame. 25. The computer system according to claim 24, wherein said control program is stored in said non-volatile memory. 26. The computer system of claim 25, wherein said non-volatile memory comprises a read-only memory device. 27. The computer system according to claim 25, wherein said non-volatile memory comprises a non-volatile random access storage device, and said computer system comprises a power supply operatively associated with said The non-volatile random access memory device is connected for energizing the non-volatile random access memory device and maintaining said control program stored therein. 28. A personal computer system having a high speed system processor - compatible with application software and operating system software designed to execute on a lower speed system processor, said personal computer system comprising: a high-speed microprocessor for processing digital data, said microprocessor having real address and protected modes of operation, electrically connected to the high-speed data bus; Non-volatile memory electrically connected to a lower speed data bus; A bus controller for providing communication between a high-speed data bus and a lower-speed data bus; Volatile memory electrically connected to a high-speed data bus; A storage controller electrically connected to the volatile memory and the nonvolatile memory, the storage controller controlling the volatile memory, the nonvolatile memory and the high-speed microprocessor Control the communication between devices; Rotating media direct access storage device IDE DASD with integrated drive electronics for receiving, storing and transmitting digital data, said IDE DASD having a first predetermined number of cylinders and a second predetermined number of heads, each of said cylinders having a sector divided into a third predetermined number and said head exchanging digital data with said sector of said cylinder, The IDE DASD has a digital data address determined by using the cylinder-head-sector storage address data, said cylinders together with said heads and said sectors determine the storage capacity of said device, said storage capacity exceeding 528,482,304 bytes of digital data, A second microprocessor for processing digital data, the second microprocessor and the IDE DASD are combined as a whole, and use the cylinder-head-sector storage address data to control the digital data with the IDE DASD data exchange, and a control program integral with said IDE DASD and accessible by said second microprocessor for controlling the flow of digital data into and out of said IDE DASD, the second microprocessor accesses the control program and loads the control program, and runs under the control of the control program, The control program is further configured to: querying the DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, The first predetermined number is repeatedly divided by 2 until the quotient is less than 1024, and the number N of repeating this division is registered simultaneously, establishing a first reference frame for cylinder-head-sector data, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference frame for cylinder-head-sector data, said second reference frame having a range greater than 1024 cylinders and a range up to said second predetermined number of heads, and Scaling the storage address digital data between said first and second reference frame to exchange data within the total storage capacity of said DASD by repeatedly dividing said first predetermined number by 2 The number of times N to complete, where the number of cylinders obtained from the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads to obtain the number of cylinders and heads of the second reference frame number, The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame. 29. The computer system according to claim 28, characterized in that it comprises a storage unit for receiving and storing said control program, said storage unit and said IDEDASD are combined as a whole, and operate with said second The microprocessor is connected to allow the second microprocessor to access the control program. 30. The computer system of claim 29, wherein said storage unit comprises a read-only memory device. 31. The computer system according to claim 29, wherein said storage unit comprises a non-volatile random access memory device, and said computer system comprises a power supply operatively associated with said non-volatile The random access memory device is connected for energizing said non-volatile random access memory device and maintaining said control program stored therein. 32. A personal computer system having a high speed system processor compatible with application software and operating system software designed to execute on a lower speed system processor, said personal computer system comprising: a motherboard for supporting and connecting the electrical components of said computer system, a high-speed microprocessor mounted on said motherboard for processing digital data, said microprocessor having real address and protected modes of operation, and electrically connected to a high-speed data bus; Non-volatile memory electrically connected to a lower speed data bus, an input/output channel defined in said motherboard comprising a channel socket electrically connected to a lower speed data bus, a bus controller for providing communication between a high-speed data bus and a lower-speed data bus, a volatile memory electrically connected to a high-speed data bus; A memory controller electrically connected to the volatile memory and the nonvolatile memory, the memory controller controlling the volatile memory and the nonvolatile memory and the high-speed microprocessor control the communication between A rotating media direct access storage device DASD for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each of said cylinders being divided into a third predetermined number of sectors zone and said head exchanges digital data with said sector of said cylinder, The DASD has a digital data address therein determined using cylinder-head-sector storage address data, said cylinders together with said heads and said sectors determine the storage capacity of said device, said storage capacity exceeding 528,482,304 bytes of digital data; a DASD controller card installed in said channel socket; A second microprocessor for processing digital data, the second microprocessor is installed on the DASD controller card, and exchanges digital data with the DASD using cylinder-head-sector storage address data to control, and a control program residing on a controller card and accessible by said microprocessor for controlling the flow of digital data into and out of said DASD, the second microprocessor accesses the control program and loads the control program and operates under the control of the control program, The control program is further configured to: querying the DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, The first predetermined number is repeatedly divided by 2 until the quotient is less than 1024, and the number N of repeating this division is registered simultaneously, establishing a first reference frame for cylinder-head-sector data, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference frame for cylinder-head-sector data, said second reference frame having a range greater than 1024 cylinders and a range up to said second predetermined number of heads, and converting the stored address digital data exchanged between said first and second reference frame to exchange data within the total storage capacity of said DASD, said converting by repeatedly dividing said first predetermined number Completed with 2 times N, where the number of cylinders obtained from the first reference frame is multiplied by 2 ^N , and the number of heads obtained from the first reference frame is divided by the second predetermined number of heads to obtain the number of cylinders and heads of the second reference frame number, The number of cylinders obtained from the second reference frame is divided by 2 ^N , and the number of heads obtained from the second reference frame is multiplied by 2 ^N , thereby obtaining the number of cylinders and the number of heads of the first reference frame. 33. The computer system according to claim 32, characterized in that it comprises a storage unit for receiving and storing said control program, said storage unit is installed on said DASD controller card, and operates with said micro The processor is connected for the microprocessor to access the control program. 34. The computer system of claim 33, wherein said storage unit comprises a read-only memory device. 35. The computer system according to claim 33, wherein said storage unit comprises a non-volatile random access memory device, and said computer system comprises a power supply operatively associated with said non-volatile A random access memory device is connected for energizing said non-volatile random access memory device and maintaining said control program stored therein. 36. A method of operating a computer system having: a rotating media direct access storage device DASD for receiving, storing and transmitting digital data, said DASD having a first predetermined number of cylinders and a second predetermined number of heads, each cylinder being divided into a third predetermined number of sectors, The magnetic head and the sector of the cylinder exchange digital data, and the DASD has a digital data address determined by using the cylinder-head-sector CHS data. The cylinder, the magnetic head and the sector together determine the storage capacity of the DASD. The storage capacity exceeds 528,482,304 bytes of numeric data, A microprocessor for processing digital data, the microprocessor uses cylinder-head-sector storage address data to control digital data exchange with DASD, and A control program accessible by the microprocessor to control the flow of digital data to and from the DASD, The method is characterized in comprising the following steps: access control program through the microprocessor, Load the control program, and perform the following operations under the control of the control program: Query DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, Repeatedly dividing the first predetermined number by 2 until the quotient is less than 1024, and simultaneously registering the number of times N of this division, establishing a first reference frame for the CHS data, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference frame for the CHS data, the second reference frame having a range greater than 1024 cylinders and a range up to a second predetermined number of heads, and Scaling the CHS storage address digital data exchanged between the first and second reference page frames so as to exchange data within the total storage capacity of the DASD, said scaling step using the number N of repetitions of the first predetermined number divided by 2 to complete. 37. The method according to claim 36, wherein the step of converting CHS storage address digital data comprises the following steps: multiplying the number of cylinders obtained from the first reference page frame by 2 ^N , and multiplying the number of cylinders obtained from the first reference page frame The number of magnetic heads is divided by 2 ^N , so as to obtain the number of cylinders and the number of magnetic heads of the second reference frame. 38. The method according to claim 36, wherein the step of converting CHS storage address digital data comprises the following steps: dividing the number of cylinders obtained from the second reference page frame by 2 ^N , and dividing the number of cylinders obtained from the second reference page frame The number of heads is multiplied by 2 ^N , so as to obtain the number of cylinders and the number of heads of the first reference page frame. 39. The method according to claim 36, wherein the step of converting CHS storage address digital data comprises the following steps: Respond to disk drive commands by querying the value of N; then Distinguish whether the value of N is equal to zero or greater than zero; then Respond when it is determined that N is equal to zero, and transmit the cylinder and head addresses without conversion; Respond as follows when N is determined to be greater than zero; Multiply the cylinder address by 2 ^N and dividing the head address by a second predetermined number and The remainder obtained after dividing the magnetic head address by the second predetermined number is stored as the converted magnetic head address, and then Perform logical OR operation on the quotient obtained after dividing the magnetic head address by the second predetermined number and the cylinder address, and store the result as the converted cylinder address; then Send the converted cylinder and head addresses to the past. 40. A method of operating a computer system having: A rotating media direct access storage device IDE DASD with integrated drive electronics for receiving, storing and transmitting digital data, the IDE DASD has a first predetermined number of cylinders and a second predetermined number of heads, each cylinder is divided into Three predetermined number of sectors, at the same time the head and the sector of the cylinder exchange digital data, IDE DASD has the address of the digital data determined by using the cylinder-head-sector CHS data, the cylinder and the head and the sector are determined together IDE DASD storage capacity that exceeds 528,482,304 bytes of digital data, A microprocessor combined with the electronic circuit of IDE DASD as a whole for processing digital data, which controls the exchange of digital data with IDE DASD using CHS data, and A control program accessible by the microprocessor to control the flow of digital data into and out of the IDE DASD, The method is characterized by comprising the following steps: access control program through the microprocessor, Load the control program, and perform the following operations under the control of the control program: Query DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, Repeatedly dividing the first predetermined number by 2 until the quotient is less than 1024, and simultaneously registering the number of times N of this division, Create a first reference frame for CHS data to be used outside of IDE DASD, the first reference frame has an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference frame for CHS data to be used within the IDE DASD, the second reference frame having a range greater than 1024 cylinders and a range up to a second predetermined number of heads, and Scaling the CHS storage address digital data exchanged between the first and second reference page frames to exchange data within the total storage capacity of the IDE DASD, said scaling step is performed by dividing the first predetermined number of repetitions by 2 N to complete. 41. The method according to claim 40, wherein the step of converting the CHS storage address digital data comprises the following steps: multiplying the number of cylinders obtained from the first reference page frame by 2 ^N , and multiplying the number of cylinders obtained from the first reference page frame The number of magnetic heads is divided by the second predetermined number of magnetic heads, so as to obtain the number of cylinders and the number of magnetic heads of the second reference frame. 42. The method according to claim 40, wherein the step of converting CHS storage address digital data comprises the following steps: multiplying the number of cylinders obtained from the second reference page frame by 2 ^N , and multiplying the number of cylinders obtained from the second reference page frame The number of heads is multiplied by 2 ^N , so as to obtain the number of cylinders and the number of heads of the first reference page frame. 43. The method according to claim 40, wherein the step of converting CHS storage address digital data comprises the following steps: Respond to disk drive commands by querying the value of N; then Distinguish whether the value of N is equal to zero or greater than zero; then Respond when it is determined that N is equal to zero, and transmit the cylinder and head addresses without conversion; Make the following responses when N is determined to be greater than zero: Multiply the cylinder address by 2 ^N , and dividing the head address by a second predetermined number and The remainder obtained after dividing the magnetic head address by the second predetermined number is stored as the converted magnetic head address; then Perform logical OR operation on the quotient obtained after dividing the magnetic head address by the second predetermined number and the cylinder address, and store the result as the converted cylinder address; then Send the converted cylinder and head addresses to the past. 44. A method of operating a computer system having: a rotating media direct access storage device DASD for receiving, storing and transmitting digital data, the DASD having a first predetermined number of cylinders and a second predetermined number of heads, each cylinder being divided into a third predetermined number of sectors, At the same time, the magnetic head and the sector of the cylinder exchange digital data, and the DASD has the digital data address determined by the cylinder-head-sector CHS data. The cylinder, the magnetic head and the sector together determine the storage capacity of the DASD. The storage container Over 528,482,304 bytes of numeric data, A motherboard for supporting and connecting the electrical components of a computer system that defines an input/output channel with channel sockets, The DASD controller card installed in the channel socket has a microprocessor for processing digital data, the microprocessor controls the exchange of digital data with DASD using CHS data, and is stored on the card accessible by the microprocessor The control program is used to control the flow of digital data into and out of the DASD, The method is characterized in comprising the following steps: access control program through the microprocessor, Load the control program, and perform the following operations under the control of the control program: Query DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, Repeatedly dividing the first predetermined number by 2 until the quotient is less than 1024, and simultaneously registering the number of times N of this division, establishing a first reference frame for CHS data to be used outside of the DASD controller card, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference page frame for CHS data to be used between the DASH controller card and the DASD, the second reference page frame having an extent greater than 1024 cylinders and an extent up to a second predetermined number of heads, and Scaling the CHS storage address digital data exchanged between the first and second reference page frames so as to exchange data within the total storage capacity of the DASD, said scaling step using the number N of repetitions of the first predetermined number divided by 2 to complete. 45. The method according to claim 44, wherein the step of converting CHS storage address digital data comprises the following steps: multiplying the number of cylinders obtained from the first reference page frame by 2 ^N , and multiplying the number of cylinders obtained from the first reference page frame The number of magnetic heads is divided by the second predetermined number of magnetic heads, so as to obtain the number of cylinders and the number of magnetic heads of the second reference frame. 46. The method according to claim 44, wherein the step of converting the CHS storage address digital data comprises the following steps: dividing the number of cylinders obtained from the second reference page frame by 2 ^N , and dividing the number of cylinders obtained from the second reference page frame The number of heads is multiplied by 2 ^N , so as to obtain the head number of the cylinder number of the first reference page frame. 47. The method according to claim 44, wherein the step of converting CHS storage address digital data comprises the following steps: Respond to disk drive commands by querying the value of N, then, Distinguish whether the value of N is equal to zero or greater than zero; then Respond when it is determined that N is equal to zero, and transmit the cylinder and head addresses without conversion; Response upon determining that N is greater than zero is as follows: Multiply the cylinder address by 2 ^N and dividing the head address by a second predetermined number and The remainder obtained after dividing the magnetic head address by the second predetermined number is stored as the converted magnetic head address; then Perform logical OR operation on the quotient obtained after dividing the magnetic head address by the second predetermined number and the cylinder address, and store the result as the converted cylinder address; then Send out the cylinder and head addresses thus converted. 48. A method of operating a computer system having: a rotating media direct access storage device DASD for receiving, storing and transmitting digital data, the DASD having a first predetermined number of cylinders, a second predetermined number of heads, each cylinder divided into a third predetermined number of sectors, At the same time, the magnetic head and the sector of the cylinder exchange digital data. DASD has a digital data address determined by using the cylinder-head-sector CHS data. The cylinder, the magnetic head and the sector together determine the storage capacity of the DASD. The storage capacity Over 528,482,304 bytes of numeric data, A motherboard for supporting and connecting the electrical components of a computer system, the motherboard has a system microprocessor for processing digital data, the microprocessor controls the exchange of digital data with DASD using CHS data, and there is a motherboard An on-board control program accessible by the microprocessor is used to control the flow of digital data into and out of the DASD, The method is characterized in comprising the following steps: access control program through the microprocessor, Load the control program, and perform the following operations under the control of the control program: Query DASD for the first predetermined number of cylinders, determining that the first predetermined number of cylinders exceeds 1024, Repeatedly dividing the first predetermined number by 2 until the quotient is less than 1024, and simultaneously registering the number of times N of this division, establishing a first reference frame for CHS data to be used outside of DASD, the first reference frame having an extent of up to 1024 cylinders and an extent of up to 256 heads, establishing a second reference frame for CHS data to be used within the DASD, the second reference frame having an extent greater than 1024 cylinders and an extent up to a second predetermined number of heads, and Scaling the CHS storage address digital data exchanged between the first and second reference page frames so as to exchange data within the total storage capacity of the DASD, said scaling step using the number N of repetitions of the first predetermined number divided by 2 to complete. 49. The method according to claim 48, wherein the step of converting the CHS storage address digital data comprises the following steps: multiplying the number of cylinders obtained from the first reference page frame by 2 ^N , and multiplying the number of cylinders obtained from the first reference page frame The number of magnetic heads is divided by the second predetermined number of magnetic heads, so as to obtain the number of cylinders and the number of magnetic heads of the second reference frame. 50. The method according to claim 48, wherein the step of converting CHS storage address digital data comprises the following steps: multiplying the number of cylinders obtained from the second reference page frame by 2 ^N , and multiplying the number of cylinders obtained from the first reference page frame The number of heads is multiplied by 2 ^N , so as to obtain the number of cylinders and the number of heads of the first reference page frame. 51. The method according to claim 48, wherein the step of converting CHS storage address digital data comprises the following steps: Respond to disk drive commands by querying the value of N; then Distinguish whether the value of N is equal to zero or greater than zero; then Respond when it is determined that N is equal to zero, and transmit the cylinder and head addresses without conversion; Make the following responses when N is determined to be greater than zero: Multiply the cylinder address by 2 ^N and dividing the head address by a second predetermined number and Dividing the head address by the second predetermined number and storing the remainder as the converted head address; then Perform logical OR operation on the quotient obtained after dividing the magnetic head address by the second predetermined number and the cylinder address, and store the result as the converted cylinder address; then Send the converted cylinder and head addresses to the past.

Images