CN109600928A - The manufacturing method of circuit board and applied to manufacturing its stacked structure - Google Patents
The manufacturing method of circuit board and applied to manufacturing its stacked structure Download PDFInfo
- Publication number
- CN109600928A CN109600928A CN201710916841.0A CN201710916841A CN109600928A CN 109600928 A CN109600928 A CN 109600928A CN 201710916841 A CN201710916841 A CN 201710916841A CN 109600928 A CN109600928 A CN 109600928A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- transfer printing
- layer
- circuit board
- printing layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000010023 transfer printing Methods 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 239000012528 membrane Substances 0.000 claims description 33
- 238000003825 pressing Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 166
- 239000000463 material Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000001723 curing Methods 0.000 description 5
- 239000005020 polyethylene terephthalate Substances 0.000 description 5
- 238000003384 imaging method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 150000001925 cycloalkenes Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007756 gravure coating Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0531—Decalcomania, i.e. transfer of a pattern detached from its carrier before affixing the pattern to the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention discloses a kind of manufacturing method of circuit board and applied to its stacked structure is manufactured, the manufacturing method of circuit board includes: multiple sunk structures are formed on transfer printing layer；Dielectric layer is formed on transfer printing layer, to form stacked structure, dielectric layer is at least mutually embedding with sunk structure；Stacked structure is pressed on substrate, so that dielectric layer contacts substrate；Pattern dielectric layer, and pattern dielectric layer above-mentioned includes to be exposed technique to stacked structure across transfer printing layer；And transfer printing layer is removed after exposure technology is completed.Whereby, the present invention controls the coarse area ratio of sunk structure by the raised structures of transfer printing layer, the contact area between conducting wire and dielectric layer can thus be increased and then improve the binding force between conducting wire and dielectric layer with its miniature line width, and avoid the problem that conducting wire is separated with dielectric layer and circuit board is made to generate blistering in subsequent technique.
Description
Technical field
The present invention relates to a kind of circuit boards, especially with regard to a kind of circuit board using transfer printing layer.
Background technique
Wiring board is the electronic devices such as current mobile phone, computer and digital camera (electronic device) and/or electricity
Depending on part required for the electrical home appliances such as, washing machine and refrigerator.Specifically, wiring board can carry and for chip
(chip), passive device (passive component), active member (active component) and MEMS member
A variety of electronic components (electronic component) such as part (Microelectromechanical Systems, MEMS) dress
It is provided thereon.In this way, electric current can be transmitted to electronic component above-mentioned via wiring board, so operate electronic device and/or
Electrical home appliances.
Summary of the invention
The contact area between conducting wire and dielectric layer can be increased the purpose of the present invention is to provide one kind and then improved
Binding force between conducting wire and dielectric layer with its miniature line width, and avoid conducting wire from separating with dielectric layer and in subsequent
Circuit board is made to generate the manufacturing method of the circuit board of bubble problem in technique.
An embodiment according to the present invention, a kind of manufacturing method of circuit board are formed multiple recessed on transfer printing layer
Fall into structure；Dielectric layer is formed on transfer printing layer, to form stacked structure, dielectric layer is at least mutually embedding with sunk structure；In base
Stacked structure is pressed on plate, so that the dielectric layer of stacked structure contacts substrate；Pattern dielectric layer, and patterned dielectric above-mentioned
Layer is comprising being exposed technique to stacked structure across transfer printing layer；And transfer printing layer is removed after exposure technology completion.
It is above-mentioned to form multiple sunk structures in including on transfer printing layer: shape in one or more embodiments of the invention
At membrane structure on substrate to form transfer printing layer；And pattern is formed on membrane structure using transfer printing process more to be formed
A sunk structure.
In one or more embodiments of the invention, the manufacturing method of circuit board also includes: in the film of transfer printing layer
It is formed after pattern in structure, cured film structure.
In one or more embodiments of the invention, formation dielectric layer above-mentioned is so that multiple recessed on transfer printing layer
Sunken Structure transfer forms multiple raised structures in dielectric layer close to the side of transfer printing layer.
In one or more embodiments of the invention, the manufacturing method of circuit board also includes: in pressing stacked structure
Before on substrate, first line layer is formed on substrate.It is so that first line layer is embedded in that stacked structure, which is pressed, in substrate
The dielectric layer of stacked structure.
In one or more embodiments of the invention, pattern dielectric layer above-mentioned includes: remove transfer printing layer it
Before, exposure technology to form exposure region and non-exposed area on the dielectric layer of stacked structure.After removing transfer printing layer, to warp
The dielectric layer of exposure carries out developing process.
In one or more embodiments of the invention, the manufacturing method of circuit board also includes: in patterned Jie
The second line layer is formed in electric layer.Second line layer is at least mutually embedding with the exposure region of dielectric layer.
In one or more embodiments of the invention, the refractive index of refractive index and the transfer printing layer tool of dielectric layer above-mentioned
It is substantially the same.
It is above-mentioned to form multiple sunk structures in being with more on transfer printing layer in one or more embodiments of the invention
The mode of dimension arrangement forms multiple sunk structures on transfer printing layer.
Another embodiment according to the present invention, a kind of stacked structure are applied to manufacture circuit board.Stacked structure includes to turn
Print layer and dielectric layer.Transfer printing layer includes substrate and membrane structure.Membrane structure is set on substrate, and has multiple multidimensional
The sunk structure of arrangement.Dielectric layer is set on transfer printing layer, and is located at least in multiple sunk structures of membrane structure, so that being situated between
Electric layer at least with the mutual down of multiple sunk structures on membrane structure.
In conclusion the present invention is mutual by the sunk structure of transfer printing process and transfer printing layer due to the raised structures of dielectric layer
It mends, therefore raised structures have coarse area ratio (the Roughness Surface Area substantially the same with sunk structure
Ratio,RSAR).Therefore, the coarse area ratio of sunk structure is controlled by the raised structures of transfer printing layer, thus can increase conduction
Contact area between route and dielectric layer improves the binding force between conducting wire and dielectric layer in turn with its miniature line width, and
Avoid the problem that conducting wire is separated with dielectric layer and circuit board is made to generate blistering (Blister) in subsequent technique.
Detailed description of the invention
For above and other purpose, feature, advantage and embodiment of the invention can be clearer and more comprehensible, said now in conjunction with attached drawing
It is bright as follows:
Fig. 1 to Figure 12 is painted circuit board the cuing open under different intermediate manufacturing states of an embodiment according to the present invention respectively
View.
Figure 13 to Figure 14 is painted the circuit board of another embodiment according to the present invention under different intermediate manufacturing states respectively
Cross-sectional view.
Specific embodiment
The following description will provide many different embodiments or embodiment to implement subject of the present invention.Element or row
The concrete example of column will be in following discussion to simplify the present invention.Certainly, these descriptions be only partial example and the present invention not with
This is limited.For example, fisrt feature is formed in above second feature, this narration is not only special with second comprising fisrt feature
The embodiment directly contacted is levied, is also formed between fisrt feature and second feature comprising other features, and in this case
The embodiment that fisrt feature will not be contacted directly with second feature.In addition, the present invention may repeat in different examples
Label or text.Duplicate purpose is rather than to define discussed different embodiments and configuration to simplify and clearly describe
Between relationship.
In addition, space relative terms such as " following ", " lower section ", " being lower than ", " above ", " top " and other similar use
Language is in order to facilitate the relationship of an elements or features and another elements or features in description figure herein.Space is opposite to be used
For language in addition to covering in figure other than discribed orientation, which more covers other orientation of device in use or operation.Namely
It says, when the orientation of the device (being rotated by 90 ° or in other orientation) different from attached drawing, used space is opposite herein
Term equally can be explained correspondingly.
Fig. 1 is please referred to Figure 12.The circuit board 1 that Fig. 1 to Figure 12 is painted an embodiment according to the present invention respectively (is shown in
In Figure 12) cross-sectional view under Yu Butong intermediate manufacturing state.
As shown in Figure 1, providing substrate 120.Then, membrane structure 122 is formed on substrate 120, to form transfer printing layer 12.
Also that is, the transfer printing layer 12 of present embodiment includes substrate 120 and membrane structure 122, and it is applied to manufacture circuit board 1.At this
In embodiment, form that membrane structure 122 may include coating process, depositing operation in the method on substrate 120 or other are any
Suitable technique.For example, depositing operation may include rotary coating (spin coating) technique, plane-of-weakness joint type coating (slot
Coating) technique, intaglio plate coating (Gravure coating) technique, idler wheel are coated with (Comma Coating) technique, physics gas
Mutually deposition (Physical vapor deposition, PVD) technique or other any suitable techniques.In the present embodiment,
The material of substrate 120 includes polyethylene terephthalate (Polyethylene terephthalate, PET), but of the invention
It is not limited with this material.
In the present embodiment, membrane structure 122 is schematically shown as single layer structure.However, in other embodiments, film knot
Structure 122 can be multilayered structure.The material of membrane structure 122 of the invention includes epoxy resin (expoxy), polymethylacrylic acid
Late resin (Arcylic resin) or cycloolefin (Cyclic-Olefin), and its thickness is substantially less than 5 microns (μm), but
The present invention is not limited with this material and thickness range.The refractive index of the membrane structure 122 of present embodiment and the folding of substrate 120
Penetrating has following relationships between rate:
1≥nPET/nA≥0.995；
Wherein nPETIt is defined as the refractive index of substrate 120, and nAIt is defined as the refractive index of membrane structure 122.However, this hair
The refractive index of bright substrate 120 is not limited with the refractive index of membrane structure 122 with forgoing relationship, other any suitable relationships are all
It can apply at this in the present invention.
As shown in Fig. 2, forming multiple sunk structures 1220 in the membrane structure of transfer printing layer 12 after forming transfer printing layer 12
On 122.Specifically, pattern P is formed on membrane structure 122 multiple recessed to be formed by present embodiment using transfer printing process P1
Fall into structure 1220.For example, the transfer printing process P1 of present embodiment be first production have pattern P micro-structure in motherboard (not
Be painted) on, and then will be located at pattern P on motherboard be needed on membrane structure 122 it is complementary with the micro-structure of motherboard recessed to be formed
Fall into structure 1220.
The sunk structure 1220 of the present embodiment is that equably have to repeat regularly to be formed in the form of multidimensional arrangement to turn
On the membrane structure 122 for printing layer 12.The form of aforementioned multidimensional arrangement refers to that sunk structure 1220 has interconnected bottom position
1222 and top position 1224.The top position 1224 of sunk structure 1220 has the first height H1 relative to substrate 120, and first
Height H1 is substantially less than 5 microns.The top position 1224 of sunk structure 1220 has the second height H2 relative to bottom position 1222,
And the ratio of the second height H2 and the first height H1 are substantially between 0.05 and 0.5.The top of adjacent sunk structure 1220
There is first distance D1 and second distance D2 between position 1224.In the present embodiment, first distance D1 is substantially the same
In second distance D2.In other embodiments, first distance D1 may differ from second distance D2, and form the recessed of density distribution
Fall into structure 1220.
Furthermore, one two inner wall 1226 in two adjacent sunk structures 1220 fold and have first
Angle A 1, and two inner walls 1226 of another one fold and have second angle A2.In the present embodiment, first angle A1 essence
On be identical to second angle A2, and substantially between 45 ° and 135 °.In other embodiments, first angle A1 can not
It is same as second angle A2.In some embodiments, coarse area ratio (the Roughness Surface of sunk structure 1220
Area Ratio, RSAR) substantially between 1.1 and 2.6.
As shown in figure 3, after being formed on membrane structure 122 of the pattern P in transfer printing layer 12, using curing process P2 with solid
Change membrane structure 122.In some embodiments, curing process P2 may include heat curing process or ultraviolet curing process.
As shown in figure 4, dielectric layer 14 is formed on the membrane structure 122 of transfer printing layer 12 after cured film structure 122
Stacked structure 10 is collectively formed.Also that is, stacked structure 10 includes transfer printing layer 12 and dielectric layer 14.Furthermore, it is formed
Dielectric layer 14 is in being so that the sunk structure 1220 for being located at transfer printing layer 12 transfers and forms the protrusion knots of multiple complementations on transfer printing layer 12
Structure 140 is in dielectric layer 14 close to the side of transfer printing layer 12.Raised structures 140 are distributed evenly on dielectric layer 14, on section
With outline of straight line (as shown in two side walls 148 in Fig. 4), and it is located at least in multiple sunk structures 1220 of membrane structure 122
In, so that dielectric layer 14 is at least mutually embedding with the sunk structure 1220 on transfer printing layer 12 via raised structures 140.
In the present embodiment, forming dielectric layer 14 in the method on transfer printing layer 12 may include coating process, and dielectric layer
14 material be photosensitive type interlayer material (Photoimagible Dielectric, PID), but the present invention not with previous process with
And material is limited.In some embodiments, the refractive index of the membrane structure 122 of the refractive index of dielectric layer 14 and transfer printing layer 12 it
Between have following relationships:
1≥nA/nPID≥0.998；
Wherein nPIDIt is defined as the refractive index of dielectric layer 14, and nAIt is defined as the refractive index of membrane structure 122.In this implementation
In mode, the refractive index of dielectric layer 14 and the refractive index of transfer printing layer 12 are substantially the same.However, the folding of dielectric layer 14 of the invention
It penetrates rate and the refractive index of membrane structure 122 is not limited with forgoing relationship, other any suitable relationships can all be applied at this at this
Invention.
Since the raised structures 140 of dielectric layer 14 and the sunk structure 1220 of transfer printing layer 12 are complementary, raised structures 140
With the coarse area ratio substantially the same with motherboard and sunk structure 1220, and with motherboard surface profile having the same.
In some embodiments, the coarse area ratio of the raised structures 140 of dielectric layer 14 is substantially between 1.1 and 2.6.In detail
For, if in the case where dielectric layer 14 is greater than 2.6 relative to the coarse area ratio on the surface of substrate 16, the be intended to shape of subsequent technique
At fine rule road be not easy to be formed on surface above-mentioned.Relatively, if dielectric layer 14 relative to substrate 16 surface it is coarse
In the case that area ratio is less than 1.1, surface above-mentioned can not provide enough contacts area to provide dielectric layer 14 and subsequent work
Binding force between the skill route to be formed, thus separated in subsequent technique dielectric layer 14 with route above-mentioned, and make
Blistering (Blister) problem occurs at circuit board 1.
Therefore, present embodiment can be by way of transfer in the sunk structure of formation and transfer printing layer 12 on dielectric layer 14
1220 complementary raised structures 140, to control the coarse area ratio of sunk structure 1220.Pass through the recessed of motherboard and transfer printing layer 12
Structure 1220 is fallen into, the coarse area ratio of the raised structures 140 of present embodiment can be controlled in the range of about 1.1 to about 2.6,
To improve the binding force of fine rule road and dielectric layer 14 that subsequent technique to be formed, and avoid in subsequent baking process to circuit
Bubble problem caused by plate 1.
As shown in figure 5, providing substrate 16.The substrate 16 of present embodiment has opposite first surface 160 and second
Surface 162, and can be ceramic wafer, metal plate, organic plates or other any suitable structures.Then, respectively at the of substrate 16
First line layer 18 is formed on one surface 160 and second surface 162.Then, after forming stacked structure 10, respectively at base
Stacked structure 10 is pressed on the first surface 160 and second surface 162 of plate 16, so that the dielectric layer 14 of stacked structure 10 contacts
The first surface 160 and second surface 162 of substrate 16, and first line layer 18 is respectively embedded into Jie of stacked structure 10
Electric layer 14.It in the present embodiment, include vacuum film pressing technique by the method that stacked structure 10 is pressed on substrate 16, but of the invention
It is not limited with this technique.In addition, board used in the vacuum film pressing technique of present embodiment may include batch single hop press mold
Machine or batch multistage vacuum film pressing machine.
As shown in fig. 6, in pressing stacked structure 10 after on substrate 16, pattern dielectric layer 14.Furthermore, originally
Embodiment is to be exposed technique P3 to stacked structure 10 across transfer printing layer 12, on the dielectric layer 14 ' of stacked structure 10
Form exposure region 142 and non-exposed area 144.For example, board used in the exposure technology P3 of present embodiment can wrap
Containing direct imaging (Imaging System, DI) board, laser direct imaging (Laser Direct Imaging, LDI) board,
Step-by-step movement (Stepper) board, contact exposure (Contact) board or other any suitable boards.By in this embodiment party
The refractive index of the dielectric layer 14 of formula and the refractive index of transfer printing layer 12 are substantially the same and be mutually matched, therefore in being exposed technique
During P3, transfer printing layer 12 will not cause the influence in exposure to the patterning of dielectric layer 14, thus can be on dielectric layer 14 '
Form the exposure region 142 in design and non-exposed area 144.
As shown in fig. 7, transfer printing layer 12 is removed to expose through exposing after being exposed technique P3 to stacked structure 10
The dielectric layer 14 ' of light.Also that is, on exposed dielectric layer 14 ', the protrusion knot complementary with the sunk structure 1220 of transfer printing layer 12
Structure 140 is exposed.Whereby, present embodiment is not necessary to through additional etch process with opposite in exposed dielectric layer 14 '
Formed on the surface of substrate 16 it is non-uniform slightly make structure, thus relevant etch process (for example, wet etching process) can be omitted,
And then simplifies manufacturing process and reduce manufacturing cost.
As shown in figure 8, developing process P4 is carried out to exposed dielectric layer 14 ' after removing transfer printing layer 12, to be formed
Patterned dielectric layer 14 ".Furthermore, present embodiment removes exposed dielectric layer 14 ' by developing process P4
In non-exposed area 144 and retain exposure region 142, to form via hole 146 and patterned dielectric layer 14 ".First Line
Road floor 18 is exposed via via hole 146.Then, after developing process P4 completion, using curing process to solidify warp
Patterned dielectric layer 14 ".In some embodiments, the curing process of present embodiment may include that heat curing process, light are solid
The combination or other any suitable techniques of chemical industry skill, above-mentioned technique.
As shown in figure 9, the second line layer 19 is formed in patterned after forming patterned dielectric layer 14 "
On dielectric layer 14 ", and it is formed in via hole 146 and contacts first line layer 18.Second line layer 19 at least with dielectric layer 14 '
Exposure region 142 on raised structures 140 mutually it is embedding.In the present embodiment, the second line layer 19 is formed in patterned Jie
Method in electric layer 14 " includes electroplating technology, but the present invention is not limited with this technique.In the present embodiment, the second line layer
19 material includes copper (Cu).In some embodiments, the material of the second line layer 19 can be aluminium (Al), but the present invention not with
This material is limited, other any suitable materials all can be applied to the present invention.
By the coarse area ratio of the raised structures 140 in present embodiment by control and substantially between 1.1 and 2.6 it
Between, thus the contact area between the second line layer 19 and patterned dielectric layer 14 " can be increased, and then improve the second route
Binding force between layer 19 and patterned dielectric layer 14 ", to reduce the second line layer 19 and patterned dielectric layer 14 "
Between because binding force deficiency due to lead to the chance being separated from each other.
As shown in Figure 10, after forming the second line layer 19, photoresist layer 17 is formed on the second line layer 19.This implementation
The photoresist layer 17 of mode at least corresponds to the setting of first line layer 18, and has multiple openings 170, to expose the second line of part
Road floor 19.The position that photoresist layer 17 can protect the second line layer 19 to be covered by photoresist layer 17.Then, it is lost by etch process P5
Carve 170 naked positions of opening of the second line layer 19 by photoresist layer 17.
As shown in figure 11, after etch process P5 is completed, the second line layer 19 is patterned to form first and leads
Electric line 190 and the second conducting wire 192.
As shown in figure 12, it is formed after the first conducting wire 190 and the second conducting wire 192, removes photoresist layer 17, into
And complete the circuit board 1 of present embodiment.Specifically, the first conducting wire 190 is located at least in via hole 146, and is connected
In first line layer 18.Second conducting wire 192 is located on the exposure region 142 of dielectric layer 14 ', and electrically isolates in the first conduction
Route 190.Controlled by the coarse area ratio of the raised structures 140 in present embodiment, because can due to increase by the second conducting wire
Contact area between 192 and patterned dielectric layer 14 ", and then improve the second conducting wire 192 and patterned Jie
Binding force between electric layer 14 " avoids the second conducting wire 192 and patterned dielectric layer 14 " point with its miniature line width
From and in making circuit board 1 lead to the problem of blistering in subsequent technique.For example, present embodiment is in subsequent technique
The line width for being formed by the second conducting wire 192 is smaller than 30 microns.
In addition, in the present embodiment, it is located at the raised structures 140 on patterned dielectric layer 14 " and is exposed to the
Between one conducting wire 190 and the second conducting wire 192, therefore it can contact others structure, Jin Erye in subsequent technique
Patterned dielectric layer 14 " and other subsequent binding forces being formed by between structure can be improved, to reduce phase between structure
The chance for mutually separating and circuit board 1 being caused to generate defect.
Please refer to Figure 13.Figure 13 is painted the cross-sectional view of the stacked structure 20 of another embodiment according to the present invention.Such as Figure 13
Shown, the stacked structure 20 of present embodiment includes transfer printing layer 22 and dielectric layer 24.The transfer printing layer 22 into one of stacked structure 20
Step includes substrate 120 and membrane structure 222.Connection relationship between the structures of these elements, function and each element all with
Stacked structure 10 shown in Fig. 1 to Fig. 4 is roughly the same, therefore can refer to aforementioned related description, and details are not described herein.It to say herein
It is bright, in place of the difference of embodiment shown in present embodiment and Fig. 1 to Fig. 4, in the transfer printing layer 22 in present embodiment
The inner wall 2226 of sunk structure 2220 there is the crooked outline that be recessed towards substrate 120, without interior in the cross-sectional view of such as Fig. 2
Outline of straight line shown in wall 1226.
The sunk structure 2220 of the present embodiment is that equably have to repeat regularly to be formed in the form of multidimensional arrangement to turn
On the membrane structure 222 for printing layer 22.The form of aforementioned multidimensional arrangement means that sunk structure 2220 has interconnected bottom position
2222 and top position 2224.The top position 2224 of sunk structure 2220 has the first height H3 relative to substrate 120, and first
Height H3 is substantially less than 5 microns (μm).The top position 2224 of sunk structure 2220 is high with second relative to bottom position 2222
H4 is spent, and the ratio of the second height H4 and the first height H3 are substantially between 0.05 and 0.5.Adjacent sunk structure 2220
Top position 2224 between have first distance D3 and second distance D4.In the present embodiment, first distance D3 is substantial
It is identical to second distance D4.In other embodiments, first distance D3 may differ from second distance D4, and form density distribution
Sunk structure 2220.In some embodiments, coarse area ratio (the Roughness Surface of sunk structure 2220
Area Ratio, RSAR) substantially between 1.1 and 2.6.
Since the raised structures 240 of dielectric layer 24 and the sunk structure 2220 of transfer printing layer 22 are complementary, raised structures 240
With the coarse area ratio substantially the same with motherboard and sunk structure 2220, and with motherboard surface profile having the same.
In some embodiments, the coarse area ratio of the raised structures 240 of dielectric layer 24 is substantially between 1.1 and 2.6.In detail
For, if in the case where dielectric layer 24 is greater than 2.6 relative to the coarse area ratio on the surface of substrate 16, the be intended to shape of subsequent technique
At fine rule road be not easy to be formed on surface above-mentioned.Relatively, if dielectric layer 24 relative to substrate 16 surface it is coarse
In the case that area ratio is less than 1.1, surface above-mentioned can not provide enough contacts area to improve dielectric layer 24 and subsequent work
Binding force between the skill route to be formed, thus separated in subsequent technique dielectric layer 24 with route above-mentioned, and make
Bubble problem occurs at circuit board 2.
Therefore, present embodiment can be by way of transfer in the sunk structure of formation and transfer printing layer 22 on dielectric layer 24
2220 (see Figure 13) complementary raised structures 240, to pass through the thick of the 2220 control projection structure 240 of sunk structure of transfer printing layer 22
Rough area ratio.Whereby, due to the sunk structure 2220 of transfer printing layer 22, the coarse area ratio of the raised structures 240 of present embodiment
It can be controlled in the range of about 1.1 to about 2.6, to improve the knot of fine rule road and dielectric layer 24 that subsequent technique to be formed
It closes, and avoids in subsequent baking process to blistering caused by circuit board 2 (Blister) problem.
It is moreover observed that the work between Figure 13 into Figure 14 under different intermediate manufacturing states in the present embodiment
Skill step is essentially the same as processing step shown in Fig. 5 to Figure 11, and therefore, relevant description can refer to aforementioned paragraphs, in this
Place repeats no more.
Please refer to Figure 14.Figure 14 is painted the cross-sectional view of the circuit board 2 of another embodiment according to the present invention.Such as Figure 14 institute
Show, the circuit board 2 of present embodiment includes substrate 16, first line layer 18, patterned dielectric layer 24 ", the first conductor wire
Road 190 and the second conducting wire 192.Connection relationship between the structures of these elements, function and each element all with Fig. 1 extremely
Circuit board 1 shown in Figure 12 is roughly the same, therefore can refer to aforementioned related description, and details are not described herein.Herein it is noted that
The place of the difference of embodiment shown in present embodiment and Fig. 1 to Figure 12 is located on dielectric layer 24 in the present embodiment
Raised structures 240 have far from the crooked outline outstanding of substrate 16, without raised structures 240 in the cross-sectional view of such as Figure 12
Shown in outline of straight line.Therefore, present embodiment replaces raised structures 140 as shown in Figure 10 with raised structures 240.
Controlled by the coarse area ratio of the raised structures 240 in present embodiment, because can due to increase by the second conducting wire
Contact area between 192 and dielectric layer 24, and then the binding force between the second conducting wire 192 and dielectric layer 24 is improved with micro-
Contract its line width, and avoids the problem that subsequent technique causes blistering (Blister) to circuit board 1.For example, present embodiment
The line width of the second conducting wire 192 formed in subsequent technique is smaller than 30 microns.
It is of the invention each that the feature of aforesaid plurality of embodiment can be such that those skilled in the art is better understood
A aspect.Those skilled in the art is it should be appreciated that in order to reach identical purpose and/or embodiments of the present invention
Same advantage further design or modify other techniques and structure based on the present invention.In the art
Technical staff it will also be appreciated that such equivalent structures without departing from spirit and scope of the present invention, and without departing substantially from the present invention
Spirit and scope under, those skilled in the art can carry out various changes, replacement and amendment herein.
Claims (10)
1. a kind of manufacturing method of circuit board, characterized by comprising:
Multiple sunk structures are formed on transfer printing layer；
Form dielectric layer on the transfer printing layer, to form stacked structure, wherein the dielectric layer at least with the recess knot
Structure is mutually embedding；
The stacked structure is pressed on substrate, so that the dielectric layer contacts the substrate；And
The dielectric layer is patterned, and the patterning dielectric layer includes:
Technique is exposed to the stacked structure across the transfer printing layer；
The transfer printing layer is removed after exposure technology completion.
2. the manufacturing method of circuit board as described in claim 1, which is characterized in that it is described on the transfer printing layer formed described in
Multiple sunk structures include:
Membrane structure is formed on substrate to form the transfer printing layer；And
Pattern is formed on the membrane structure to form the multiple sunk structure using transfer printing process.
3. the manufacturing method of circuit board as claimed in claim 2, which is characterized in that also include:
The pattern is formed after on the membrane structure described, solidifies the membrane structure using curing process.
4. the manufacturing method of circuit board as described in claim 1, which is characterized in that it is described on the transfer printing layer formed described in
Dielectric layer is so that the multiple sunk structure transfers to form multiple raised structures in the dielectric layer close to the transfer printing layer
Side.
5. the manufacturing method of circuit board as described in claim 1, which is characterized in that also include:
In the pressing stacked structure before on the substrate, first line layer is formed on the substrate, wherein institute
It is so that the first line layer is embedded in the dielectric layer that the pressing stacked structure, which is stated, in the substrate.
6. the manufacturing method of circuit board as described in claim 1, which is characterized in that the patterning dielectric layer includes:
It is described remove the transfer printing layer before, the exposure technology to be formed exposure region and non-exposed on the dielectric layer
Area；And
After the removal transfer printing layer, developing process is carried out to the exposed dielectric layer.
7. the manufacturing method of circuit board as claimed in claim 6, which is characterized in that also include:
Form the second line layer on the patterned dielectric layer, wherein second line layer at least with the dielectric layer
The exposure region it is mutually embedding.
8. the manufacturing method of circuit board as described in claim 1, which is characterized in that the refractive index of the dielectric layer and described turn
The refractive index for printing layer tool is substantially the same.
9. the manufacturing method of circuit board as described in claim 1, which is characterized in that it is described formed the multiple sunk structure in
It is to form the multiple sunk structure on the transfer printing layer in a manner of multidimensional arrangement on the transfer printing layer.
10. a kind of stacked structure is applied to manufacture circuit board, which is characterized in that the stacked structure includes transfer printing layer, includes:
Substrate；And
Membrane structure is set on the substrate, and the sunk structure with the arrangement of multiple multidimensional；And
Dielectric layer is set on transfer printing layer, and is located at least in the multiple sunk structure of the membrane structure, so that described
Dielectric layer at least with the mutual down of the multiple sunk structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710916841.0A CN109600928B (en) | 2017-09-30 | 2017-09-30 | Manufacturing method of circuit board and stack structure applied to manufacture the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710916841.0A CN109600928B (en) | 2017-09-30 | 2017-09-30 | Manufacturing method of circuit board and stack structure applied to manufacture the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109600928A true CN109600928A (en) | 2019-04-09 |
| CN109600928B CN109600928B (en) | 2021-04-02 |
Family
ID=65955605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710916841.0A Active CN109600928B (en) | 2017-09-30 | 2017-09-30 | Manufacturing method of circuit board and stack structure applied to manufacture the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109600928B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113707638A (en) * | 2020-05-22 | 2021-11-26 | 矽品精密工业股份有限公司 | Substrate structure and method for fabricating the same |
| CN114171488A (en) * | 2021-10-22 | 2022-03-11 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1294835A (en) * | 1998-02-26 | 2001-05-09 | 揖斐电株式会社 | Multilayer printed wiring board with filled conductive via structure |
| CN1823557A (en) * | 2003-09-29 | 2006-08-23 | 揖斐电株式会社 | Interlayer insulating layer for printed circuit board, printed circuit board and manufacturing method thereof |
| WO2017057263A1 (en) * | 2015-09-29 | 2017-04-06 | 大日本印刷株式会社 | Wiring line structure and method of manufacturing same, semiconductor device, multilayer wiring line structure and method of manufacturing same, semiconductor element mounting substrate, method of forming pattern structure, mold for imprinting and method of manufacturing same, imprint mold set, and method of manufacturing multilayer wiring board |
| CN106922088A (en) * | 2011-10-11 | 2017-07-04 | 日立化成株式会社 | Structure and its manufacture method and hot curing resin composition with conductor circuit |
-
2017
- 2017-09-30 CN CN201710916841.0A patent/CN109600928B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1294835A (en) * | 1998-02-26 | 2001-05-09 | 揖斐电株式会社 | Multilayer printed wiring board with filled conductive via structure |
| CN1823557A (en) * | 2003-09-29 | 2006-08-23 | 揖斐电株式会社 | Interlayer insulating layer for printed circuit board, printed circuit board and manufacturing method thereof |
| CN106922088A (en) * | 2011-10-11 | 2017-07-04 | 日立化成株式会社 | Structure and its manufacture method and hot curing resin composition with conductor circuit |
| WO2017057263A1 (en) * | 2015-09-29 | 2017-04-06 | 大日本印刷株式会社 | Wiring line structure and method of manufacturing same, semiconductor device, multilayer wiring line structure and method of manufacturing same, semiconductor element mounting substrate, method of forming pattern structure, mold for imprinting and method of manufacturing same, imprint mold set, and method of manufacturing multilayer wiring board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113707638A (en) * | 2020-05-22 | 2021-11-26 | 矽品精密工业股份有限公司 | Substrate structure and method for fabricating the same |
| CN114171488A (en) * | 2021-10-22 | 2022-03-11 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109600928B (en) | 2021-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8629354B2 (en) | PCB having embedded IC and method for manufacturing the same | |
| US20060087044A1 (en) | Electronic component, and system carrier and panel for producing an electronic component | |
| KR100782412B1 (en) | Transfer circuit forming method and circuit board manufacturing method | |
| CN101170875A (en) | Circuit board and method for manufacturing the same | |
| CN103107157A (en) | Chip package and method of forming the same | |
| CN113777880A (en) | Micro LED device and preparation method thereof | |
| CN109600928A (en) | The manufacturing method of circuit board and applied to manufacturing its stacked structure | |
| JP5426567B2 (en) | Printed circuit board, manufacturing method thereof, and panel for manufacturing printed circuit board | |
| US11322377B2 (en) | Stacking structure applicable to manufacturing circuit board | |
| KR101862243B1 (en) | Method for manuracturing printed circuit board with via and fine pitch circuit and printed circuit board by the same method | |
| CN110087392B (en) | Circuit board structure and manufacturing method thereof | |
| TW201307184A (en) | Thin film structure for high density inductance and redistribution in wafer level packaging | |
| CN101248708B (en) | Dielectric substrate with holes and method of manufacture | |
| KR20100117975A (en) | Embedded circuit board and method of manufacturing the same | |
| TWI642333B (en) | Circuit board and manufacturing method thereof | |
| US9997425B2 (en) | Layered benzocyclobutene interconnected circuit and method of manufacturing same | |
| KR102109046B1 (en) | Printed circuit board and manufacturing method thereof | |
| US20140174810A1 (en) | Printed circuit board and method of manufacturing the same | |
| US10607856B2 (en) | Manufacturing method of redistribution layer | |
| CN109714888A (en) | Circuit board and its manufacturing method | |
| CN104703408B (en) | The preparation method of high density copper coating board | |
| KR101051590B1 (en) | Ceramic substrate and its manufacturing method | |
| TW202027568A (en) | Substrate structure and manufacturing method thereof | |
| CN111465167B (en) | Substrate structure and manufacturing method thereof | |
| KR100782403B1 (en) | Circuit Board Manufacturing Method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |