CN109558282B

CN109558282B - A PCIE link detection method, system, electronic device and storage medium

Info

Publication number: CN109558282B
Application number: CN201811463366.7A
Authority: CN
Inventors: 智绪东
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2018-12-03
Filing date: 2018-12-03
Publication date: 2021-10-29
Anticipated expiration: 2038-12-03
Also published as: CN109558282A

Abstract

The present application discloses a PCIE link detection method, a system, an electronic device and a computer-readable storage medium. The method includes: when detecting that the target device is connected, identifying the PCIE port number corresponding to the target device; The system command is used to determine the PCIE slot corresponding to the target device; determine whether the current PCIE bus bandwidth and rate are within the preset range; if not, output alarm information; wherein the alarm information includes the PCIE slot. In the PCIE link detection method provided by the present application, the PCIE slot position of the target device is determined by detecting the PCIE port number, and the PCIE slot position is output when it is detected that the target device is faulty. The PCIE slot of the faulty equipment is determined by the system command, which replaces the analysis process of the maintenance personnel, realizes the purpose of quickly identifying and locating the faulty equipment, accelerates the maintenance speed of the production line, and improves the operation efficiency of the production line.

Description

PCIE link detection method, system, electronic equipment and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a PCIE link detection method, a PCIE link detection system, an electronic device, and a computer-readable storage medium.

Background

At present, a notebook, a desktop computer, a server and a storage largely use a PCIE bus to connect various devices, and the various devices are also connected by a PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) bus. During the production process, it is necessary to detect whether the PCIE link between each connected device is correct, and the link error may be classified as unrecognized (the recognized bus width is x0), degraded (for example, the connection originally of x16 recognizes only x8), and the like.

In the prior art, when a problem is detected in a certain PCIE link, the PCIE port number having the problem is sent to a maintenance person, and the maintenance person determines which link has the problem. However, in such a situation, a maintenance worker needs to know and understand the entire system deeply and is familiar with Linux instructions, so that the faulty port number can be recognized quickly, and after cross validation of a certain step, the faulty device is confirmed, and the detection efficiency is low.

Therefore, how to improve the failure detection efficiency of devices connected by using a PCIE link is a problem to be solved by those skilled in the art.

Disclosure of Invention

The present application aims to provide a PCIE link detection method, a PCIE link detection system, an electronic device, and a computer-readable storage medium, which improve the failure detection efficiency of devices connected by using a PCIE link.

To achieve the above object, the present application provides a PCIE link detection method, including:

when detecting that a target device is accessed, identifying a PCIE port number corresponding to the target device;

determining a PCIE slot position corresponding to the target equipment by using a system command according to the PCIE port number;

judging whether the bandwidth and the rate of the current PCIE bus are within a preset range;

if not, outputting alarm information; wherein the alarm information includes the PCIE slot.

Wherein the target device comprises an FC card.

Determining a PCIE slot corresponding to the target device by using a system command according to the PCIE port number includes:

obtaining a corresponding PCI ID number by utilizing a first system command according to the PCIE port number;

and determining a corresponding PCIE slot position according to the PCI ID number.

Wherein, the judging whether the bandwidth and the rate of the current PCIE bus are within the preset range includes:

and acquiring the current PCIE bus bandwidth and rate by utilizing a second system command, and judging whether the current PCIE bus bandwidth and rate are within a preset range.

To achieve the above object, the present application provides a PCIE link detection system, including:

the device comprises an identification module and a processing module, wherein the identification module is used for identifying a PCIE port number corresponding to target equipment when the access of the target equipment is detected;

a determining module, configured to determine, according to the PCIE port number, a PCIE slot corresponding to the target device by using a system command;

the judging module is used for judging whether the bandwidth and the rate of the current PCIE bus are within a preset range or not; if not, outputting alarm information; wherein the alarm information includes the PCIE slot.

Wherein the target device comprises an FC card.

Wherein the determining module comprises:

a first determining unit, configured to obtain a corresponding PCI ID number by using a first system command according to the PCIE port number;

and the second determining unit is used for obtaining the corresponding PCIE slot position according to the PCI ID number.

The judging module is specifically used for acquiring the current PCIE bus bandwidth and rate by utilizing a second system command and judging whether the current PCIE bus bandwidth and rate are within a preset range; and if not, outputting the alarm information.

To achieve the above object, the present application provides an electronic device including:

a memory for storing a computer program;

and the processor is used for realizing the steps of the PCIE link detection method when executing the computer program.

To achieve the above object, the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the PCIE link detection method as described above.

According to the above scheme, the PCIE link detection method provided in the present application includes: when detecting that a target device is accessed, identifying a PCIE port number corresponding to the target device; determining a PCIE slot position corresponding to the target equipment by using a system command according to the PCIE port number; judging whether the bandwidth and the rate of the current PCIE bus are within a preset range; if not, outputting alarm information; wherein the alarm information includes the PCIE slot.

According to the PCIE link detection method provided by the application, the PCIE slot position of the target equipment is determined by detecting the PCIE port number of the target equipment, and the PCIE slot position is output when the target equipment is detected to be in failure. The PCIE slot position of the fault equipment is determined through a system command, the analysis process of maintenance personnel is replaced, the purpose of quickly identifying and positioning the fault equipment is achieved, the maintenance speed of a production line is increased, and the operation efficiency of the production line is improved. The application also discloses a PCIE link detection system, an electronic device and a computer readable storage medium, which can also realize the technical effect.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart of a PCIE link detection method disclosed in the embodiment of the present application;

fig. 2 is a flowchart of another PCIE link detection method disclosed in the embodiment of the present application;

fig. 3 is a structural diagram of a PCIE link detection system disclosed in the embodiment of the present application;

fig. 4 is a block diagram of an electronic device disclosed in an embodiment of the present application;

fig. 5 is a block diagram of another electronic device disclosed in the embodiments of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application discloses a PCIE link detection method, which improves the fault detection efficiency of equipment connected by using a PCIE link.

Referring to fig. 1, a flowchart of a PCIE link detection method disclosed in the embodiment of the present application is shown in fig. 1, and includes:

s101: when detecting that a target device is accessed, identifying a PCIE port number corresponding to the target device;

in this embodiment, specific target devices are not specifically limited, and devices connected by using a PCIE link are all within the protection scope of this embodiment, for example, a CPU (Central Processing Unit, etc.), a PCH (Platform Controller Hub, integrated south bridge of intel corporation), a PCIE Switch (PCIE Switch or PCIE Switch), an Expander (SAS Expander), an SAS (Statistical Analysis System, which is a modular and integrated large application software System) card, an FC card (an optical fiber card), a network card, and the like.

In the prior art, for example, an FC card connected to PCIE x4 is inserted into SLOT. The system will recognize the port number of the card first, then detect the bus bandwidth, connection rate, etc. of the PCIE link, if the connection is wrong, the system will send the wrong port number to the maintenance personnel in the form of a Linux command, so that the maintenance personnel can analyze the port number to obtain a specific faulty device, where the Linux command is as follows:

ExMessage:[File:pcievdp.cpp,Line:173]00:01.1,Device:Intel Corporation Xeon E7v4/Xeon E5v4/Xeon E3v4/Xeon D PCI ERoot Port of PCI Express Root Complex[*],Current Link Width check fail,sys:x4,user:x0

wherein 00:01.1 is the PCIE port number.

In this step, as in the prior art, when it is detected that a target device accesses, a PCIE port number corresponding to the target device is identified.

S102: determining a PCIE slot position corresponding to the target equipment by using a system command according to the PCIE port number;

in specific implementation, when the PCIE port number of the target device is identified, the PCIE slot is determined by using a system command, and when the target device fails, the PCIE slot of the target device is directly reported.

Preferably, this step may include obtaining a corresponding PCI ID number by using the first system command according to the PCIE port number, and determining the corresponding PCIE slot according to the PCI ID number. The first system command can be lspci-s xxx, where xxx is the PCIE port number.

For a fixed PCIE port, the hardware connection is fixed and unchanged, and the assembly position is also fixed and unchanged for the whole machine, for example, in the example mentioned in the above step, the port number 00:01.1 is fixed and unchanged, the PCI ID number 8086:6f03 corresponding to the port number can be obtained by using the first system command through the port number, and the position of the externally-inserted PCIE card on the machine corresponding to the PCI ID (i.e., the PCIE SLOT position) is the SLOT B.

S103: judging whether the bandwidth and the rate of the current PCIE bus are within a preset range; if not, entering S104;

in this step, as in the prior art, whether the target device fails is determined by detecting whether the bandwidth and the rate of the current PCIE bus are within a preset range. It can be understood that, when the current PCIE bus bandwidth and rate are within the preset range, it indicates that the target device is normal, and the test procedure is ended. Otherwise, the target device fails, and the process goes to S104.

Preferably, the step may include obtaining the current PCIE bus bandwidth and rate by using a second system command, and determining whether the current PCIE bus bandwidth and rate are within a preset range. In a specific implementation, the current PCIE bus bandwidth and rate may be obtained by using a second system command, where the second system command may specifically be lspci-n-d xxx-vvv | grep-i width. Wherein xxx is the PCIE ID obtained in the previous step.

S104: outputting alarm information; wherein the alarm information includes the PCIE slot.

In specific implementation, when the target device fails, alarm information including the PCIE slot is sent to a maintenance worker. In the above example, when the FC card has a fault, the alarm information of the SLOT B PCIE connection error is directly reported, so that the embodiment can save the analysis action of the maintenance personnel, accelerate the verification and maintenance speed, and improve the production efficiency of the production line.

In the PCIE link detection method provided in the embodiment of the present application, the PCIE slot position of the target device is determined by detecting a PCIE port number of the target device, and the PCIE slot position is output when the target device is detected to have a failure. The PCIE slot position of the fault equipment is determined through a system command, the analysis process of maintenance personnel is replaced, the purpose of quickly identifying and positioning the fault equipment is achieved, the maintenance speed of a production line is increased, and the operation efficiency of the production line is improved.

The embodiment of the application discloses a PCIE link detection method, and compared to the previous embodiment, the embodiment further describes and optimizes the technical scheme. Specifically, the method comprises the following steps:

referring to fig. 2, a flowchart of another PCIE link detection method provided in the embodiment of the present application is shown in fig. 2, and includes:

s201: when detecting that a target device is accessed, identifying a PCIE port number corresponding to the target device;

s202: obtaining a corresponding PCI ID number by utilizing a first system command according to the PCIE port number, and determining a corresponding PCIE slot position according to the PCI ID number;

s203: acquiring the current PCIE bus bandwidth and rate by utilizing a second system command, and judging whether the current PCIE bus bandwidth and rate are within a preset range; if not, entering S204;

s204: outputting alarm information; wherein the alarm information includes the PCIE slot.

In the following, a PCIE link detection system provided in the embodiment of the present application is introduced, and a PCIE link detection system described below and a PCIE link detection method described above may refer to each other.

Referring to fig. 3, a structure diagram of a PCIE link detection system provided in the embodiment of the present application is shown in fig. 3, and includes:

an identifying module 301, configured to identify a PCIE port number corresponding to a target device when it is detected that the target device accesses;

a determining module 302, configured to determine, according to the PCIE port number, a PCIE slot corresponding to the target device by using a system command;

a determining module 303, configured to determine whether a current PCIE bus bandwidth and rate are within a preset range; if not, outputting alarm information; wherein the alarm information includes the PCIE slot.

The PCIE link detection system provided in the embodiment of the present application determines the PCIE slot position of the target device by detecting a PCIE port number of the target device, and outputs the PCIE slot position when detecting that the target device fails. The PCIE slot position of the fault equipment is determined through a system command, the analysis process of maintenance personnel is replaced, the purpose of quickly identifying and positioning the fault equipment is achieved, the maintenance speed of a production line is increased, and the operation efficiency of the production line is improved.

On the basis of the above embodiment, as a preferred implementation, the target device includes an FC card.

On the basis of the foregoing embodiment, as a preferred implementation manner, the determining module 302 includes:

On the basis of the foregoing embodiment, as a preferred implementation manner, the determining module 303 specifically obtains the current PCIE bus bandwidth and rate by using a second system command, and determines whether the current PCIE bus bandwidth and rate are within a preset range; and if not, outputting the alarm information.

The present application further provides an electronic device, referring to fig. 4, a structure diagram of an electronic device provided in an embodiment of the present application, as shown in fig. 4, includes:

a memory 100 for storing a computer program;

the processor 200, when executing the computer program, may implement the steps provided by the above embodiments.

Specifically, the memory 100 includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions, and the internal memory provides an environment for the operating system and the computer-readable instructions in the non-volatile storage medium to run. The processor 200 may be a Central Processing Unit (CPU), a controller, a microcontroller, a microprocessor, or other data Processing chips in some embodiments, and provides computing and control capabilities for an electronic device, and when executing a computer program stored in the memory 100, the steps of the PCIE link detection method provided in any embodiment may be implemented.

According to the embodiment of the application, the PCIE slot position of the target equipment is determined by detecting the PCIE port number of the target equipment, and the PCIE slot position is output when the target equipment is detected to be in failure. The PCIE slot position of the fault equipment is determined through a system command, the analysis process of maintenance personnel is replaced, the purpose of quickly identifying and positioning the fault equipment is achieved, the maintenance speed of a production line is increased, and the operation efficiency of the production line is improved.

On the basis of the above embodiment, as a preferred implementation, referring to fig. 5, the electronic device further includes:

and an input interface 300 connected to the processor 200, for acquiring computer programs, parameters and instructions imported from the outside, and storing the computer programs, parameters and instructions into the memory 100 under the control of the processor 200. The input interface 300 may be connected to an input device for receiving parameters or instructions manually input by a user. The input device may be a touch layer covered on a display screen, or a button, a track ball or a touch pad arranged on a terminal shell, or a keyboard, a touch pad or a mouse, etc.

A display unit 400, connected to the processor 200, for displaying data processed by the processor 12 and for displaying a visualized user interface. The display unit 15 may be an LED display, a liquid crystal display, a touch-controlled liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, and the like.

And a network port 500 connected to the processor 200 for performing communication connection with each external terminal device. The communication technology adopted by the communication connection can be a wired communication technology or a wireless communication technology, such as a mobile high definition link (MHL) technology, a Universal Serial Bus (USB), a High Definition Multimedia Interface (HDMI), a wireless fidelity (WiFi), a bluetooth communication technology, a low power consumption bluetooth communication technology, an ieee802.11 s-based communication technology, and the like.

While FIG. 5 shows only an electronic device having the

assembly

100 and 500, those skilled in the art will appreciate that the configuration shown in FIG. 5 does not constitute a limitation of the electronic device, and may include fewer or more components than shown, or some components may be combined, or a different arrangement of components.

The present application also provides a computer-readable storage medium, which may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk. The storage medium stores thereon a computer program, and the computer program, when executed by a processor, implements the steps of the PCIE link detection method provided in any of the above embodiments.

The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims

1. a PCIE link detection method, is characterized in that, comprises:

When detecting that the target device is connected, identify the PCIE port number corresponding to the target device;

Utilize system commands to determine the PCIE slot corresponding to the target device according to the PCIE port number;

Determine whether the current PCIE bus bandwidth and rate are within the preset range;

If not, output alarm information; wherein, the alarm information includes the PCIE slot;

Wherein, the PCIE slot corresponding to the target device is determined by using a system command according to the PCIE port number, including:

Utilize the first system command to obtain the corresponding PCI ID number according to the PCIE port number;

The corresponding PCIE slot is determined according to the PCI ID number.

2 . The PCIE link detection method according to claim 1 , wherein the target device comprises an FC card. 3 .

3. PCIE link detection method according to claim 1, is characterized in that, whether described judging current PCIE bus bandwidth and speed are within preset scope, comprising:

Acquire the current PCIE bus bandwidth and rate by using the second system command, and determine whether the current PCIE bus bandwidth and rate are within a preset range.

4. a PCIE link detection system, is characterized in that, comprises:

an identification module, configured to identify the PCIE port number corresponding to the target device when it is detected that the target device is connected;

A determination module, used for determining the PCIE slot corresponding to the target device by utilizing a system command according to the PCIE port number;

a judgment module, configured to judge whether the current PCIE bus bandwidth and rate are within a preset range; if not, output alarm information; wherein, the alarm information includes the PCIE slot;

Wherein, the determining module includes:

A first determining unit, used to obtain a corresponding PCI ID number by utilizing the first system command according to the PCIE port number;

The second determining unit is configured to obtain the corresponding PCIE slot according to the PCI ID number.

5. The PCIE link detection system according to claim 4, wherein the target device comprises an FC card.

6. according to the described PCIE link detection system of claim 4, it is characterized in that, described judging module is to utilize the second system command to obtain described current PCIE bus bandwidth and speed specifically, and judge whether described current PCIE bus bandwidth and speed are? Within the preset range; if not, the module that outputs alarm information.

7. An electronic device, characterized in that, comprising:

memory for storing computer programs;

The processor is configured to implement the steps of the PCIE link detection method according to any one of claims 1 to 3 when executing the computer program.

8. A computer-readable storage medium, characterized in that, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the PCIE chain as described in any one of claims 1 to 3 is realized The steps of the road detection method.