CN109491290A - A kind of cold standby bus complexing circuit suitable for digital processing system - Google Patents
A kind of cold standby bus complexing circuit suitable for digital processing system Download PDFInfo
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- CN109491290A CN109491290A CN201811369372.6A CN201811369372A CN109491290A CN 109491290 A CN109491290 A CN 109491290A CN 201811369372 A CN201811369372 A CN 201811369372A CN 109491290 A CN109491290 A CN 109491290A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
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- G05B2219/21063—Bus, I-O connected to a bus
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Abstract
一种适用于数字处理系统的冷备份总线复用电路，首先对主控制板与多个被控制板的数据传输进行数据信号复用，每个被控制板中的多个被控FPAG采用菊花链方式互联，其次在主控制板与被控制板信号通路上增加接口阻抗隔离电路，实现对被控制板接收信号与发送信号的阻抗隔离，以及主控制板与多个被控制板的阻抗匹配，最后对接口阻抗匹配电路与对应的被控制板分别进行独立供电，使得被控制板在开关机两种状态下与主控制板的阻抗匹配，以及被控制板开机后的数据复用。
A cold backup bus multiplexing circuit suitable for a digital processing system. First, the data signal multiplexing is performed on the data transmission between the main control board and multiple controlled boards, and the multiple controlled FPAGs in each controlled board are daisy-chained. Secondly, an interface impedance isolation circuit is added to the signal path between the main control board and the controlled board to realize the impedance isolation of the received signal and the transmitted signal of the controlled board, and the impedance matching between the main control board and multiple controlled boards. Finally, The interface impedance matching circuit and the corresponding controlled board are independently powered, so that the controlled board is matched with the impedance of the main control board in two states of on and off, and the data is multiplexed after the controlled board is turned on.
Description
Technical field
The present invention relates to multiband in the communications field and the transponder systems of multi-mode working system, especially a kind of suitable
Cold standby bus complexing circuit for digital processing system.
Background technique
In traditional answering machine communication TT & C architecture, system generally uses fixed frequency range, fixed frequency point and single-mode
Work.In the answering machine communication TT & C architecture of a new generation, often using the complicated system with more working frequency range, multi-operation mode
It unites, core function and the key technical indexes need more set FPGA in the system, and by system master making sheet, load refreshing is different
Software, to realize the arbitrary switch of different systems and function.Currently, using traditional more board data under this working system
The hardware design scheme of transmission passes through low-frequency connector, back panel connector mainly directly to interconnect or two class of data bus protocol
Method is realized.The system communicated using direct mutual contact mode, the limited node resource of connector are constrained needed for multi-mode system
Data transmission path, and designer trends based on product small light, system is also difficult to constantly to expand design scale complete
It is transmitted at a large amount of data.Data bus protocol method need to use respective standard transport protocol, but part FPGA interface not
It centainly supports the mode protocol, the mutual contact mode application is made to be very limited.Therefore, it in the design of existing system, faces
Design scale is huge, the switching of more boards frequently and the various problems such as system power dissipation is larger.
Summary of the invention
Technical problem solved by the present invention is having overcome the deficiencies of the prior art and provide a kind of suitable for digital processing system
The cold standby bus complexing circuit of system, the circuit include data-reusing, interface impedance isolation and switched-mode power supply management three parts
Circuit, in realization system under the conditions of the cold standby of multiple board timesharing bootings, the reliable transmission of high data volume multiplexing, compared to tradition
Method, which greatly reduces data channel number, improves resource utilization, and reduces system power dissipation.
The technical solution of the invention is as follows: a kind of cold standby bus complexing circuit suitable for digital processing system, packet
Include data-reusing circuit, interface impedance isolation circuit, switched-mode power supply management circuit, in which:
Data-reusing circuit, it is described to master board and multiple data transmission progress data-signal multiplexings by control panel
Master board completed with multiple data interconnections by control panel by same group of data access, the transmission data-signal of master board
It is sent by mother daughter board connector to multiple controlled making sheet, the master control FPGA of master board sends data-signal extremely by mother daughter board connector
By the interface impedance isolation circuit of control panel；
Interface impedance isolation circuit, including interface chip circuit, controlled terminal build-out resistor R1, filter capacitor C1；Interface
The input terminal of chip circuit receives the data-signal that master control FPGA is sent, output termination one end controlled terminal build-out resistor R1, quilt
Control terminal build-out resistor R1 is another to terminate the input pin that FPGA is controlled in controlled making sheet, and filter capacitor C1 mono- terminates controlled terminal
Build-out resistor R1 and the input pin that FPGA is controlled in control panel, filter capacitor C1 other end ground connection；
Switched-mode power supply manages circuit, interface impedance matching circuit is carried out with corresponding controlled plate respectively it is independently-powered, often
A partition source power supply by control panel is that interface impedance isolation circuit is powered for a long time, and power supply power supply is it by control panel according to being
System requires time sharing power supply, and when so that being shut down by control panel, interface impedance match circuit can guarantee master control borad and multiple controlled plates
Impedance matching, data isolation and controlled plate booting after data-reusing；Including power supply chip D1, output voltage
With resistance R2, R3, enabled state resistance R4, polarity filter capacitor C2, C3, C4, C5, ceramic filter capacitor C6, C7；Power supply chip
The input voltage VIN of D1 terminates polarity filter capacitor C2 positive terminal, another termination polarity filter capacitor of polarity filter capacitor C2
C3 positive terminal, the other end ground connection of polarity filter capacitor C3, the output voltage VO UT of D1 terminate polarity filter capacitor C4 positive terminal,
The other end concatenates the positive terminal of C5, and the end output voltage VO UT of polarity filter capacitor C5 other end ground connection, D1 connects ceramic filtering simultaneously
The end ADJ of the one end wave capacitor C6, C7, C6, C7 other end ground connection, D1 connects output voltage build-out resistor R2, R3 one end simultaneously, and R2 is another
One end ground connection, the end VOUT of another termination D1 of R3, enabled state resistance R4 connect the port ENABLE and the middle position of VIN of D1.
Described is connect using after data channel multiplexing interconnection with master board by control panel, is controlled by multi-disc in control panel
The data interconnection of FPGA uses daisy chaining.
The controlled terminal build-out resistor R1 is between 200 Ω to 1K Ω, and filter capacitor C1 capacitance is in 0.01uF to 0.1uF
Between.
The interface chip circuit includes interface chip N1, power supply filter capacitor C8, power supply filter capacitor C9, current limliting electricity
Hinder R5, current-limiting resistance R6, resistance R7, resistance R8；Two enable port OE1, OE2 the connecting resistance R7, resistance R7 of interface chip N1
Other end ground connection, power supply port VCCA1, VCCA2 of interface chip N1 meet filter capacitor C8, current-limiting resistance R5, filters
The other end of capacitor C8 is grounded, another termination power supply VOUT, the power supply port VCCB1 of interface chip N1 of current-limiting resistance R5,
VCCB2 connects filter capacitor C9 and current-limiting resistance R6, the other end ground connection of filter capacitor C9, another termination power supply of current-limiting resistance R6
Data direction port DIR1, DIR2 connecting resistance R8 of VOUT, interface chip N1, another termination VOUT of resistance R8, interface chip
8 ports GND of N1 are grounded, and the data-in port 1B0 of N1 receives data-signal, and the data-out port 1A0 of N1 is sent
Data-signal.
The advantages of the present invention over the prior art are that:
(1) present invention is transmitted by multiplex data, is saved hardware resource, has been saved the port resource and data of master control FPGA
Transmission channel quantity, and in similar complication system, there is certain scalability；
(2) present invention is isolated by impedance and is matched, and guarantees the low-power consumption work for the cold standby that the more boards of system are switched in timesharing
Make under mechanism, realizes the reliability multiplexing transmission of data；
(3) autonomous power supply system of the present invention and the mutually independent region electric supply system of board power supply, it is multiple to realize data
With while also preferably reduce system power dissipation.
Detailed description of the invention
Fig. 1 is data multiplexing system functional block diagram；
Fig. 2 is port equivalent model block diagram；
Fig. 3 is partition source schematic block circuit diagram；
Fig. 4 is interface chip schematic block circuit diagram.
Specific embodiment
A kind of cold standby bus complexing circuit suitable for digital processing system, the circuit are hindered by data-reusing, interface
Anti- isolation, switched-mode power supply management three parts circuit are realized, combine each interface by control panel to hinder using data-reusing transmission channel
It is multiple by control panel to realize that master board is transmitted to by single group data channel time-sharing multiplex for anti-isolation circuit, and master board source
Hold port Impedance independent of by the working condition of control panel, it is ensured that under the working condition of terminal board timesharing booting, signal
The constantly matching of transfer impedance, avoids the impedance mismatching to the port master control FPGA.Electricity is isolated in each interface impedance by control panel
The independently-powered mechanism of plate inner region power supply module that road uses, when being in cold standby off-mode by control panel, interface isolation
Circuit still plays the effect of signal isolation and impedance matching, guarantees the data-signal multiplexing of cold standby under system low-power consumption.
Data-reusing circuit, to master board and multiple data transmission progress data-signal multiplexings by control panel, transmission
Number of channels is completed to transmit with multiple data by control panel by one group of access, and the multi-disc of intralamellar part is controlled FPGA and then uses chrysanthemum
Chain mode interconnects；
Interface impedance isolation circuit is sent a signal to by mother daughter board connector for master control FPGA and is connect by the first order of control panel
Circuit is received, which includes interface chip circuit, controlled terminal build-out resistor R1, filter capacitor C1 and controlled FPGA.Pass through
The data signal transmission of multiplexing extremely after control panel, is carried out by interface impedance isolation circuit to the data-signal received and source
Isolation, and the impedance matching with terminal.
Since on multiplex data transmission link, the board that terminal is in cold standby off-mode will lead to source board master
The impedance mismatching of the port FPGA is controlled, antistatic diode (end Vcc) is positive inside the input port of the controlled FPGA of off-mode
Conducting, the inside I/O generate equivalent small resistance, and the resistance is similar to the output I/O earth impedance magnitude of source master control FPGA,
Influence source end port impedance.Therefore, the interface chip on transmission link can carry out the isolation of signal between plate, and in interface chip
Output end, close on the port I/O of controlled FPGA, concatenate impedance matching resistor, add signal filter capacitor；The resistance of series resistor
Value need to be much larger than source master control fpga logic device inside equivalent resistance resistance value, avoid controlled terminal under cold standby state with source
Terminal impedance mismatch realizes the data-reusing under cold standby；
Between 200 Ω to 1K Ω, filter capacitor C1 capacitance exists build-out resistor R1 resistance value in interface impedance isolation circuit
Between 0.01uF to 0.1uF；
Switched-mode power supply management circuit is supplied the partial circuit by the independently-powered design to interface impedance matching circuit
Electricity and its peeled away by the power supply of Control card, each partition source power supply by control panel is that interface impedance isolation circuit is long-term
Power supply, power supply power supply be its by control panel according to system requirements time sharing power supply, when so that the board being in off-mode, interface is still
So guarantee the impedance matching on data path, it is ensured that the data-reusing of low-power consumption timesharing booting；
The model specification that switched-mode power supply manages power supply chip in circuit is MSK5101-00, and peripheral circuit includes defeated
Voltage matches resistance R2, R3, enabled state resistance R4 out, polarity filter capacitor C2, C3, C4, C5, ceramic filter capacitor C6, C7；
Specific implementation method of the invention is further described in detail with reference to the accompanying drawing.
In view of satellite operation on orbit and the space radiation environment of complexity, select ACTEL company insensitive to single-particle
Core processor of the antifuse device A54SX72A-1CQ208M as master board, realize by control panel multiband, multimode
The program updating of formula loads control.The XQ5VFX130T-1EF1738I type of XILINX company is used by the core FPGA of control panel
Number chip.
In order to save master control FPGA port resource and data transmission channel, while system power dissipation is reduced, in realization system
Multiple boards can timesharing booting cold standby status data multiplexing, the invention proposes a kind of buses suitable for cold standby system
Multiplex circuit, the circuit include bus complexing circuit, and interface impedance isolation circuit, switched-mode power supply management circuit are realized, such as Fig. 1
It is shown, in which:
(1) data-reusing circuit, for what is transmitted with two by four groups of refreshings load data of control panel to master board
Reuse plan, by master control FPGA by mother daughter board connector and two by control panel totally four controlled FPGA interconnections, respectively by control panel
It is interconnected between internal FPGA using daisy chaining, realizes that multiple groups internet data is passed with the time-sharing multiplex of same group of data access
It is defeated；
(2) interface impedance isolation circuit, the partial circuit include interface chip circuit (as shown in Figure 4), terminal coupling electricity
R1, terminal filter capacitor C1 are hindered, as shown in Figure 2.Use 54ACS164245SF for core interface device, terminal coupling resistance R1
It is serially connected between interface chip and controlled FPGA, mono- end Jie of filter capacitor C1 is controlled FPGA signal input part, and one end pulls down to
Ground.Interface chip circuit includes interface chip N1, power supply filter capacitor C8, power supply filter capacitor C9, current-limiting resistance R5, current limliting electricity
Hinder R6, resistance R7, resistance R8；Two enable ports OE1, OE2 while series resistor R7 of interface chip N1, resistance R7's is another
Port ground connection；Power supply port VCCA1, VCCA2 of interface chip N1 concatenates filter capacitor C8 and current-limiting resistance R5 simultaneously, filters
The other end of wave capacitor C8 is grounded, another termination power supply VOUT of current-limiting resistance R5；The power supply port of interface chip N1
VCCB1, VCCB2 concatenate filter capacitor C9 and current-limiting resistance R6 simultaneously, and the other end of filter capacitor C9 is grounded, and current-limiting resistance R6 is another
One termination power supply VOUT；Data direction port DIR1, DIR2 while series resistor R8 of interface chip N1, the other end of resistance R8
Meet VOUT；8 ports GND of interface chip N1 are grounded；The data-in port 1B0 of N1 receives data input signal, N1's
Data-out port 1A0 sends data output signal；
Be transmitted to by the data of multiplexing by after control panel, by interface impedance isolation circuit to the signal received carry out with
The Isolation of source end port and impedance matching with terminal；
(3) switched-mode power supply manages circuit, uses MSK5101-00H for core power chip D1, and output rated current is
1.5A can satisfy the requirement of the interface impedance isolation circuit.Its peripheral circuit includes, as shown in figure 3, output voltage
Build-out resistor R2, R3, enabled state resistance R4, polarity filter capacitor C2, C3, C4, C5, ceramic filter capacitor C6, C7；Power supply core
The input voltage VIN end of piece D1 concatenates polarity filter capacitor C2 positive terminal, the other end concatenation C3 anode of polarity filter capacitor C2
End, the other end ground connection of polarity filter capacitor C3；The output voltage VO UT of D1 terminates polarity filter capacitor C4 positive terminal, the other end
Concatenate the positive terminal of C5, polarity filter capacitor C5 other end ground connection；The end output voltage VO UT of D1 connects ceramic filter capacitor simultaneously
The one end C6, C7, C6, C7 other end ground connection；The end ADJ of D1 connects output voltage build-out resistor R2, R3 one end, another termination of R2 simultaneously
Ground, the R3 other end connect the end VOUT of D1 simultaneously, and enabled state resistance R4 is concatenated between the port ENABLE of D1 and VIN；
Wherein polar capacitor C4, C5 close on the placement of output voltage port, to avoid output voltage concussion；R4 is concatenated to power supply
Between the port ENABLE of chip and VIN, enabled working condition is set by power supply chip.By to interface impedance matching circuit
Independently-powered design, partial circuit power supply and the power supply of its board are peeled away, when so that the board being in off-mode,
Interface still ensures that the impedance matching on data path, it is ensured that the data-reusing of low-power consumption timesharing booting；
The method that the present invention uses cold standby data-reusing: open system master board is powered on, two are in by control panel
Off-mode is controlled by instruction, is opened to two power supply+5V_J by control panel partition source management module, is passed through its electricity
Source circuit is converted to 3.3V_J and is supplied to each interface isolation circuit power supply by control panel, guarantees the long work shape of the partial circuit
State；
Controlled according to instruction, cold standby off-mode be in by control panel 2, in open system by the power supply of control panel 1+
5VIN_1,1.0V, 2.5V, 3.3V, 3.3V_ needed for being respectively converted into board by the multi-disc DC/DC and LDO in plate
The voltages such as AVDD, 3.0V_AVDD, 1.8V, output to number each in plate, analog device；
Using data-reusing transmission channel, data are exported by master control FPGA, are transmitted to by mother daughter board connector by control panel
1, it is transmitted to controlled FPGA1 after the interface isolation circuit isolation matching in plate, the load for carrying out S frequency range program refreshes；When
After the completion of the load of FPGA1 program refreshes, is controlled according to instruction, be transmitted to by same group of data transmission channel by control panel 1
FPGA1 refreshes the load brush of load C frequency range program in the daisy chain signal mutual contact mode for being transferred directly to FPGA2 by FPGA1
Newly, it realizes and is transmitted by the data time-sharing multiplex of two frequency ranges in control panel 1；
It is controlled according to instruction, cold standby off-mode, the confession by control panel 2 in open system will be placed in by control panel 1
Electricity+5VIN_2 is transmitted to the load refreshing that X frequency range program is carried out by the FPGA1 of control panel 2 by same group of data transmission channel；
It is completed when FPGA1 program loads to refresh, is controlled according to instruction, be transmitted to by same group of data transmission channel by control panel 2
FPGA1, in the daisy chain mutual contact mode for being transmitted to FPGA2 by FPGA1, the load for refreshing load KA frequency range program refreshes.
It is an advantage of the invention that by using the transmission mode of data-reusing, it is incorporated in and each interface impedance is equipped with by control panel
The circuit of isolation and switched-mode power supply management realizes the timesharing booting under system cold standby, is reducing FPGA and is transmitting logical
The port resource on road reduces system power dissipation while occupancy.
The present invention has been applied in certain answering machine satellite system, realizes a single machine and completes four work frequencies of system
Section, the switchable type work of nine kinds of operating modes, the present invention realize simple, and debugging flexibly, is gone into operation more products with batch, uniform
Secondary success.The present disclosure applies equally to the data-reusing transmission that more board multi-discs are controlled FPGA, have certain scalability.
In conclusion the invention proposes a kind of cold standby data-reusing circuits of low hardware resource, with multiplexing type data
Transmission channel, in conjunction with interface impedance isolation circuit and its power supply circuit, so that the source end port impedance of master board does not depend on
In by the working condition of control panel, with lower hardware resource, the cold standby of more board timesharing bootings in multi-mode system is realized
The reliable transmission of part data-reusing, and effectively reduce system power dissipation.
The content that description in the present invention is not described in detail belongs to the well-known technique of those skilled in the art.
Claims (4)
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| CN201811369372.6A CN109491290B (en) | 2018-11-16 | 2018-11-16 | A Cold Backup Bus Multiplexing Circuit Suitable for Digital Processing System |
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| CN201811369372.6A CN109491290B (en) | 2018-11-16 | 2018-11-16 | A Cold Backup Bus Multiplexing Circuit Suitable for Digital Processing System |
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Inventor after: Li Wenchen Inventor after: Liu Jie Inventor after: Zhao Hui Inventor after: Xing Jianli Inventor after: Liu Junfeng Inventor before: Li Wenchen Inventor before: Liu Jie Inventor before: Zhao Hui Inventor before: Xing Jianli Inventor before: Liu Junfeng |