CN109449891B

CN109449891B - Single-wafer battery protection circuit capable of improving peak voltage resistance and charging and discharging circuit

Info

Publication number: CN109449891B
Application number: CN201811536650.2A
Authority: CN
Inventors: 蒋锦茂; 谭健
Original assignee: Suzhou Saixin Electronic Technology Co ltd
Current assignee: Suzhou Saixin Electronic Technology Co ltd
Priority date: 2018-11-06
Filing date: 2018-12-14
Publication date: 2025-08-01
Anticipated expiration: 2038-12-14
Also published as: CN110854831A; CN212572075U; CN110854832A; CN109449891A; CN212572076U; CN212543359U; CN110854832B; CN209250230U

Abstract

The invention provides a single-wafer battery protection circuit and a charging and discharging circuit for improving peak voltage resistance. The battery protection circuit comprises a basic protection circuit, a clamping circuit, a grid substrate control circuit and a charge-discharge control MOS tube, wherein one end of a source electrode or a drain electrode of the charge-discharge control MOS tube is connected to a battery, the other end of the source electrode or the drain electrode is connected to a charger or a load, a grid electrode and a substrate are connected to the grid substrate control circuit, the basic protection circuit detects the charge-discharge condition of the battery and sends a control signal to the grid substrate control circuit, the grid substrate control circuit controls the conduction condition of the charge-discharge control MOS tube according to the control signal so as to control the charge-discharge of the battery, and the clamping circuit is used for clamping the power supply voltage of the grid substrate control circuit and preventing the grid substrate control circuit and the charge-discharge control MOS tube from being damaged. The invention can prevent the battery protection circuit from being damaged by peak voltage and direct current high voltage, and prolong the service life of the charge-discharge circuit.

Description

Single-wafer battery protection circuit capable of improving peak voltage resistance and charging and discharging circuit

Technical Field

The present invention relates to the field of battery charging and discharging technologies, and in particular, to a single-wafer battery protection circuit and a charging and discharging circuit capable of improving peak voltage resistance.

Background

With the increasing functions of mobile terminals in recent years, the performance of mobile terminals is also rapidly improved, which also puts greater demands on the terminal battery. Some application batteries need to be made very small, some application batteries need to be made very low in cost, while traditional battery protection schemes generally occupy a large area and have high cost, and are not suitable for new market demands.

Conventional battery protection schemes are achieved by discrete devices. A control circuit chip and a chip comprising two N-type power MOS transistors are required. The control circuit chip controls the grid voltages of the two power MOS tubes to realize charge and discharge control of the battery. The control circuit chip is made in a CMOS process, while the power MOS die is typically made with a vertical structure of DMOS or UMOS transistors. Since CMOS and DMOS/UMOS are two completely different processes, the control circuit chip and the two power MOS chips are typically from two different suppliers, being two separate chips. In addition, the charge-discharge peripheral circuit of this split device scheme requires two resistors and one capacitor.

In order to reduce the area of the above-mentioned scheme for battery protection of the separator and reduce the cost of the scheme, in chinese patent CN103474967a, i propose a single-wafer battery protection circuit and a charge-discharge circuit. The single-wafer battery protection circuit integrates a control circuit chip, two power MOS tube chips and a resistor at the periphery of the control circuit chip, the two power MOS tube chips and the resistor at the periphery of the control circuit chip into a semiconductor substrate, and a charge-discharge circuit at the periphery only needs one resistor and one capacitor. The single-wafer battery protection scheme proposed by my department integrates a control circuit chip and two power MOS chips on a semiconductor substrate, and further, my department combines two power MOS tube structures of the traditional scheme into one power MOS tube so as to further reduce the scheme area and the scheme cost.

Currently, to minimize circuit area and cost, a 5V CMOS process is typically used. And the breakdown voltage of the 5V CMOS process MOS transistor is 8V-12V. Because the battery protection circuit may generate peak voltage up to 16V and direct current high voltage in the process of charging and discharging and production test, the single-wafer battery protection circuit manufactured by the 5V CMOS process may be broken down by the peak voltage or the direct current high voltage, so that the single-wafer battery protection circuit is damaged.

A visual solution is to select a semiconductor process with higher breakdown voltage to increase the withstand voltage of the single-wafer battery protection circuit so that the single-wafer battery protection circuit can bear 16V peak voltage and direct-current high voltage, but in this way, the process layer number is increased, the occupied area of a semiconductor device on a chip is greatly increased, and the cost of the protection circuit is greatly increased.

In view of the above, the present invention provides a single-wafer battery protection circuit and a charge-discharge circuit capable of improving the anti-spike voltage capability, so as to solve the problem that the single-wafer battery protection circuit is damaged by the dc high voltage and the spike voltage.

Disclosure of Invention

The invention aims to provide a single-wafer battery protection circuit and a charging and discharging circuit capable of improving the anti-spike voltage capability, which can prevent the single-wafer battery protection circuit from being damaged by direct-current high voltage and spike voltage during the battery production test process and the charging and discharging use, and prolong the service lives of the charging and discharging circuit and the battery.

The technical scheme provided by the invention is as follows:

the invention provides a single-wafer battery protection circuit capable of improving peak voltage resistance, which comprises a basic protection circuit, a clamp voltage circuit, a grid substrate control circuit and a charge-discharge control MOS tube, wherein the basic protection circuit is connected with the clamp voltage circuit;

One ends of a source electrode and a drain electrode of the charge-discharge control MOS tube are connected to a negative end of the battery, the other ends of the source electrode and the drain electrode of the charge-discharge control MOS tube are connected to a negative electrode of a charger or a load, and a grid electrode and a substrate of the charge-discharge control MOS tube are respectively connected to the grid electrode substrate control circuit.

The basic protection circuit detects the charge and discharge condition of the battery and sends a control signal to the grid substrate control circuit, so that the grid substrate control circuit controls the conduction condition of the charge and discharge control MOS tube according to the control signal, and the charge and discharge of the battery are controlled;

the clamp circuit is used for clamping the power supply voltage of the grid substrate control circuit and preventing the grid substrate control circuit and the charge-discharge control MOS tube from being damaged.

The battery protection circuit in the scheme relates to a great number of semiconductor devices, and the battery protection circuit can be damaged by peak voltage or direct current high voltage during battery production test and charge and discharge use. For example, the breakdown voltage of a 5V CMOS process MOS tube is 8V-12V, and if the peak voltage generated in the production test process and the charge-discharge use exceeds the breakdown voltage, the MOS tube is damaged. The general visual solution is to increase the withstand voltage value of the MOS tube, so that the number of process layers and the area of the MOS tube on the chip are increased, and the cost of the chip is increased. In order to protect devices from being damaged by peak voltage or direct current high voltage on the premise of guaranteeing cost and chip area, the clamp voltage circuit is added, voltage is clamped in a certain range, and even if the peak voltage or direct current high voltage exists in the production test process and during charging and discharging use, the voltage is clamped in a safe voltage range by the clamp voltage circuit, so that the protection circuit is prevented from being damaged.

In the production test process of the battery protection circuit, the battery protection chip and the resistor-capacitor are firstly made into a battery protection board, and then the battery protection board and the battery core are connected together to form the battery with the protection function. Test equipment such as a protection board tester, a comprehensive tester, a separate container cabinet and the like can be frequently used in the production test process of the battery. The protection board tester is used for detecting whether the protection board is qualified or not, the comprehensive tester is used for detecting whether the battery with the protection function is qualified or not, and the capacity division cabinet is used for detecting the capacity of the battery with the protection function. The test equipment often generates peak voltage or direct current high voltage up to 16V in the test process, so that the breakdown voltage of the charge control MOS tube Mc and the discharge control MOS tube Md is required to be more than 16V in the traditional battery protection scheme, so that the battery with the protection function is prevented from being broken down by the peak voltage or direct current high voltage of 16V in the production test process.

In theory, the single-wafer battery protection circuit needs to enable the breakdown voltage of the source electrode and the drain electrode of the charge-discharge control MOS tube to be more than 16V at the same time, so that the battery with the protection function cannot be broken down by peak voltage or direct current high voltage up to 16V generated by test equipment in the production test process. However, the breakdown voltage of the charge-discharge control MOS tube is more than 16V, and the cost is high.

By adopting the clamping circuit, the voltage withstand voltage of the charge-discharge control MOS tube only needs 12V, namely the breakdown voltage of the traditional 5V CMOS process, so that the battery with the protection function can be prevented from being broken down by peak voltage or direct current high voltage up to 16V in the production test process and during charge-discharge use.

Preferably, the grid substrate control circuit comprises a grid control part and a substrate control part, wherein the grid control part is connected with the grid of the charge-discharge control MOS tube, and the substrate control part is connected with the substrate of the charge-discharge control MOS tube;

The grid control part outputs a grid control response signal according to the control signal to control the grid voltage of the charge-discharge control MOS tube, and the substrate control part outputs a substrate control response signal according to the control signal to control the substrate voltage of the charge-discharge control MOS tube so as to control the conduction condition of the charge-discharge control MOS tube.

Preferably, the voltage divider circuit comprises a voltage dividing resistor R5 and a zener diode, one end of the voltage dividing resistor R5 is connected to the power supply voltage VDD, the other end of the voltage dividing resistor R5 is connected to the negative electrode of the zener diode, and the positive electrode of the zener diode is connected with the VSS end.

According to the voltage stabilization principle of the zener diode, the power supply voltage of the grid substrate control circuit can be clamped within a safe voltage range well, and the grid substrate control circuit and the charge-discharge control MOS tube are protected from being damaged.

Preferably, the clamp circuit comprises a divider resistor R5 and N diodes which are connected in series in one direction, wherein N is more than or equal to 1;

one end of the voltage dividing resistor R5 is connected to the power supply voltage VDD, the other end of the voltage dividing resistor R5 is connected to the positive ends of the N unidirectional serial diodes, and the negative ends of the N unidirectional serial diodes are connected to the VSS end.

Preferably, the clamp circuit comprises a divider resistor R5 and N NMOS tubes which are connected in series, wherein N is more than or equal to 1;

One end of the voltage dividing resistor R5 is connected to the power supply voltage VDD, and the other end of the voltage dividing resistor R5 is connected to the VSS end through the N NMOS tubes connected in series.

Preferably, the clamp circuit comprises a divider resistor R5 and N PMOS tubes connected in series, wherein N is more than or equal to 1;

One end of the voltage dividing resistor R5 is connected to the power supply voltage VDD, and the other end of the voltage dividing resistor R5 is connected to the VSS end through the N PMOS tubes connected in series.

Preferably, the clamp circuit includes a low dropout linear regulator.

Preferably, the battery protection circuit also comprises an over-temperature protection circuit, which is used for detecting the temperature of the chip integrated by the battery protection circuit during charging and discharging and controlling the transmission of the control signal together with the basic protection circuit.

Preferably, the over-temperature protection circuit comprises an over-temperature comparator and a logic control unit.

According to the scheme, the over-temperature protection circuit can detect the temperature of the chip where the battery protection circuit is located in real time, and when the temperature is abnormal, the over-temperature protection circuit can send an over-temperature control signal to disconnect the charge and discharge loop, so that the protection effect on the battery protection circuit is achieved.

Preferably, the basic protection circuit specifically includes:

the device comprises a reference circuit, a discharge overcurrent comparator, a discharge short-circuit comparator, a charge overcurrent comparator, an overdischarge voltage comparator, an overcharge voltage comparator, a delay circuit and a charge-discharge detection circuit, wherein the control signals comprise a first control signal VCHOC, a second control signal VOC2 and a third control signal VOD2;

The reference circuit is used for generating a positive input signal VOC1 of the discharging over-current comparator, a positive input signal VSHORT of the discharging short-circuit comparator, a negative input signal VCHOC of the charging over-current comparator, a negative input signal VODV of the over-discharging voltage comparator, a positive input signal VOCV of the over-charging voltage comparator, and generating a positive input signal VPN and a negative input signal VOTP of the over-temperature comparator.

The discharge overcurrent comparator outputs a high level VDD or a low level VGND based on the comparison result of the magnitude of the positive input signal VOC1 and the magnitude of the negative input signal virtual ground voltage VM 1;

The discharging short-circuit comparator outputs a high level VDD or a low level VGND based on the comparison result of the magnitude of the positive input signal VSHORT and the magnitude of the negative input signal virtual ground voltage VM 1;

the charge overcurrent comparator outputs a high level VDD or a low level VGND based on the comparison result of the magnitude of the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC, and outputs the first control signal VCHOC to the gate substrate control circuit;

the overcharge voltage comparator outputs a high level VDD or a low level VGND based on a comparison result of the positive input signal VOCV and the negative input signal VROCV of the VDD voltage divided by the resistor;

the overdischarge voltage comparator outputs a high level VDD or a low level VGND based on a comparison result of the positive input signal VRODV and the negative input signal VODV of the VDD voltage divided by the resistor;

the delay circuit performs respective corresponding delays based on the output result of the discharging overcurrent comparator, the output result of the discharging short-circuit comparator, the output result of the charging overcurrent comparator, the output result of the overcharging voltage comparator and the output result of the overdischarging voltage comparator, and the respective delays may be different in length, and outputs the second control signal VOC2 and the third control signal VOD2 through logic processing.

Preferably, in the basic protection circuit, when the second control signal VOC2 and the third control signal VOD2 both output a high level, the gate substrate control circuit outputs a high level gate voltage VGATE as a gate control response signal according to the second control signal VOC2 and the third control signal VOD 2;

when at least one of the second control signal VOC2 and the third control signal VOD2 outputs the low level VGND, the gate substrate control circuit outputs the low level gate voltage VGATE as a gate control response signal according to the second control signal VOC2 and the third control signal VOD 2.

The invention also provides a battery charging circuit, which comprises the battery protection circuit, a charger, a battery and an RC filter circuit, wherein:

One end of a resistor R0 in the RC filter circuit is connected with a power supply voltage VDD end, and the other end of the resistor R0 is connected with the anode of the battery;

one end of a capacitor C0 in the RC filter circuit is connected with the power supply voltage VDD end, and the other end of the capacitor C0 is connected with the cathode of the battery;

the positive electrode of the charger is connected with the positive electrode of the battery during charging to provide charging voltage for the battery.

The invention also provides a battery discharging circuit, which comprises the battery protection circuit, an RC filter circuit, a battery and a load, wherein:

the positive electrode of the battery is connected with the positive electrode of the load during discharging to provide power for the load, and the negative electrode of the load is connected with the negative electrode of the battery through a charge-discharge control MOS tube.

The single-wafer battery protection circuit and the charging and discharging circuit for improving the peak voltage resisting capability can bring at least one of the following beneficial effects:

In the invention, the voltage between the power supply voltage GVDD and the VSS end of the grid substrate control circuit is clamped within a preset range by utilizing the clamping circuit. The withstand voltage of the battery protection circuit chip in the production test process and the charging and discharging use is improved, and the damage of devices in the battery protection circuit is prevented.

Drawings

The above features, technical features, advantages and implementation manners of a single-wafer battery protection circuit and a charge/discharge circuit for improving the peak voltage resistance will be further described with reference to the accompanying drawings in a clear and understandable manner.

Fig. 1 is a block diagram of a charging and discharging circuit of a conventional discrete device battery protection circuit;

FIG. 2 is a diagram of a charging and discharging circuit of a conventional single wafer battery protection circuit;

FIG. 3 is a schematic circuit diagram of a gate substrate control circuit in accordance with the prior art of single wafer battery protection schemes;

FIG. 4 is a block diagram of a single wafer battery protection circuit and charge-discharge circuit for improving anti-spike voltage capability in accordance with the present invention;

fig. 5 is a block diagram of the basic protection circuit in fig. 4;

FIG. 6 is a circuit diagram of the over-temperature protection circuit of FIG. 4;

FIG. 7 is a circuit schematic of the gate substrate control circuit of FIG. 4;

FIG. 8 is another circuit schematic of the gate substrate control circuit of FIG. 4;

FIG. 9 is a schematic diagram of a voltage clamping circuit in accordance with one embodiment of the present invention;

FIG. 10 is a schematic diagram of another embodiment of a clamping circuit according to the present invention;

FIG. 11 is a schematic diagram of another embodiment of a clamping circuit;

FIG. 12 is a schematic diagram of another embodiment of a clamping circuit according to the present invention;

fig. 13 is another circuit schematic of the clamping circuit in an embodiment of the invention.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.

For the sake of simplicity of the drawing, the parts relevant to the present invention are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.

Fig. 1 is a charge-discharge circuit of a conventional discrete device battery protection scheme. The control circuit A controls the grid voltages of the two power MOS transistors (Mc and Md) to realize the charge and discharge control of the battery. The control circuit a is made of CMOS technology, and the power MOS transistors (Mc and Md) are typically made of DMOS or UMOS transistors of a vertical structure. Since CMOS and DMOS/UMOS are two completely different processes, the control circuit a and the two power MOS transistors (Mc and Md) are typically from two different suppliers, two separate chips, two resistors R0 and Rvm and one capacitor C0 are required for the peripheral circuits.

Fig. 2 is an internal block diagram of a battery protection circuit and a charge-discharge circuit in a single wafer battery protection scheme technique. When the battery protection circuit enters over-charge voltage protection, over-charge over-current protection or over-charge over-temperature protection, the charging path of the battery protection circuit is closed, and the voltage of the charger is completely provided by an external charging circuit. The basic protection circuit, the over-temperature protection circuit, the logic control unit I12 and the logic control unit I13 in the battery protection circuit are battery powered, have no high voltage and cannot be damaged by the high voltage. However, the power supply voltage of the gate substrate control circuit during the charge protection is the charger voltage, and the voltage may reach a high voltage of 16V during the production test and the charger access, which may damage the gate substrate control circuit and may damage the charge-discharge control MOS transistor M0. Fig. 3 is a circuit diagram of a gate substrate control circuit in a prior art single wafer battery protection scheme. Referring to fig. 3, the substrate control circuit includes a gate control circuit for outputting VGATE and a substrate control circuit for outputting VSUB, and since the low level VSS voltage and VGND voltage of the gate control circuit are not identical, the low level of the VOD voltage, VOC voltage, and VCHOC voltage inputted from the gate control circuit is VGND voltage, and it is necessary to convert to VSS voltage. The VOD voltage, the VOC voltage, and the VCHOC voltage all require a level shifter circuit, and the level shifter circuit of the VOD voltage is described as an example.

The MOS transistors M7, M8, M9 and M10 and the logic control unit I6 complete low level conversion of the VOD voltage. When the VOD voltage is at the high level VDD, the transistor M7 is turned off, the transistor M8 is turned on, the VODP voltage is at the high level VDD, and when the VOD voltage is at the low level VGND, the transistor M7 is turned on, the transistor M8 is turned off, the VODP voltage is at the low level VSS, and the conversion from the VGND level to the VSS level is completed. The VOC voltage is converted to the VOCP voltage, VCHOC to VCHOC P voltage, VCHOC N voltage. When VODP voltage and VOCP voltage are both high level, VGATE terminal outputs high level VDD, when one of VODP voltage and VOCP voltage is low level VSS, VGATE terminal outputs low level VSS. When VOCP is high level, VGOC is low level, VGOCB is high level, MOS tube M1 is on, MOS tube M2 is off, output VSUB voltage is equal to VGND voltage, when VOCP is low level,

VGOC is high level, VGOCB is low level, MOS tube M1 is cut off, MOS tube M2 is conducted, and output VSUB voltage is equal to VM voltage. When VCHOC is high, VCHOC P is high, VCHOC N is low, MOS tube M19 is on, MOS tube M20 is off, VSS is equal to VGND, VCHOC P is low, VCHOC P is low, VCHOC N is high, MOS tube M19 is off, MOS tube M20 is on, and VSS is equal to VM.

In the above description, when VCHOC V CMOS process MOS transistor breakdown voltage is 8V-12V, which is lower than the generated spike voltage or dc voltage, the existing gate substrate control circuit may be damaged or broken down when VDD voltage-VSS voltage differential is the voltage differential between VDD voltage and VM voltage, and the spike voltage or dc voltage up to 16V may be generated during the production test process and the charge-discharge use.

Based on the analysis conclusion, the invention provides a novel battery protection circuit. Fig. 4 is a block diagram of a battery charge-discharge circuit in an embodiment of the invention. Fig. 5 is a structural diagram of the basic protection circuit in fig. 4. Fig. 6 is a circuit diagram of the over-temperature protection circuit of fig. 4. Fig. 7 and 8 are two circuit diagrams of the gate substrate control circuit in fig. 4. As shown in fig. 7 and 8, the gate substrate control circuit includes a gate control portion and a substrate control portion, which have a common circuit. Referring to fig. 4 to 7, a clamp circuit is added and a gate substrate control circuit is improved with respect to the battery protection circuit of fig. 2 and the gate substrate control circuit of fig. 3. In fig. 4, when the battery protection circuit enters the overcharge voltage protection, the charge overcurrent protection or the charge overtemperature protection, the charging path of the battery protection circuit is closed, and the voltage of the charger is completely supplied by the external charging circuit. Referring to fig. 7, when the positive power supply terminal of the improved gate substrate control circuit is the output voltage GVDD of the voltage clamping circuit, and the battery protection circuit enters the overcharge voltage protection, the charge overcurrent protection or the charge overtemperature protection, the negative power supply terminal VSS voltage is VM, and the negative power supply terminal VSS voltage is VGND. The power supply voltage of the grid substrate control circuit is GVDD-VM or GVDD-VGND, the power supply voltage is clamped and is lower than the breakdown voltage of all MOS tubes in the grid substrate control circuit, and the grid substrate control circuit is not damaged.

Referring to fig. 4, the battery protection circuit in an embodiment of the present invention includes a basic protection circuit, an over-temperature protection circuit, a clamp voltage circuit, a gate substrate control circuit, a first logic control unit I12, a second logic control unit I13, and a charge-discharge control MOS transistor M0. One ends of a source electrode and a drain electrode of the charge-discharge control MOS tube M0 are connected to the negative end of the battery, and the other ends of the source electrode and the drain electrode of the charge-discharge control MOS tube M0 are connected to the negative electrode of the charger or the load; the basic protection circuit detects the charge and discharge condition of the battery, and sends a control signal to the grid substrate control circuit, so that the grid substrate control circuit controls the conduction condition of the charge and discharge control MOS tube M0 according to the control signal, thereby controlling the charge and discharge of the battery;

referring to fig. 5, the basic protection circuit in fig. 4 includes a reference circuit, a discharge overcurrent comparator, a discharge short-circuit comparator, a charge overcurrent comparator, an overdischarge voltage comparator, an overcharge voltage comparator, a charge detection circuit, a delay circuit, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a logic control unit I0, a logic control unit I1, a logic control unit I2, a logic control unit I3, and a logic control unit I4.

The reference circuit is configured to generate the positive input signal VOC1 of the discharging over-current comparator, the positive input signal VSHORT of the discharging short-circuit comparator, the negative input signal VCHOC of the charging over-current comparator, the reference output voltages VPN, VOTP, the positive input signal VOCV of the over-charging voltage comparator, and the negative input signal VODV of the over-discharging voltage comparator.

The discharge overcurrent comparator outputs a high level VDD when VOC1 is greater than VM1 and outputs a low level VGND when VOC1 is lower than VM1 based on the magnitude comparison result of the positive input signal VOC1 and the negative input signal virtual ground voltage VM 1.

The discharging short-circuit comparator outputs a high level VDD when VSHORT is greater than VM1 and outputs a low level VGND when VSHORT is lower than VM1 based on a comparison result of the magnitude of the positive input signal VSHORT and the negative input signal virtual ground voltage VM 1.

The charge over-current comparator outputs a high level VDD when VM1 is greater than VCHOC and outputs a low level VGND when VM1 is lower than VCHOC based on the magnitude comparison result of the positive input signal virtual ground voltage VM1 and the negative input signal VCHOC.

The overcharge voltage comparator outputs a high level VDD or a low level VGND based on a comparison result of the positive input signal VOCV and the negative input signal VROCV, which is obtained by dividing the VDD voltage by resistors.

The overdischarge voltage comparator outputs a high level VDD or a low level VGND based on the comparison result of the positive input signal VRODV and the negative input signal VODV of the VDD voltage divided by the resistor.

The charge-discharge detection circuit outputs the high level VDD or the low level VGND based on the magnitude comparison result of the positive input VGND and the negative input signal VM 1. VGND is higher than VM1 and is lower than VM1 and is higher than VDD.

The delay circuit is used for delaying the output signal VOC1P of the discharge overcurrent comparator, the output signal VSHORTP of the discharge short-circuit comparator, the output signal VCHOC1 of the charge overcurrent comparator, the output signal VODVP of the overdischarge voltage comparator and the output signal VOCVP of the overcharge voltage comparator, and the delayed output signals correspond to the outputs VDOC1 and VDSHORT, VDCHOC, VDODV, VDOCV. VDOC1 is a VOC1P delayed signal, VDSHORT is a VSHORTP delayed signal, VDCHOC is a VCHOC1 delayed signal, VDODV is a VODVP delayed signal, and VDOCV is a VOCVP delayed signal.

When VDOC, VDSHORT, VDODV are both high, the VOD3 output is high VDD, and when at least one of VDOC1, VDSHORT, VDODV, is low, the VOD3 output is low VGND.

When VDCHOC, VDOCV are both high, the VOC3 output is high level VDD. When at least one of VDCHOC and VDOCV is low, the VOC3 output is at a low level VGND.

When at least one of VOD3 and VCHP is high, VOD2 output is high level VDD, and when both VOD3 and VCHP are low, VOD2 output is low level VGND.

When at least one of VOC3, VCHN is high, the VOC2 output is high level VDD, and when both VOC3, VCHN are low, the VOC2 output is low level VGND.

Fig. 6 is an over-temperature protection circuit, which includes an over-temperature comparator, a first logic control unit I14, a second logic control unit I15, and a third logic control unit I16.

The over-temperature comparator outputs a high level when VPN is greater than VOTP and outputs a low level when VPN is less than VOTP based on a comparison result of the magnitudes of the positive input signal VPN and the negative input signal VOTP.

The VCHOTP output is high level VDD when at least one of VOTPP, VCHN1 is high, and VCHOTP output is low when both VOTPP, VCHN1 are low.

The VDISOTP output is high level VDD when at least one of VOTPP, VCHP is high, and VDISOTP output is low when both VOTPP, VCHP are low.

Fig. 7 is a circuit schematic of a gate substrate control circuit. The resistors R11, R12, R13, R14, R15 and R16 and the MOS transistors M21, M22, M23, M24, M25 and M26 are added compared with the original grid substrate control circuit. The function of adding resistors and MOS transistors is described by R11, R12, M21 and M22, wherein the positive power supply voltage of the grid substrate control circuit is the output voltage GVGDD of the clamping circuit due to the addition of the clamping circuit, the input voltage VOD is the high level VDD or the low level VGND, the voltages of the GVGDD-VDD are more than the GATE breakdown voltages of the MOS transistors M7 and M8 so as to damage the MOS transistors M7 and M8, and the maximum voltages from GATE of the M7 and M8 to the GVGDD after the R11, M21, R12 and M22 are added are the parasitic diode voltages of the M21 and M22, so that the parasitic diode voltages can not damage the MOS transistors. Similarly, R13, R14, M23 and M24 protect M11 and M12 from damage, and R15, R16, M25 and M26 protect M15 and M16 from damage.

Fig. 8 shows the same functions as described above, with the diodes being replaced by M21, M22, M23, M24, M25, and M26 in fig. 7.

Fig. 9 is a block diagram of a clamp circuit in an embodiment of the invention. The voltage divider comprises a voltage dividing resistor R5 and a zener diode Z0 which are connected in series, wherein the connecting end of the voltage dividing resistor R5 and the zener diode Z0 is an output end GVDD, the other end of the voltage dividing resistor R5 is connected with a power supply voltage VDD, and the other end of the zener diode is connected with a VSS end.

The principle of the circuit capable of clamping the voltage between GVDD and VSS within a preset range is that the PN junction of the zener diode has extremely low resistance in a reverse breakdown state, so that the GVDD-VSS voltage is equal to the breakdown voltage of the zener diode when the zener diode is conducted, and the GVDD is almost equal to VDD when the zener diode is not conducted.

When the voltages of VDD to VSS are lower than the conducting voltage of the Zener, GVGD is equal to VDD, and when the voltages of VDD to VSS are higher than the conducting voltage of the Zener, the highest output voltage of GVGD to VSS is the voltage of the Zener. The conducting voltage of the zener diode in the integrated circuit is 5.5-6.5V, if the voltage of VDD-VSS is continuously increased, the voltage of the zener diode is stabilized at the conducting voltage of the zener diode, the rest voltage is reduced on the resistor R5, the voltage drop of tens of volts on the resistor R5 is not problematic, and therefore, the voltage withstand of VDD-VSS is as high as tens of volts, and the voltage clamping circuit is not damaged.

The power supply voltage of the grid substrate control circuit is GVDD-VSS, and the maximum value is the conducting voltage of the zener diode. The breakdown voltage is 8V-12V lower than that of the MOS transistor, so that the gate substrate control circuit cannot be damaged.

Fig. 10 is a block diagram of a clamp circuit in another embodiment of the invention.

Referring to FIG. 10, the voltage divider circuit comprises a voltage divider resistor R5 and N unidirectional series diodes, wherein N is larger than or equal to 1, one end of the voltage divider resistor R5 is connected to a power supply voltage VDD, the other end of the voltage divider resistor R5 is connected to the positive ends of the N unidirectional series diodes, and the negative ends of the N unidirectional series diodes are connected to the VSS end.

It can be seen that the difference compared to fig. 9 is that the zener diode is replaced by N series diodes that are turned on unidirectionally from the GVDD terminal to the VSS terminal of the supply voltage, where N is ≡1.

The principle that the plurality of diodes are connected in series to clamp the voltage between GVDD and VSS within a preset range is that by utilizing the forward conduction voltage ramp characteristic of the diodes, when the diodes are conducted, the GVDD-VSS voltage is equal to the sum of the conduction voltages of the plurality of diodes, and when the diodes are not conducted, the GVDD is almost equal to VDD.

Fig. 11 and 12 are block diagrams of a clamp circuit in still another embodiment of the present invention.

Referring to fig. 11 and 12, the clamp circuit comprises a divider resistor R5 and N series NMOS tubes, wherein N is equal to or greater than 1, one end of the divider resistor R5 is connected to a supply voltage VDD, and the other end of the divider resistor R5 is connected to a VSS end through the N series NMOS tubes. Or the voltage divider circuit comprises a voltage divider resistor R5 and N PMOS tubes connected in series, wherein N is more than or equal to 1, one end of the voltage divider resistor R5 is connected to the power supply voltage VDD, and the other end of the voltage divider resistor R5 is connected to the VSS end through the N PMOS tubes connected in series.

It can be seen that the difference compared with FIG. 9 is that the zener is replaced by N series NMOS tubes or N series PMOS tubes, where N≥1.

The principle that the voltage between GVDD and VSS can be clamped in a preset range by connecting a plurality of NMOS in series is that the drain end and the grid electrode of the NMOS are in short circuit, the NMOS is equivalent to a diode, and the forward conduction voltage is the threshold voltage Vthn of the NMOS. Therefore, when the NMOS is on, the GVDD voltage is equal to the sum of the threshold voltages of the plurality of NMOS, and when the NMOS is off, the GVDD is almost equal to the VDD.

The principle that the voltage between GVDD and VSS can be clamped in a preset range by the PMOS series connection and the principle that the voltage between GVDD and VSS can be clamped in a preset range by the NMOS series connection can be realized.

Fig. 13 is a block diagram of a clamp circuit in yet another embodiment of the invention.

Referring to fig. 13, the clamp circuit includes a low dropout linear regulator. It can be seen that the difference compared to fig. 9 is that the clamp circuit is a low dropout linear regulator.

The principle that the low dropout linear regulator LDO can clamp the voltage between GVDD and VSS within a preset range is that when the voltage of VDD-VSS is lower, the voltage of VDD-VSS is divided through a resistor R6 and a resistor R7 to output lower voltage VG3, VG3 is lower than the gate opening voltage of an NMOS tube M3, the NMOS tube M3 is closed, VD3 is high, VEN0 is low after passing through a logic control unit I5, the MOS tube M6 is closed, the MOS tube M5 is conducted, and the output GVDD voltage is equal to the VDD voltage. When the voltages VDD to VSS are higher, the voltages VDD to VSS are divided by the resistor R6 and the resistor R7 to output higher voltages VG3, VG3 is higher than the gate turn-on voltage of the NMOS transistor M3, the NMOS transistor M3 is turned on, VD3 is low, VEN0 is high after passing through the logic control unit I5, the MOS transistor M6 is turned on, the MOS transistor M5 is turned off, and since the reference voltage of the positive input voltage of the amplifier is equal to the voltage VR10 of the negative input voltage of the amplifier, and the voltage VR10 is obtained by dividing GVDD by the resistor R9 and the resistor R10, the output voltage is gvdd=reference voltage (r9+r10)/R10.

It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims

1. The single-wafer battery protection circuit for improving the peak voltage resisting capability is characterized by comprising a basic protection circuit, a clamp voltage circuit, a grid substrate control circuit and a charge-discharge control MOS tube;

one ends of a source electrode and a drain electrode of the charge-discharge control MOS tube are connected to a negative end of the battery, and the other ends of the source electrode and the drain electrode of the charge-discharge control MOS tube are connected to a charger negative electrode or a load;

The basic protection circuit detects the charge and discharge conditions of the battery, and sends a control signal to the grid substrate control circuit, so that the grid substrate control circuit controls the conduction conditions of the charge and discharge control MOS tube according to the control signal, and the charge and discharge of the battery are controlled;

The clamp circuit is used for clamping the power supply voltage of the grid substrate control circuit;

The basic protection circuit specifically comprises:

the reference circuit is used for generating a positive input signal VOC1 of the discharge overcurrent comparator, a positive input signal VSHORT of the discharge short-circuit comparator, a negative input signal VCHOC of the charge overcurrent comparator, a negative input signal VODV of the overdischarge voltage comparator, a positive input signal VOCV of the overcharge voltage comparator, and input signals VPN and VOTP of the over-temperature protection circuit;

the over-temperature protection circuit is used for detecting the temperature of the chip integrated by the battery protection circuit during charging and discharging and controlling the transmission of the control signal together with the basic protection circuit;

The delay circuit performs respective corresponding delay based on the output result of the discharging overcurrent comparator, the output result of the discharging short-circuit comparator, the output result of the charging overcurrent comparator, the output result of the overcharging voltage comparator and the output result of the overdischarging voltage comparator, and outputs the second control signal VOC2 and the third control signal VOD2 through logic processing.

2. The single-wafer battery protection circuit for improving the anti-spike voltage capability of claim 1, wherein the gate substrate control circuit comprises a gate control part and a substrate control part, wherein the gate control part is connected with a gate of the charge-discharge control MOS tube, and the substrate control part is connected with a substrate of the charge-discharge control MOS tube;

When the battery is charged and discharged, the grid control part outputs a grid control response signal according to the control signal to control the grid voltage of the charge-discharge control MOS tube, and the substrate control part outputs a substrate control response signal according to the control signal to control the substrate voltage of the charge-discharge control MOS tube so as to control the conduction condition of the charge-discharge control MOS tube.

3. The single-wafer battery protection circuit for improving peak voltage resistance according to claim 1, wherein the voltage divider resistor R5 and the zener diode are included, one end of the voltage divider resistor R5 is connected to the power supply voltage VDD, the other end of the voltage divider resistor R5 is connected to the negative electrode of the zener diode, and the positive electrode of the zener diode is connected to the VSS end.

4. The single-wafer battery protection circuit for improving the anti-spike voltage capability according to claim 1, wherein the voltage divider resistor R5 and N diodes connected in series in one way, wherein N is more than or equal to 1;

5. The single-wafer battery protection circuit for improving the anti-spike voltage capability according to claim 1, wherein the clamp circuit comprises a divider resistor R5 and N NMOS tubes connected in series, wherein N is more than or equal to 1;

6. The single-wafer battery protection circuit for improving the anti-spike voltage capability according to claim 1, wherein the clamp circuit comprises a divider resistor R5 and N PMOS tubes connected in series, wherein N is more than or equal to 1;

7. The single wafer battery protection circuit of claim 1, wherein the clamp circuit comprises a low dropout linear regulator.

8. The single-wafer battery protection circuit according to claim 1, wherein, in the basic protection circuit, when the second control signal VOC2 and the third control signal VOD2 output high levels, the gate substrate control circuit outputs a high-level gate voltage VGATE as a gate control response signal according to the second control signal VOC2 and the third control signal VOD 2;

when at least one of the second control signal VOC2 and the third control signal VOD2 outputs a low level, the gate substrate control circuit outputs a low level gate voltage VGATE as a gate control response signal according to the second control signal VOC2 and the third control signal VOD 2.

9. A battery charging circuit comprising a single wafer battery protection circuit for improving anti-spike voltage capability as claimed in any one of claims 1 to 8, and a charger, battery, RC filter circuit, wherein:

one end of a resistor R0 in the RC filter circuit is connected with a power supply voltage VDD end, and the other end of the resistor R0 is connected with the positive electrode of the battery;

one end of a capacitor C0 in the RC filter circuit is connected with the power supply voltage VDD end, the other end of the capacitor C0 is connected with the negative electrode of the battery, the positive electrode of the charger is connected with the positive electrode of the battery to provide charging voltage for the battery, and the negative electrode of the charger is connected with the negative electrode of the battery through the charging and discharging control MOS tube.

10. A battery discharge circuit comprising a single wafer battery protection circuit for improving anti-spike voltage capability as claimed in any one of claims 1 to 8, and an RC filter circuit, battery, load, wherein:

the positive electrode of the battery is connected with the positive electrode of the load to provide power for the load, and the negative electrode of the load is connected with the negative electrode of the battery through the charge-discharge control MOS tube.