CN109449167B - A display panel and display device - Google Patents

Abstract

Embodiments of the present invention provide a display panel and a display device, which relate to the field of display technology and reduce the load difference of signal lines of different lengths. The display panel includes a picture display area and a non-picture display area. The picture display area includes a first display area and a second display area; the picture display area includes pixels; and the first signal line includes the first signal line in the first display area. A sub-first signal line and a second sub-first signal line in the second display area, the number of pixels connected by the first sub-first signal line is greater than the number of pixels connected by the second sub-first signal line; the display panel includes Capacitance compensation structure, the capacitance compensation structure includes a first conductive layer, a second conductive layer and a third conductive layer; the second conductive layer is located between the first conductive layer and the third conductive layer, and the first conductive layer is connected to the third conductive layer , the first conductive layer overlaps with the second conductive layer, and the second conductive layer overlaps with the third conductive layer; the second sub-first signal line multiplexes the second conductive layer or the third conductive layer.

Description

A display panel and display device

【Technical field】

The present invention relates to the field of display technology, and in particular, to a display panel and a display device.

【Background technique】

With the diversified designs of display panels, special-shaped display panels have been widely used. However, for a special-shaped display panel, since the shape of the display area is irregular, the lengths of the signal lines disposed in the display area are also different. In this way, the number of pixels that need to be driven by a signal line with a shorter length will be less than the number of pixels that need to be driven by a signal line with a longer length, resulting in inconsistent trace loads of different signal lines, which in turn leads to different signal lines. The attenuation of the transmitted signal is different, which adversely affects the display performance of the display panel.

[Content of the invention]

In view of this, embodiments of the present invention provide a display panel and a display device, which are used to reduce the load difference of signal lines of different lengths and improve the display performance of the display panel.

In one aspect, an embodiment of the present invention provides a display panel, the display panel includes a picture display area and a non-picture display area, and the picture display area includes a first display area and a second display area;

The picture display area includes:

multiple pixels;

a plurality of first signal lines, the first signal lines include a first sub-first signal line and a second sub-first signal line, the first sub-first signal line is located in the first display area, the The second sub-first signal line is located in the second display area, wherein the number of pixels electrically connected to the first sub-first signal line is greater than the number of pixels electrically connected to the second sub-first signal line the number of;

The display panel further includes a plurality of capacitance compensation structures, and the capacitance compensation structures include a first conductive layer, a second conductive layer and a third conductive layer; wherein the second conductive layer is located between the first conductive layer and the third conductive layer. Between the third conductive layers, the first conductive layer is electrically connected to the third conductive layer, the first conductive layer overlaps the second conductive layer, and the second conductive layer is connected to the third conductive layer. Three conductive layers overlap;

Wherein, the second sub-first signal line is multiplexed into the second conductive layer or the third conductive layer.

On the other hand, an embodiment of the present invention provides a display device including the above-mentioned display panel.

A technical scheme in the above-mentioned technical scheme has the following beneficial effects:

In the technical solution provided by the embodiment of the present invention, based on the relative positional relationship between the first conductive layer, the second conductive layer and the third conductive layer, the first conductive layer and the second conductive layer are formed between the facing regions The first coupling capacitance is formed, and the second coupling capacitance is formed between the second conductive layer and the opposite area of the third conductive layer. At this time, whether the second sub-first signal line is multiplexed into the second conductive layer or the third conductive layer The conductive layer can both compensate the load capacitance of the second sub-first signal line through the first coupling capacitor and the second coupling capacitor, so as to increase the load capacitance of the second sub-first signal line. Further, when the second sub-first signal line is multiplexed into the third conductive layer, since the first conductive layer is electrically connected to the second sub-first signal line, the second sub-first signal line can also be increased through the first conductive layer. The trace length of the first signal line can compensate the load resistance of the second sub-first signal line, thereby increasing the load resistance of the second sub-first signal line.

It can be seen that, by using the technical solutions provided by the embodiments of the present invention, the load capacitance and load resistance of the second sub-first signal line can be simultaneously increased to a certain extent, or the second sub-first signal line can be increased to a certain extent. The load capacitance of the second sub-first signal line is increased, the load difference between the second sub-first signal line and the first sub-first signal line is reduced, and the load of the second sub-first signal line is reduced. The difference in attenuation of the signals transmitted on a signal line and the first sub-first signal line improves the display uniformity of the first display area and the second display area, and improves the display performance of the display panel.

【Description of drawings】

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a top view of a display panel provided by an embodiment of the present invention;

Fig. 2 is the partial enlarged schematic diagram of Fig. 1;

Fig. 3 is the sectional view of Fig. 1 along A1-A2 direction;

4 is a schematic diagram of the relationship between the film layers of the first conductive layer, the second conductive layer and the third conductive layer provided by an embodiment of the present invention;

5 is a schematic diagram of another film layer relationship of the first conductive layer, the second conductive layer and the third conductive layer provided by an embodiment of the present invention;

6 is a schematic structural diagram of an inorganic layer provided by an embodiment of the present invention;

Fig. 7 is another sectional view of Fig. 1 along the A1-A2 direction;

FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the present invention.

【Detailed ways】

In order to better understand the technical solutions of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. As used in the embodiments of the present invention and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

It should be understood that the term "and/or" used in this document is only an association relationship to describe the associated objects, indicating that there may be three kinds of relationships, for example, A and/or B, which may indicate that A exists alone, and A and B exist at the same time. B, there are three cases of B alone. In addition, the character "/" in this document generally indicates that the related objects are an "or" relationship.

It should be understood that although the terms first and second may be used to describe the display areas in the embodiments of the present invention, these display areas should not be limited by these terms. These terms are only used to distinguish display areas from one another. For example, without departing from the scope of the embodiments of the present invention, the first display area may also be referred to as the second display area, and similarly, the second display area may also be referred to as the first display area.

An embodiment of the present invention provides a display panel. As shown in FIGS. 1 and 2 , FIG. 1 is a top view of the display panel provided by the embodiment of the present invention, and FIG. 2 is a partial enlarged schematic diagram of FIG. 1 . The display panel includes a screen display Area 1 and non-screen display area 2, the screen display area 1 includes a first display area 3 and a second display area 4.

The picture display area 1 includes a plurality of pixels 5 and a plurality of first signal lines 6 . The first signal line 6 includes a first sub-first signal line 7 and a second sub-first signal line 8 , the first sub-first signal line 7 is located in the first display area 3 , and the second sub-first signal line 8 In the second display area 4 , and the number of pixels 5 electrically connected to the first sub-first signal line 7 is greater than the number of pixels 5 electrically connected to the second sub-first signal line 8 .

As shown in FIG. 3 , which is a cross-sectional view along the direction A1-A2 of FIG. 1 , the display panel further includes a plurality of capacitance compensation structures 9 , and the capacitance compensation structures 9 include a first conductive layer 10 , a second conductive layer 11 and a third conductive layer layer 12; wherein, the second conductive layer 11 is located between the first conductive layer 10 and the third conductive layer 12, the first conductive layer 10 and the third conductive layer 12 are electrically connected, and the first conductive layer 10 and the second conductive layer 11 The second conductive layer 11 and the third conductive layer 12 are overlapped; and the second sub-first signal line 8 is multiplexed into the second conductive layer 11 or the third conductive layer 12 .

In the display panel provided by the embodiment of the present invention, based on the relative positional relationship between the first conductive layer 10 , the second conductive layer 11 and the third conductive layer 12 , the positive position of the first conductive layer 10 and the second conductive layer 11 is A first coupling capacitance is formed between the opposite regions, and a second coupling capacitance is formed between the opposite regions of the second conductive layer 11 and the third conductive layer 12. At this time, whether the second sub-first signal line 8 is multiplexed Whether it is the second conductive layer 11 or the third conductive layer 12, the load capacitance of the second sub-first signal line 8 can be compensated by the first coupling capacitor and the second coupling capacitor, so as to realize the compensation of the second sub-first signal line 8 increase of the load capacitance. Further, when the second sub-first signal line 8 is multiplexed into the third conductive layer 12 , since the first conductive layer 10 is electrically connected to the second sub-first signal line 8 , the first conductive layer 10 can also pass through the first conductive layer 10 . The trace length of the second sub-first signal line 8 is increased, thereby compensating for the load resistance of the second sub-first signal line 8 and increasing the load resistance of the second sub-first signal line 8 .

It can be seen that, by using the display panel provided by the embodiment of the present invention, the load capacitance and load resistance of the second sub-first signal line 8 can be simultaneously increased to a certain extent, or the second sub-first signal line 8 can be increased to a certain extent. The load capacitance of the line 8 increases, thereby increasing the trace load of the second sub-first signal line 8, reducing the load difference between the second sub-first signal line 8 and the first sub-first signal line 7, thereby reducing the The attenuation difference of the signals transmitted on the second sub-first signal line 8 and the first sub-first signal line 7 improves the display uniformity of the first display area 3 and the second display area 4, and improves the display panel Display performance.

Optionally, referring to FIG. 3 again, the display panel includes a first substrate 13 and a second substrate 14 disposed opposite to each other, and areas of the first substrate 13 and the second substrate 14 corresponding to the non-screen display area 2 are non-hollowed. In addition, the non-screen display area 2 is a light-transmitting area, and a camera assembly can be correspondingly provided.

It should be noted that the non-hollowed arrangement means that the first substrate 13 and the second substrate 14 are not cut, that is, the display panel is not arranged to have holes in the non-screen display area 2 .

In an existing display panel, in order to set the camera assembly, the display panel is usually cut to form a hole, and the camera assembly is arranged at the hole. However, with this kind of digging design, it is necessary to encapsulate around the digging hole. However, due to the high complexity of the packaging process at the arc edge at the digging hole, the risk of package failure is high. However, in the embodiment of the present invention, by setting the camera assembly corresponding to the non-screen display area 2, and making the areas of the first substrate 13 and the second substrate 14 opposite to the non-screen display area 2 not cut, the normal imaging of the camera assembly is ensured. Under the premise, not only the cutting difficulty of the display panel is reduced, but also it is unnecessary to encapsulate the periphery of the non-screen display area 2, thereby avoiding the risk of encapsulation failure.

Optionally, the first signal line 6 includes a scan line, a data line or a fixed voltage signal line. The scan lines extend in the row direction for providing scan signals to the pixels 5; the data lines extend in the column direction for providing data signals to the pixels 5; the fixed voltage signal lines may specifically include power supply voltage signal lines and reference voltage signal lines , wherein the fixed voltage signal line is used to provide a power supply voltage signal to the pixel 5, and the power supply voltage signal line may specifically include a first power supply voltage signal line extending in the row direction and a second power supply voltage signal line extending in the column direction. The reference voltage The signal lines extend in the row direction for supplying reference voltage signals to the pixels 5 .

When the first signal line 6 includes a scan line, since the number of pixels 5 to be driven by the second sub-first signal line 8 is small and the wiring load is small, the turn-on time of the second sub-first signal line 8 is longer than that of the second sub-first signal line 8 The turn-on time of the first signal line 7 causes the data line to charge the pixels 5 in the second display area 4 more fully, which in turn causes horizontal stripes and abnormal colors in the picture displayed on the display panel. However, in the embodiment of the present invention, by compensating the trace load of the second sub-first signal line 8, the trace load of the second sub-first signal line 8 and the first sub-first signal line 7 can be made to tend to Consistent, further ensuring that the charging states of the data lines to the pixels 5 in the first display area 3 and the second display area 4 are consistent, thereby improving display uniformity.

When the first signal line 6 includes a data line, by compensating for the wiring load of the second sub-first signal line 8, the wiring of the second sub-first signal line 8 and the first sub-first signal line 7 can be The load tends to be consistent, so that the attenuation of the data signals transmitted through the second sub-first signal line 8 and the first sub-first signal line 7 is consistent, thereby improving the problem of different light-emitting brightness caused by different attenuation degrees of the data signals. .

When the first signal line 6 includes a fixed voltage signal line, by compensating for the trace load of the second sub-first signal line 8, the second sub-first signal line 8 and the first sub-first signal line 7 can be The trace loads tend to be consistent, so that the attenuation degree of the fixed voltage signal line during transmission on the second sub-first signal line 8 and the first sub-first signal line 7 tends to be the same, which improves the driving of the pixel 5 by the fixed voltage signal. uniformity.

Optionally, as shown in FIG. 4 , FIG. 4 is a schematic diagram of the relationship between the film layers of the first conductive layer, the second conductive layer, and the third conductive layer provided by the embodiment of the present invention, and the second sub-first signal line 8 is multiplexed. is the third conductive layer 12, and the second sub-first signal line 8 is the scan line. The pixel 5 includes a thin film transistor 16 and a storage capacitor 17 , wherein the storage capacitor 17 includes a first electrode plate 18 and a second electrode plate 19 arranged oppositely; the second conductive layer 11 and the first electrode plate 18 are arranged in the same layer.

With the above arrangement, on the one hand, when the second sub-first signal line 8 is multiplexed into the third conductive layer 12 , the first coupling capacitor and the second coupling capacitor formed by the first conductive layer 10 and the second conductive layer 11 can be used. The second coupling capacitor formed by the conductive layer 11 and the second sub-first signal line 8 performs capacitive load compensation on the second sub-first signal line 8 , and can also be electrically connected to the second sub-first signal line 8 through the first conductive Layer 10 performs load resistance compensation for the second sub-first signal line 8, thereby increasing the trace load of the second sub-first signal line 8 and reducing the second sub-first signal line 8 and the first sub-first signal line 7. On the other hand, the second conductive layer 11 does not need to use an additional patterning process, and can be formed by the same patterning process as the first electrode plate 18, which reduces the process flow and reduces the manufacturing cost; The two conductive layers 11 do not need to occupy additional film layers, and thus will not affect the thickness of the display panel, so that the light and thin design of the display panel can be better achieved.

Optionally, as shown in FIG. 5 , FIG. 5 is a schematic diagram of another film layer relationship of the first conductive layer, the second conductive layer, and the third conductive layer provided by the embodiment of the present invention. The second sub-first signal line 8 is multiplexed into the second conductive layer 11, and the second sub-first signal line 8 is a scan line. The pixel 5 includes a thin film transistor 16 and a storage capacitor 17, wherein the thin film transistor 16 includes an active layer 20, a gate layer 21 and a source and drain layer 22;

With the above arrangement, on the one hand, when the second sub-first signal line 8 is multiplexed into the second conductive layer 11 , the first coupling capacitance and the first coupling capacitance formed by the first conductive layer 10 and the second sub-first signal line 8 can be The second coupling capacitor formed by the second conductive layer 11 and the third conductive layer 12 performs capacitive load compensation on the second sub-first signal line 8, thereby increasing the routing load of the second sub-first signal line 8 and reducing the second sub-first signal line 8. load difference between the sub-first signal line 8 and the first sub-first signal line 7; on the other hand, the third conductive layer 12 does not need to use an additional patterning process, and can be formed by the same patterning process as the active layer 20, reducing The process flow is improved, and the manufacturing cost is reduced; on the other hand, the third conductive layer 12 does not need to occupy an additional film layer, so it does not affect the thickness of the display panel, so that the thin and light design of the display panel can be better realized.

Please refer to FIG. 2 and FIG. 3 again, the second display area 4 is located on both sides of the non-screen display area 2 , and the first conductive layer 10 is disposed in the second display area 4 , and the first conductive layer 10 is located in the second display area 4 . The third conductive layer 12 inside is electrically connected, and the first conductive layer 10 overlaps with the second conductive layer 11 in the second display area 4 .

In this way, on the one hand, whether the second conductive layer 11 or the third conductive layer 12 is the second sub-first signal line 8, each second sub-first signal line 8 corresponds to a first conductive layer 10, which can It is ensured that load compensation is performed on each second sub-first signal line 8, thereby ensuring the display uniformity of the first display area 3 and the second display area 4; on the other hand, the first conductive layer 10 is only provided on the second The display area 4 does not run through the non-screen display area 2. When the non-screen display area 2 is a light-transmitting area and a camera assembly is correspondingly arranged, the influence of the first conductive layer 10 on the light transmittance of the non-screen display area 2 can be avoided. , to improve the imaging quality of the camera assembly.

Further, in order to ensure that the load capacitance of the second sub-first signal line 8 and the load capacitance of the first sub-first signal line 7 tend to be consistent and reduce the load difference between the two, the first coupling capacitance and the second coupling The total capacitance after the capacitors are connected in parallel is equal to the difference in load capacitance between the first sub-first signal line 7 and the second sub-first signal line 8 .

其中，k为静电力常量，ε为相对介质常数，d为电容两个正对极板之间的间距，S为电容两个正对极板之间的交叠面积，可知，第一耦合电容

其中，d₁为第一导电层10和第二导电层11之间的间距，S₁为第一导电层10和第二导电层11之间的交叠面积，第二耦合电容

其中，d₂为第二导电层11与第三导电层12之间的间距，S₂为第二导电层11与第三导电层12之间的交叠面积。Specifically, according to

Among them, k is the electrostatic force constant, ε is the relative dielectric constant, d is the distance between the two positive and opposite polar plates of the capacitor, and S is the overlap area between the two positive and opposite polar plates of the capacitor. It can be known that the first coupling capacitor

Among them, d ₁ is the distance between the first conductive layer 10 and the second conductive layer 11, S ₁ is the overlapping area between the first conductive layer 10 and the second conductive layer 11, and the second coupling capacitance

Wherein, d ₂ is the distance between the second conductive layer 11 and the third conductive layer 12 , and S ₂ is the overlapping area between the second conductive layer 11 and the third conductive layer 12 .

其中，N₁为一条第一子第一信号线7对应的像素5的个数，N₂为一条第二子第一信号线8对应的像素5的个数，c为一个像素5的等效寄生电容。When the number of the second display areas 4 is two, and the number of the pixels 5 electrically connected to the two second sub-first signal lines 8 whose extension lines overlap in the two second display areas 4 are equal, the number of the first sub-first signal lines 8 is equal. The difference in load capacitance between the signal line 7 and the second sub-first signal line 8

Wherein, N ₁ is the number of pixels 5 corresponding to a first sub-first signal line 7 , N ₂ is the number of pixels 5 corresponding to a second sub-first signal line 8 , and c is the equivalent of one pixel 5 parasitic capacitance.

Further, according to C ₁ +C ₂ =ΔC, it is derived that d ₁ , S ₁ , d ₂ , and S ₂ satisfy:

It should be noted that, with reference to FIG. 2 , the extension lines of the two second sub-first signal lines 8 are shown by the dotted lines between the two second sub-first signal lines 8 in FIG. 2 , and the two second display areas 4 The two second sub-first signal lines 8 overlapping the middle extension line specifically refer to two second sub-first signal lines 8 that are electrically connected to the pixels 5 in the same row or column.

Optionally, when the second sub-first signal line 8 is multiplexed into the third conductive layer 12, in order to ensure that the load resistance of the second sub-first signal line 8 and the load resistance of the first sub-first signal line 7 tend to be Consistent, reducing the load difference between the two can make the load resistance of the first conductive layer 10 equal to the load resistance difference between the first sub-first signal line 7 and the second sub-first signal line 8 .

其中，R_s为方块电阻，l为第一导电层10的长度，w为第一导电层10的宽度。第一子第一信号线7和第二子第一信号线8之间的负载电阻差

其中，r为一个像素5的电阻。Specifically, the load resistance of the first conductive layer 10

Wherein, R _s is the sheet resistance, l is the length of the first conductive layer 10 , and w is the width of the first conductive layer 10 . The load resistance difference between the first sub-first signal line 7 and the second sub-first signal line 8

Among them, r is the resistance of one pixel 5 .

Further, according to R=ΔR, it is derived that w and l satisfy:

In addition, when the first conductive layer 10 is only disposed in the second display area 4, since the first conductive layer 10 does not block the non-screen display area 2, the material of the first conductive layer 10 may include light-tight Metal materials can also include transparent conductive materials, such as one or more of indium tin oxide, indium zinc oxide or indium gallium zinc oxide.

Optionally, when the non-screen display area 2 is a light-transmitting area and a camera assembly is correspondingly arranged, in order to further improve the light transmittance of the non-screen display area 2 and further improve the imaging quality of the camera assembly, the display panel also includes: Inorganic layer, the inorganic layer is hollowed out in the non-screen display area 2 . Specifically, as shown in FIG. 6 , which is a schematic structural diagram of an inorganic layer provided by an embodiment of the present invention, the inorganic layer includes a buffer layer 23 disposed on the side of the active layer 20 facing away from the light-emitting surface, and a buffer layer 23 disposed on the active layer The first insulating layer 24 between the gate layer 20 and the gate layer 21 , and the second insulating layer 25 between the gate layer 21 and the source and drain layers 22 .

Optionally, please refer to FIG. 2 again, the second display area 4 is located on both sides of the non-screen display area 2; and, as shown in FIG. 7, FIG. 7 is another cross-sectional view along the direction A1-A2 of FIG. The conductive layer 10 runs through the non-screen display area 2 and the second display area 4, the first conductive layer 10 is electrically connected to the third conductive layer 12 in the second display area 4 on both sides respectively, and the first conductive layer 10 is connected to the two respectively. The second conductive layers 11 in the side second display area 4 overlap.

It should be noted that no matter the second sub-first signal line 8 is multiplexed into the second conductive layer 11 or the third conductive layer 12 , the two second sub-first signals overlapping or electrically connected to the first conductive layer 10 The line 8 is the two second sub-first signal lines 8 overlapping the extension lines.

In this way, a first conductive layer 10 can respectively perform load compensation on the second sub-first signal lines 8 of the second display area 4 on both sides of the non-screen display area 2, so as to reduce the second sub-first signal on both sides at the same time. Load difference between line 8 and the first sub-first signal line 7 .

Further, in order to ensure that the load capacitance of the second sub-first signal line 8 on both sides and the load capacitance of the first sub-first signal line 7 tend to be consistent and reduce the load difference between the two, the first coupling capacitance and The total capacitance of the parallel connection of the second coupling capacitors is equal to the difference in load capacitance between the first sub-first signal line 7 and the two second sub-first signal lines 8 on both sides.

其中，k为静电力常量，ε为相对介质常数，d为电容两个正对极板之间的间距，S为电容两个正对极板之间的交叠面积，可知，第一耦合电容

其中，d₁′为第一导电层10和第二导电层11之间的间距，S₁′为第一导电层10和第二导电层11之间的交叠面积，第二耦合电容

其中，d₂′为第二导电层11与第三导电层12之间的间距，S₂′为第二导电层11与第三导电层12之间的交叠面积。Specifically, according to

Among them, k is the electrostatic force constant, ε is the relative dielectric constant, d is the distance between the two positive and opposite polar plates of the capacitor, and S is the overlap area between the two positive and opposite polar plates of the capacitor. It can be known that the first coupling capacitor

Wherein, d ₁ ′ is the distance between the first conductive layer 10 and the second conductive layer 11 , S ₁ ′ is the overlapping area between the first conductive layer 10 and the second conductive layer 11 , and the second coupling capacitance

Wherein, d ₂ ′ is the distance between the second conductive layer 11 and the third conductive layer 12 , and S ₂ ′ is the overlapping area between the second conductive layer 11 and the third conductive layer 12 .

When the number of the second display areas 4 is two, and the number of pixels 5 electrically connected to the two second sub-first signal lines 8 whose extension lines overlap in the two second display areas 4 are equal, the first sub-first signal Load capacitance difference ΔC′=(N ₁ -2×N ₂ )×c between the two second sub-first signal lines 8 overlapping the line 7 and the extension line, where N ₁ is a first sub-first signal The number of pixels 5 corresponding to line 7 , N ₂ is the number of pixels 5 corresponding to one second sub-first signal line 8 , and c is the equivalent parasitic capacitance of one pixel 5 .

Further, according to C ₁ '+C ₂ '=ΔC', it is derived that d ₁ ', S ₁ ', d ₂ ', S ₂ ' satisfy:

Optionally, when the second sub-first signal line 8 is multiplexed into the third conductive layer 12, in order to ensure that the total load resistance of the two second sub-first signal lines 8 overlapped by the extension lines and the first sub-first signal The load resistance of the line 7 tends to be the same, reducing the load difference between the two, so that the load resistance of the first conductive layer 10 can be made equal to the difference between the first sub-first signal line 7 and the two second sub-first signal lines 8. Poor load resistance.

其中，R_s为方块电阻，l′为第一导电层10的长度，w′为第一导电层10的宽度。第一子第一信号线7和两条第二子第一信号线8之间的负载电阻差ΔR′＝(N₁-2×N₂)×r，其中，r为一个像素5的等效电阻。Specifically, the load resistance of the first conductive layer 10

Wherein, R _s is the sheet resistance, l′ is the length of the first conductive layer 10 , and w′ is the width of the first conductive layer 10 . The load resistance difference between the first sub-first signal line 7 and the two second sub-first signal lines 8 ΔR′=(N ₁ −2×N ₂ )×r, where r is the equivalent of one pixel 5 resistance.

Further, according to R'=ΔR', it is derived that w' and l' satisfy:

In addition, when the first conductive layer 10 runs through the non-screen display area 2, the non-screen display area 2 is a light-transmitting area, and a camera assembly is correspondingly arranged, in order to reduce the light transmittance of the first conductive layer 10 to the non-screen display area 2 In order to improve the imaging quality of the camera assembly, the material of the first conductive layer 10 may include transparent conductive materials, such as one or more of indium tin oxide, indium zinc oxide or indium gallium zinc oxide.

An embodiment of the present invention further provides a display device. As shown in FIG. 8 , FIG. 8 is a schematic structural diagram of the display device provided by the embodiment of the present invention, and the display device includes the above-mentioned display panel 100 . The specific structure of the display panel 100 has been described in detail in the above-mentioned embodiments, and will not be repeated here. Of course, the display device shown in FIG. 8 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book, or a television.

Since the display device provided by the embodiment of the present invention includes the above-mentioned display panel, the display device can compensate the wiring load of the second sub-first signal line 8 to a certain extent and reduce the second sub-first signal The load difference between the line 8 and the first sub-first signal line 7, thereby reducing the attenuation difference of the signal transmitted on the second sub-first signal line 8 and the first sub-first signal line 7, and improving the first display The display uniformity of the area 3 and the second display area 4 improves the display performance of the display device.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (12)

1. A display panel is characterized in that the display panel comprises a picture display area and a non-picture display area, wherein the picture display area comprises a first display area and a second display area;

the screen display area includes:

a plurality of pixels;

a plurality of first signal lines including first sub first signal lines and second sub first signal lines, the first sub first signal lines being positioned in the first display region, the second sub first signal lines being positioned in the second display region, wherein the number of pixels electrically connected to the first sub first signal lines is greater than the number of pixels electrically connected to the second sub first signal lines;

the display panel further comprises a plurality of capacitance compensation structures, wherein each capacitance compensation structure comprises a first conductive layer, a second conductive layer and a third conductive layer; wherein the second conductive layer is located between the first conductive layer and the third conductive layer, the first conductive layer is electrically connected with the third conductive layer, the first conductive layer overlaps with the second conductive layer, and the second conductive layer overlaps with the third conductive layer;

wherein the second sub-first signal line is multiplexed as the second conductive layer or the third conductive layer;

the second display areas are positioned at two sides of the non-picture display area, the number of the second display areas is two, and in the two second display areas, the number of the pixels electrically connected with the two second sub-first signal lines with superposed extension lines is equal;

the first conducting layer is arranged in the second display area, is electrically connected with the third conducting layer in the second display area and is overlapped with the second conducting layer in the second display area;

the second sub-first signal line is multiplexed into the third conductive layer, and the width w of the first conductive layer and the length l of the first conductive layer satisfy:

wherein N is₁The number of the pixels electrically connected to one of the first sub-first signal lines, N₂The number of the pixels electrically connected to one of the second sub-first signal lines, R_sIs a square resistance, r is an equivalent resistance of one of the pixels;

or, the first conducting layer penetrates through the non-picture display area and the second display area, the first conducting layer is respectively and electrically connected with the third conducting layers in the second display areas on two sides, and the first conducting layer is overlapped with the second conducting layers in the second display areas on two sides;

the second sub first signal line is multiplexed into the third conductive layer, and the width w 'of the first conductive layer and the length l' of the first conductive layer satisfy:

2. the display panel according to claim 1, further comprising a first substrate and a second substrate disposed opposite to each other, wherein a region of the first substrate and the second substrate corresponding to the non-image display region is non-hollow.

3. The display panel according to claim 1, wherein the first signal line comprises a scan line, a data line, or a fixed voltage signal line.

4. The display panel according to claim 1, wherein the second sub-first signal lines are multiplexed into the third conductive layer, and the second sub-first signal lines are scan lines;

the pixel comprises a thin film transistor and a storage capacitor, wherein the storage capacitor comprises a first polar plate and a second polar plate which are oppositely arranged;

the second conducting layer and the first polar plate are arranged on the same layer.

5. The display panel according to claim 1, wherein a second sub-first signal line is multiplexed as the second conductive layer, and the second sub-first signal line is a scan line;

the pixel comprises a thin film transistor and a storage capacitor, wherein the thin film transistor comprises an active layer, a gate layer and a source drain layer;

the third conductive layer and the active layer are arranged on the same layer.

6. The display panel according to claim 1, wherein the first conductive layer is provided in the second display region;

an overlapping area S between the first conductive layer and the second conductive layer₁A distance d between the first conductive layer and the second conductive layer₁An overlapping area S between the second conductive layer and the third conductive layer₂A distance d between the second conductive layer and the third conductive layer₂Satisfies the following conditions:

where k is the constant of the electrostatic force, the relative dielectric constant, N₁The number of the pixels electrically connected to one of the first sub-first signal lines, N₂The pixel electrically connected with one of the second sub-first signal linesC is an equivalent parasitic capacitance of one of the pixels.

7. The display panel according to claim 6, wherein a material of the first conductive layer comprises a metal material; or the material of the first conducting layer is one or more of indium tin oxide, indium zinc oxide or indium gallium zinc oxide.

8. The display panel according to claim 1, wherein the display panel further comprises an inorganic layer, and the inorganic layer is hollowed out in the non-picture display region.

9. The display panel according to claim 8, wherein the picture display region is provided with a thin film transistor including an active layer, a gate layer, and a source drain layer;

the inorganic layer comprises a buffer layer arranged on one side of the active layer, which faces away from the light-emitting surface, a first insulating layer arranged between the active layer and the gate layer, and a second insulating layer arranged between the gate layer and the source drain layer.

10. The display panel according to claim 1, wherein the first conductive layer penetrates the non-screen display region and the second display region;

an overlapping area S between the first conductive layer and the second conductive layer₁', a distance d between the first conductive layer and the second conductive layer₁', an overlapping area S between the second conductive layer and the third conductive layer₂', a distance d between the second conductive layer and the third conductive layer₂' satisfies:

where k is the constant of the electrostatic force, the relative dielectric constant, N₁The number of the pixels electrically connected to one of the first sub-first signal lines, N₂C is the equivalent capacitance of one pixel, and c is the number of the pixels electrically connected to one second sub-first signal line.

11. The display panel according to claim 10, wherein a material of the first conductive layer is one or more of indium tin oxide, indium zinc oxide, or indium gallium zinc oxide.

12. A display device comprising the display panel according to any one of claims 1 to 11.

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