CN109417081A

CN109417081A - Chip packaging structure, method and electronic device

Info

Publication number: CN109417081A
Application number: CN201880001868.XA
Authority: CN
Inventors: 吴宝全; 蒋万里
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2018-09-29
Filing date: 2018-09-29
Publication date: 2019-03-01
Anticipated expiration: 2038-09-29
Also published as: CN109417081B; WO2020062140A1; CN112820749A

Abstract

The disclosure relates to the technical field of chip packaging, and discloses a chip packaging structure, a chip packaging method and electronic equipment. The chip packaging structure comprises a substrate, a connector, an image sensing module and an auxiliary module, wherein the image sensing module and the auxiliary module are integrally packaged by utilizing the substrate; the image sensing module comprises an image sensing chip, and the image sensing chip is packaged on the first surface of the substrate; the auxiliary module comprises at least one optical auxiliary chip, and the at least one optical auxiliary chip is packaged on the second surface of the substrate and is electrically connected with the image sensing chip through the substrate; the connector is connected to the substrate and used for electrically connecting the chip packaging structure with an external unit. The embodiment of the disclosure can improve the integration level of the chip packaging module and reduce the total volume of the module.

Description

Chip-packaging structure, method and electronic equipment

Technical field

This disclosure relates to chip encapsulation technology field, and more particularly, to a kind of chip-packaging structure, method and electricity Sub- equipment.

Background technique

Along with the progress of science and technology and stepping up for user demand, the integrated level of electronic equipment is higher and higher. In order to adapt to this development trend, electronic equipment each class component, device used in is also faced with, volume higher to integrated level Smaller, the higher direction transformation of standardization level.

However, important component of the optical finger print chip as the electronic equipment with optical finger print identification function, by The influence of its packaged type, integrated level are limited by very large.Current optical finger print chip generally uses the light of separate type Fingerprint module packaging scheme is learned, image sensing chip, companion chip and the connector of usual such optical finger print mould group stick respectively Be affixed on different substrates, then by flexible circuit board (Flexible Printed Circuit, FPC) by supplementary module, The realizations such as image sensing chip module, connector electrical connection.Such mode integrated level is low, and volume is big, and is difficult to realize standard Change, it is difficult to meet the market demand.

Summary of the invention

For the problems in background technique, present disclose provides a kind of chip-packaging structure, method and electronic equipments, effectively Chip package integrated level is improved, reduces volume, while improving standardization level.

In a first aspect, providing a kind of chip-packaging structure, comprising: substrate, connector, image sensing module and auxiliary mould Block, the image sensing module and the supplementary module carry out integral type encapsulation using the substrate；The image sensing module Including image sensing chip, first surface of the image sensing chip package in the substrate；The supplementary module includes extremely A few optics companion chip, at least one described optics companion chip is encapsulated in the second surface of the substrate, and passes through institute Substrate is stated to be electrically connected with the image sensing chip；The connector connection on the substrate, is used to supply the core Chip package is electrically connected with outside elements.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the connector is connected to the base The first surface or second surface of plate；Specifically, the image sensing chip and at least one described optics companion chip point The main part of the first surface and second surface of the substrate is not set, and the connector is connected to the first of the substrate Surface or the edge part of second surface.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the substrate further includes multiple sides One of side of the substrate is arranged in face, the connector.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the first surface is the substrate Main surface, the second surface is the back side that the substrate and the main surface are away from each other.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the image sensing module further includes The top of the image sensing chip is arranged in lens module, the lens module, for assembling or leading target optical signal Guide to the image sensing chip.

As the disclosure provide chip-packaging structure a kind of optional implementation, the lens module include lens barrel and Be housed in the optical lens of the lens barrel, the image sensing chip includes optical sensor array, the optical lens with it is described Optical sensor array carries out optical path alignment setting.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the lens module further includes filtering Piece, the optical filter are housed in the lens barrel, and between the optical lens and the image sensing chip, the optical filtering Piece prevents it from entering the optical sensor array for external disturbance light to be isolated.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the image sensing module is optics Finger print detecting module, the target optical signal are the fingerprint detection light reflected from finger surface, wherein the fingerprint detection light is logical It crosses the optical lens and assembles or direct into the image sensing chip, the image sensing chip is for detecting the fingerprint Detection light is to carry out optical finger print imaging.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the image sensing chip passes through the One adhesive fits to the first surface of the substrate, and the pad on its surface is connected to the substrate by the first metal wire The contact that is electrically connected of first surface.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the optics companion chip passes through the Two adhesives fit to the second surface of the substrate, and the pad on its surface is connected to the substrate by the second metal wire The contact that is electrically connected of second surface, and connection line and the image sensing core of the optics companion chip by the substrate Piece is electrically connected.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the substrate is with through silicon via Silicon substrate, the image sensing chip are connected to the first surface of the silicon substrate, and the image by the pad of its bottom surface The through silicon via of at least partly pad and the silicon substrate of sensing chip is electrically connected.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the optics companion chip passes through it The pad of bottom surface is connected to the second surface of the silicon substrate, and at least portion of the optics companion chip in a manner of face-down bonding Pad is divided to be electrically connected by the through silicon via and the image sensing chip.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the supplementary module further includes at least One capacitor, at least one described capacitor are connected to the fringe region of the second surface of the substrate by scolding tin.

As a kind of optional implementation for the chip-packaging structure that the disclosure provides, the supplementary module further includes plastic packaging The optics companion chip and at least one described capacitor are sealed in the second surface of the substrate by material, the plastic packaging material, and So that the surfacing of the chip-packaging structure.

Second aspect provides a kind of method of chip package, comprising: provides the substrate for being used for chip package, the base Plate includes first surface and second surface；By image sensing chip package the substrate first surface；By at least one light Learn the second surface that companion chip is encapsulated in the substrate, wherein at least one described optics companion chip passes through the substrate It is electrically connected with the image sensing chip；Attach a connector to the substrate, for the chip-packaging structure with Outside elements are electrically connected.

As a kind of optional implementation for the chip packaging method that the disclosure provides, the connector is connected to the base The first surface or second surface of plate；Specifically, the image sensing chip and at least one described optics companion chip point The main part of the first surface and second surface of the substrate is not set, and the connector is connected to the first of the substrate Surface or the edge part of second surface.

As a kind of optional implementation for the chip packaging method that the disclosure provides, the substrate further includes multiple sides One of side of the substrate is arranged in face, the connector.

As a kind of optional implementation for the chip packaging method that the disclosure provides, the substrate is with through silicon via Silicon substrate, the image sensing chip and the connector are connected to the first of the substrate by same one-time surface attachment process Surface；Alternatively, the connector and at least one described optics companion chip are connected to institute by same one-time surface attachment process State the second surface of substrate.

A kind of optional implementation of chip packaging method as disclosure offer, the method also includes: by camera lens Module fits to the top of the image sensing chip, wherein the lens module includes lens barrel and is housed in the lens barrel Optical lens and optical filter, and the lens module fitting after the optical lens and the image sensing chip optics sense Optical path between array is answered to be aligned.

It is described by image sensing chip package as a kind of optional implementation for the chip packaging method that the disclosure provides It include: that the image sensing chip is fitted into the substrate using first adhesive in the step of first surface of the substrate First surface；Using routing technique and pass through the first metal wire for the pad of the image sensing chip surface and the substrate The electrical connection point of first surface be electrically connected.

It is described to assist at least one optics as a kind of optional implementation for the chip packaging method that the disclosure provides The step of second surface of substrate described in chip package includes: will at least one described optics companion chip using second adhesive Fit to the second surface of the substrate；Using routing technique and pass through the second metal wire at least one optics auxiliary wick by described in The pad on piece surface is electrically connected with the point that is electrically connected of the second surface of the substrate.

As a kind of optional implementation for the chip packaging method that the disclosure provides, the substrate is with through silicon via Silicon substrate, and described by image sensing chip package includes: to be passed by the image in the step of first surface of the substrate The image sensing chip is connected to the first surface of the silicon substrate by the pad of sense chip bottom surface, wherein the image sensing The through silicon via of at least partly pad and the silicon substrate of chip is electrically connected.

It is described to assist at least one optics as a kind of optional implementation for the chip packaging method that the disclosure provides The step of second surface of substrate described in chip package include: by the pad of at least one optics companion chip bottom surface with At least one described optics companion chip is connected to the second surface of the silicon substrate by face-down bonding mode, wherein it is described at least At least partly pad of one optics companion chip is electrically connected by the through silicon via and the image sensing chip.

A kind of optional implementation of chip packaging method as disclosure offer, the method also includes: it will at least One capacitance connection to the substrate second surface fringe region；It will at least one described optics auxiliary wick using plastic packaging material Piece and at least one described capacitor are sealed in the second surface of the substrate, and make the surface of the chip-packaging structure flat It is whole.

As a kind of optional implementation for the chip packaging method that the disclosure provides, at least one described capacitor and described At least one optics companion chip is connected to the second surface of the substrate by same one-time surface attachment process.

The third aspect provides a kind of electronic equipment, the optical finger print including display screen and below the display screen Detection device, the optical finger print detection device include chip-packaging structure as described above.

The embodiment of the present disclosure by the way that image sensing chip and optics companion chip to be individually enclosed in two surfaces of substrate, The integral type encapsulation for realizing the image sensing chip and the optics companion chip, can not only reduce the step of chip package Suddenly, the integrated level of chip package is improved, and reduces the total volume of chip package mould group, while improving the standardization of chip package Degree.

Detailed description of the invention

One or more embodiments are illustrated by the picture in corresponding attached drawing, these exemplary theorys The bright restriction not constituted to embodiment, the element in attached drawing with same reference numbers label are expressed as similar element, remove Non- to have special statement, composition does not limit the figure in attached drawing.

Fig. 1 is the chip-packaging structure schematic diagram according to one embodiment of the disclosure；

Fig. 2 is the flow chart according to the chip packaging method of one embodiment of the disclosure

Fig. 3 to Fig. 9 is the schematic diagram of the manufacture craft of chip-packaging structure shown in FIG. 1；

Figure 10 is chip-packaging structure schematic diagram according to another embodiment of the present disclosure；

Figure 11 is the flow chart of chip packaging method according to another embodiment of the present disclosure.

Specific embodiment

To keep the purposes, technical schemes and advantages of the embodiment of the present disclosure clearer, below in conjunction with attached drawing to the disclosure Each embodiment be explained in detail.However, it will be understood by those skilled in the art that in each embodiment of the disclosure In, many technical details are proposed in order to make reader more fully understand the disclosure.But even if without these technical details and Based on the various changes and modifications of following embodiment, disclosure technical solution claimed also may be implemented.

Fig. 1 is the chip-packaging structure schematic diagram according to one embodiment of the disclosure.As shown in Figure 1, the chip package Structure, comprising: substrate 100, supplementary module 200, image sensing module 300 and connector 400.The image sensing module 300, The supplementary module 200 and the connector 400 realize the high integration encapsulation of integral type by the substrate 100.

Wherein, the substrate 100 includes main surface, the back side being away from each other with the main surface and connect the main surface With multiple sides at the back side, more specifically, the main surface and the back side can for be respectively the substrate 100 upper surface and under Surface.The lower surface of the substrate 100 is arranged in the supplementary module 200；The image sensing module 300 is arranged in the base The upper surface of plate 100, and it is located at the main part of the substrate 100.

The connector 400 is used to be electrically connected for the chip-packaging structure with external unit, can be specific The upper surface or lower surface of the substrate 100 are set, for example, in one embodiment, the connector 400 can be set In the upper surface of the substrate 100, and it is located at the edge part of substrate 100, as shown in Figure 1；Alternatively, in other embodiments In, the edge part in 100 lower surface of substrate also can be set in the connector 400.Alternatively, the connector 400 may be used also To be connected to one of surface of the substrate 100.In other words, in embodiment of the disclosure, the connector 400 Mounting means and installation site are not limited to the structure of Fig. 1；In addition, the specification and outlet method of the connector 400 can be with It is decided according to the actual requirements, the embodiment of the present disclosure does not limit this yet.

In the embodiment of the present disclosure, the substrate 100 can be PCB substrate, have through silicon via (TSV) silicon substrate, ceramic base Plate or organic material substrate etc., upper and lower surfaces can be used to carry out chip package simultaneously.For example, shown in Fig. 1 In embodiment, the image sensing module 300 and the connector 400 are encapsulated in the upper surface of substrate 100, and the auxiliary mould Block 200 is encapsulated in the lower surface of substrate 100.Meanwhile the substrate 100 can also include needed for chip-packaging structure work Functional circuit (or auxiliary circuit) and relevant connection line；Also, 100 surface of substrate also pre-production has multiple Be electrically connected contact, it is described be electrically connected contact for commonly to weld, face-down bonding, narrowband automatic welding or metal lead wire bonding etc. in a manner of It is electrically connected with the supplementary module 200, the image sensing module 300 and the connector 400 etc..The electrical connection Point can also be connected with the connection line inside the substrate 100, to realize the electrically mutual of the chip-packaging structure entirety Even.

The image sensing module 300 can be specially optical finger print detection module, and it may include image sensing core Piece 301 and lens module 302.Wherein, the image sensing chip 301 can be cmos image sensor (CIS) chip, set It sets in the upper surface of substrate 100, and is located at the main part of substrate 100, for example, the image sensing chip 301 can pass through Adhesive 502 is bonded the upper surface for being fixed on substrate 100.

Also, the image sensing chip 301 includes being located therein the optical sensor array in region and being arranged on side The pad 602 of edge.The optical sensor array mainly for detection of via the target optical signal of the lens module 302 to realize Optical imagery, in a particular embodiment, the target optical signal can be excitation light source in the fingerprint inspection that finger reflects and is formed Light is surveyed, the fingerprint detection light is transferred to the optical sensor array of the image sensing chip 301, institute by lens module 302 Stating optical sensor array can detecte the fingerprint detection light to realize that optical finger print is imaged.The pad 602 can pass through gold Belong to the contact that is electrically connected that line 702 is connected to 100 upper surface of substrate, to realize the optical sensor chip 301 and the substrate 100 Electrically interconnection.

The top of the image sensing chip 301 is arranged in the lens module 302, for target optical signal to be assembled or Person directs into the image sensing chip 301；For example, the lens module 302 can be fixed on the shadow by adhesive 503 As the surface of sensing chip 301.In one embodiment, as shown in Figure 1, the lens module 302 can specifically include lens barrel 303, optical lens 304 and optical filter 305；Wherein, the optical lens 304 and the receiving of the optical filter 305 are arranged described The inside of lens barrel 303, and the optical filter 305 is located at it of the optical lens 304 and the image sensing chip 301 Between.The optical lens 304 is mainly used for carrying out optical path convergence or guiding, the optical filter 305 to the target optical signal It can be infrared fileter, the Infrared jamming light or other interference light of external environment are mainly used for isolating, to avoid above-mentioned Interference light interferes the optical imagery of the image sensing chip 301.

In the embodiment shown in fig. 1, the bottom of the lens barrel 303 can be fitted in the image by adhesive 503 The periphery of the optical sensor array of sensing chip 301, and the pad 602 is located at the outside of the lens barrel 303 and convenient for institute State the routing connection of metal wire 702.

The supplementary module 200 includes optics companion chip 201, capacitor 202 and plastic packaging material 203.Wherein, the optics is auxiliary Chip 201 is helped to can be one or more, it can be for for assisting the image sensing module 300 to carry out optical finger print inspection The companion chip of survey or other kinds of optical detection.The optics companion chip 201 can in the lower surface of substrate 100, For example, the optics companion chip 201 can be bonded the lower surface for being fixed on substrate 100 by adhesive 501, and in the light Learn the lower surface that its main surface after companion chip 201 is bonded deviates from the substrate 100.The master of the optics companion chip 201 Surface edge zone is additionally provided with pad 601, and the pad 601 is connected to and 100 lower surface of substrate by metal wire 701 The contact that is electrically connected, and realize by the metal wire 701 connection line of the optics companion chip 201 with the substrate 100 Electrical interconnection.

Depending on the capacitor 202 can have one or more, specific number that can design needs according to actual circuit, set Set in the lower surface of substrate 100, and be located at substrate 100 edge part, for example, the capacitor 202 can by scolding tin 801 with The mode of surface mount (SMT) is weldingly fixed on the lower surface of substrate 100.The scolding tin 801 can be used as electric connection medium, Realize that the capacitor 202 and the contact that is electrically connected of 100 lower surface of substrate are connected.

The plastic packaging material 203 covers the optics companion chip 201 and the capacitor 202, to assist the optics Chip 201 and the capacitor 202 are sealed in the lower surface of the substrate 100, while protecting the optics companion chip 201 and institute State capacitor 202.The plastic packaging material 203 not only may be implemented 100 lower surface of substrate component (including the optics auxiliary Chip 201, the capacitor 202 and described metal wire 701 etc.) sealing, while also providing for subsequent technique higher smooth Degree, wherein the plastic packaging material 203 can be epoxide resin material or organic insulating material etc..

The connector 400 is mainly used for for (such as the control of electronic equipment of the chip-packaging structure and external unit Unit, processing unit or other electric components) it is electrically connected, to realize that the image sensing module 300 and outside are single The communication role of member, to realize finger print identifying or other function.In the embodiment shown in fig. 1, the connector 400 is set It sets in the upper surface of substrate 100, and is located at the edge part of the substrate 100, for example, the connector 400 can pass through weldering Tin 802 is weldingly fixed on the substrate 100 in a manner of surface-pasted, wherein the scolding tin 802 and table on the substrate 100 The contact that is electrically connected in face is connected, and can be used as electric connection medium, realizes the electrical property of the connector 400 and the substrate 100 Interconnection.

In embodiment of the disclosure, described adhesive 501,502,503 can have bonding for glue or glue film etc. Property substance, it is corresponding to be respectively used to fit to optical finger print companion chip 201 and image sensing chip 301 substrate 100 Surface, and lens barrel 303 is fitted in the upper surface of image sensing chip 301 or substrate 100.

In the embodiment shown in fig. 1, the pad 601 of the optics companion chip 201 passes through the metal wire 701 and adopts The contact that is electrically connected of 100 lower surface of substrate is connected to routing technique, thus realize the optics companion chip 201 with it is described The electric connection of substrate 100.Analogously, the pad 602 of the image sensing chip 301 passes through the metal wire 702 and adopts The contact that is electrically connected of 100 upper surface of substrate is connected to routing technique, thus realize the image sensing chip 301 with it is described The electric connection of substrate 100.Wherein, the metal wire 701 and 702 is the electric connection medium of the chip-packaging structure, tool There can be to body the metal of satisfactory electrical conductivity for aluminium, copper, nickel, silver, gold etc..

Wherein, the pad 601 and 602 can be understood as the optics companion chip 201 and the image sensing chip 301 pins being connect with the substrate 100.It should be noted that its of optics companion chip 201 and image sensing chip 301 In a surface previously prepared respectively can have the pad 601 and 602, as shown in Figure 1, optics companion chip 201 and image Another surface of sensing chip 301, to be bonded with the lower surface of the substrate 100 or upper surface.In disclosed implementation In example, such as foregoing description, the capacitor 202 can fit under the substrate 100 using SMT technique and by scolding tin 801 The marginal portion on surface, and be connected by scolding tin 801 with the contact that is electrically connected of the substrate 100, wherein the capacitor 202 at this time It realizes and is electrically connected with the substrate 100.

On the other hand, one or more image sensing cores can be arranged in the image sensing module 300 according to actual needs Piece 301, correspondingly, the image sensing module 300 may include one or more lens modules 302 to cooperate described one Or more image sensing chips 301 carry out optical imagery.Alternatively, the image sensing module 300 uses more image sensing cores When piece 301, wherein at least partial image sensing chip 301 can share a lens module 302.Embodiment shown in Fig. 1 In, the image sensing chip 301 directly fits the upper surface that the substrate 100 is arranged in, alternatively, the image sensing Chip 301 can also be embedded to the upper surface of the substrate 100, specifically, the upper table of the substrate 100 using flush type technique The region that face is used to be arranged the image sensing chip 301 could be formed with groove, and the image sensing chip 301 can be down to Small part is housed in the inside grooves and carries out being bonded fixation with the bottom surface of the groove, is further increased using aforesaid way The integrated level of the chip-packaging structure.

In the embodiment shown in fig. 1, the lens module 302 can fit to the image by adhesive 503 and pass The upper surface of sense chip 301；In other alternate embodiments, lens module 302 can also fit to the upper table of the substrate 100 Face, i.e., the stage of the described lens barrel 303 be connected across the periphery of the image sensing chip 301 and with the image sensing chip 301 The substrate surface in outside carries out fitting fixation.The application to the laminating type of the lens module 302 without specifically limited, as long as energy It is enough that the optical sensor array of the optical lens 304 and the optical filter 305 and the image sensing chip 301 is subjected to optical path Alignment setting.The optical lens 304 and the optical filter 305 can be provided separately, as shown in Figure 1, the optical filter 305 are located at the lower section of the optical lens 304, the optical lens 304 and the optical filter 305 can also be integrated in one It rises, alternatively, the optical filter 305 can also be fitted in the optical sensor array surface of the image sensing chip 301.

In a particular embodiment, the lens module 302 of the image sensing module 300 can be arranged one according to actual needs Piece or multi-disc optical lens 304, the optical lens 304 can be specially lens, such as non-spherical lens.It is real in other substitutions It applies in example, the optical lens 304 can also be replaced using beam path alignment device or other optical path modulation devices, the optical frames First 304 and the optical filter 305 can also directly fit or be integrated into 301 surface of image sensing module or inside, Without the lens barrel 303 is additionally arranged.

Based on chip-packaging structure shown in FIG. 1, the embodiment of the present disclosure also provides a kind of chip packaging method, the chip Packaging method can be used for making chip-packaging structure as shown in Figure 1.Referring to Fig. 2, it is a reality according to the disclosure The flow chart of the chip packaging method of example is applied, to more fully understand chip packaging method that the disclosure provides, extremely below with reference to Fig. 3 Chip packaging method shown in Fig. 2 is described in the schematic diagram of the manufacture craft of chip-packaging structure described in Fig. 9.Its In, Fig. 3 is the schematic diagram for the substrate that the chip packaging method uses；Fig. 4 is that optics companion chip is arranged in substrate following table The schematic diagram in face；Fig. 5 is the schematic diagram that capacitor is fitted to base lower surface；Fig. 6 is to use plastic packaging material by optics companion chip With capacitor plastic packaging base lower surface schematic diagram；Fig. 7 is the schematic diagram that image sensing chip is disposed on the substrate to surface；Figure 8 be schematic diagram lens module being arranged in above image sensing chip；Fig. 9 is the schematic diagram that connector is fitted to substrate.

Specifically, the chip packaging method mainly comprises the steps that

Step S101 provides the substrate for chip package, and processes required circuit in the substrate, and be designed as required Size；

Referring to Fig. 3, the substrate 100 that step S101 is provided can be PCB substrate, the silicon substrate with TSV, ceramic substrate Or organic material is substantially etc., in step s101, the substrate 100 first can be ground to required size, including length Degree, width and thickness etc., then required functional circuit (or auxiliary circuit) and connection line are made by etch process, together When presumptive area on the surface of the substrate 100 make the various contacts that are electrically connected, for the subsequent substrate 100 and core to be packaged Piece or mould group carry out typical connection and prepare.

Optics companion chip is fitted to the lower surface of the substrate by step S102；

It, can be by adhesive 501 by one or multiple optics companion chips 201 referring to Fig. 4, in step s 102 The lower surface of the substrate 100 is fitted in a manner of flip-chip packaged, and uses routing technique by the optics companion chip 201 Pad 601 and the contact that is electrically connected of 100 lower surface of substrate be electrically connected by metal wire 701.

Described adhesive 501 can have the material of adhesiveness for glue or glue film etc., as long as can be by the optics Companion chip 201 fits to the lower surface of the substrate 100.The pad 601 of the optics companion chip 201 is understood that The pin being connect for the optics companion chip 201 with the substrate 100.It should be noted that in the optics companion chip Before 201 are bonded with the substrate 100, the main surface (non-binding face) of the optics companion chip 201 is made in advance The pad 601 is had, therefore, in step s 102, in the case where the optics companion chip 201 is fitted in the substrate 100 After surface, metal routing technique can be directly used by the pad 601 of the optics companion chip 201 and pass through metal wire 701 It is connected to the contact that is electrically connected of the lower surface of the substrate 100.

Capacitor is welded to the lower surface edge region of the substrate by step S103；

Referring to Fig. 5, specifically, in step s 103, the capacitor 202 can be one or more, can use SMT technique and the lower surface edge region that the substrate 100 is welded to by scolding tin 801, wherein the scolding tin 801 is in addition to carrying out Other than being welded and fixed of the capacitor 202 and the substrate 100, the capacitor 202 also is realized as electric connection medium simultaneously With the electric connection of the contact that is electrically connected of 100 lower surface of substrate.

It should be appreciated that there is no stringent tandems by step S102 and step S103 during actual process, namely It is to say, the capacitor 202 can also first be welded to the lower surface edge region of the substrate 100, then carry out the optics again The fitting of companion chip 201 is connected with routing.

The optics companion chip and the capacitor are sealed in the following table of the substrate by plastic packaging material by step S104 Face；

Specifically, referring to Fig. 6, being fixed on the substrate 100 in the optics companion chip 201 and the capacitor 202 It later, can be using plastic packaging material 203 and using plastic package process by the optics companion chip 201 and described in step S104 Capacitor 202 is sealed in the lower surface of the substrate 100 together with the pad 601, the metal wire 701, described scolding tin 801 etc.. The plastic packaging material 203 can be that epoxide resin material or organic insulating material etc. are not only completed after step S104 execution The lower surface sealing of the substrate 100, while also higher flatness is provided for subsequent technique.

Image sensing chip is fitted to the upper surface of the substrate by step S105；

Referring to Fig. 7, in step s105, can use adhesive 502 first and be bonded the image sensing chip 301 To the main part of 100 upper surface of substrate, described adhesive 502 can be equally glue or glue film etc. with adhesiveness Material；Then, being electrically connected the pad 602 of the image sensing chip 301 and 100 upper surface of substrate using routing technique Contact is electrically connected by metal wire 702.

The image sensing chip 301 can be specially the CIS chip with optical sensor array, wherein the pad 602 can fringe region with pre-production on 301 surface of image sensing chip, therefore, in step s105, in the shadow It is fitted in as sensing chip 301 after the upper surface of the substrate 100, metal routing technique can be directly used by the shadow As the pad 602 of sensing chip 301 passes through the contact that is electrically connected that metal wire 702 is connected to the upper surface of the substrate 100.

The top of the image sensing chip is arranged in lens module by step S106；

Referring to Fig. 8, in step s 106, firstly, being arranged optical lens 304 and optical filter 305 inside lens barrel 303 Lens module is formed, wherein the lower section of the optical lens 304 is arranged in the optical filter 305, the optical lens 304 can To include at least a piece of non-spherical lens.Then, the lens module is fitted to by the image sensing core by adhesive 503 The surface of piece 301；Specifically, the bottom of the lens barrel 303 of the lens module can be fitted to and the image sensing core The peripheral surface of the optical sensor array of piece 301, and the bonding position of the lens module needs to guarantee the optical lens 304 and the optical sensor array of the optical filter 305 and the image sensing chip 301 carry out optical path and be directed at setting.

Connector is welded to the substrate, for the electrical property of the chip-packaging structure and external unit by step S107 Connection；

Specifically, referring to Fig. 9, the connector 400 be mainly used for for the chip-packaging structure and external unit it Between electric connection one connectivity port or connection medium are provided, for example the connector 400 can be used to implement the figure As the communication role of sensing chip 301 and external unit, the base can be welded to using SMT technique and by scolding tin 802 The top surface edge portion of plate 100, wherein the scolding tin 802 is solid in addition to the welding for carrying out the connector 400 and the substrate 100 Other than fixed, also while as medium is electrically connected, the contact that is electrically connected of the connector 400 and 100 upper surface of substrate is realized Electric connection.

In disclosure chip packaging method provided by the above embodiment, through the above steps, it can produce such as Fig. 1 Shown in chip-packaging structure.

It should be appreciated that although above-described embodiment is first pasted with the image sensing chip 301 and lens module of image sensing mould group It closes the substrate 100 and carries out being welded and fixed for the connector 400 again later, in for his alternate embodiment, the connection Device 400 can also be first welded to after the substrate 100 carries out the image sensing chip 301 and the fitting of lens module is solid again Fixed, i.e. step S107 can also be executed before step S105.

In addition to this, person of ordinary skill in the field can know, chip package actually provided in this embodiment There is no stringent tandems for most of steps of method, for example, the connector 400 and/or shadow of 100 upper surface of the substrate Fitting installation can also be first carried out as sensing mould group, capacitor 202 and the optics for then carrying out 100 lower surface of substrate again are auxiliary Help the fitting of chip 201.

On the other hand, although the step S107 of chip packaging method provided by the above embodiment is to pass through surface mount process The connector 400 is installed to the upper surface of the substrate 100 where the image sensing chip 301, another real It applies in example, the connector 400 can also be installed to the optics by surface mount or other techniques and the capacitor 202 The lower surface of the substrate 100 where companion chip 201.Alternatively, the connector 400 can also be using independent one attachment Step fits to one of side of the substrate 100, and in this case, the side of the substrate 100 needs system in advance Work has corresponding connecting pin to carry out fitting installation for the connector 400.

Referring to Fig. 10, it is chip-packaging structure schematic diagram according to another embodiment of the present disclosure.Shown in Figure 10 Chip-packaging structure it is similar with chip-packaging structure shown in FIG. 1, the main distinction is, in chip package shown in Fig. 10 The substrate 100 of structure is using the silicon substrate with through silicon via (TSV), to replace the gold of chip-packaging structure shown in FIG. 1 Belong to line 701 and 702.

In chip-packaging structure shown in Fig. 10, the pad of image sensing chip 301 be can be set in bottom, i.e., its with The binding face of 100 upper surface of substrate, and pass through the upper surface that scolding tin 502 is welded to the substrate 100, the image sensing At least partly pad of chip 301 may be coupled to the through silicon via of the substrate 100, and further pass through the through silicon via and institute State substrate 100 connection line or the chip-packaging structure other electricity components (such as optics companion chip 201 or Connector 400 etc.) it is electrically connected.Since the image sensing chip 301 and the connector 400 are welded by scolding tin The upper surface fixed to the substrate 100 is connect, therefore the image sensing chip 301 can be by same with the connector 400 Joining Technology (such as surface mount process) Lai Shixian is welded to the upper surface of the substrate 100 while electrically connect It connects, to reduce processing step.

Similar, the patch in itself and the substrate 100 similarly can be set in the pad of the optics companion chip 201 Conjunction face, and the lower surface of the substrate 100 is welded to by scolding tin 501 using flip-chip bonding process.Also, the optics auxiliary At least partly pad of chip 201 may be coupled to the through silicon via of the substrate 100, and further pass through the through silicon via and institute State the connection line of substrate 100 or other electricity components (such as image sensing chip of the chip-packaging structure 301, the connector 400 and capacitor 201 etc.) it is electrically connected.Due to the optics companion chip 201 and the capacitor 202 be to be welded and fixed by scolding tin and electrically interconnected, therefore the optics companion chip 201 and the capacitor 202 can To realize while be welded to the lower surface of the substrate 100 by a same flip-chip bonding process and be electrically connected, from And reduce processing step.

Based on chip-packaging structure shown in Fig. 10, the disclosure furthermore provides another chip packaging method, Figure 11 It is the flow chart according to the chip packaging method of one embodiment of the disclosure.The chip packaging method can be used for preparing figure Chip-packaging structure shown in 10.The chip packaging method specifically includes:

S201 to circuit needed for processing on substrate, and is designed as required size；

Optics companion chip and capacitor, the lower surface of the substrate is fitted to using SMT technique by S202, and passes through scolding tin It is connected with the contact that is electrically connected of the base lower surface, wherein at least partly pad of the optics companion chip passes through the scolding tin It is connected to the through silicon via of the substrate；

The optics companion chip and the capacitor are sealed in the substrate by plastic packaging material using plastic package process by S203 Lower surface；

Image sensing chip and connector, the upper surface of the substrate is fitted to using SMT technique by S204, and passes through weldering Tin is connected with the contact that is electrically connected of the upper surface of base plate, wherein at least partly pad of the image sensing chip passes through the weldering Tin is connected to the through silicon via of the substrate；

In step S204, the substrate silicon can be passed through between the image sensing chip and the image sensing chip Through-hole, which is realized, to be electrically connected, and in other words, at least one pad of the image sensing chip of the upper surface of base plate passes through described The optics companion chip of through silicon via and the base lower surface is electrically connected.

Lens module is fitted to the top of the image sensing chip, and the lens module by adhesive by S205 Optical lens be directed at setting with the image sensing chip.

In the chip packaging method shown in Figure 11, the image sensing chip and the connector can be by same primary Surface mount process is connected to the upper surface of the substrate；In other alternate embodiments, the connector can also be with institute Optics companion chip is stated by same one-time surface attachment process to be connected to the lower surface of the substrate, to reduce technique step Suddenly.Alternatively, the connector can also be connected to one of side of the substrate using an individual laminating step.

The chip-packaging structure that the above-mentioned each embodiment of the disclosure provides can be adapted for the core of optical finger print detection device Piece encapsulation, especially suitable for having the electronic equipment for shielding lower optical finger print detection device.Specifically, it provides based on the above embodiment Chip-packaging structure, the embodiment of the present disclosure furthermore provides a kind of electronic equipment, the electronic equipment include display screen and Optical finger print detection device below the display screen is set, wherein the optical finger print detection device may include such as with The chip-packaging structure of upper embodiment description.More specifically, the display screen can be OLED display screen or LCD display, When using OLED display screen, the part display pixel that the optical finger print detection device can use the OLED display screen is come Excitation light source as optical finger print detection；And when using LCD display, the optical finger print detection device can configure volume The excitation light source that outer light source detects as optical finger print.

Although present disclosure includes many details, these are not necessarily to be construed as to any invention or claimed The limitation of range, but be interpreted to can be the description of feature specific to the specific embodiment to specific invention.This patent Certain features described in file can also combine realization in a single embodiment in the context of separate embodiments.On the contrary, The various features described in the context of single embodiment can also be implemented separately in various embodiments or with any suitable Sub-portfolio form realize.Although working in certain combinations moreover, feature can be described above as, and even initially It is so claimed, but can be deleted from combination in some cases from claimed combined one or more features It removes, and claimed combination can be related to the deformation of sub-portfolio or sub-portfolio.

Similarly, although describing operation in the accompanying drawings with particular order, this should not be construed as requiring these operations The particular order shown in successively executes in sequence, or require execute it is all shown in operate, to realize desired knot Fruit.Moreover, the various individual system units in the embodiment described in this patent document should not be construed as in all implementations This separation is needed in example.

It will be understood by those skilled in the art that the various embodiments described above are the specific embodiments of realization the application, and In practical applications, can to it, various changes can be made in the form and details, without departing from scope of the present application.

Claims

1. A chip packaging structure, characterized in that it comprises a substrate, a connector, an image sensing module and an auxiliary module, and the image sensing module and the auxiliary module are packaged in one piece using the substrate;

The image sensing module includes an image sensing chip, and the image sensing chip is packaged on the first surface of the substrate;

The auxiliary module includes at least one optical auxiliary chip, the at least one optical auxiliary chip is packaged on the second surface of the substrate, and is electrically connected to the image sensor chip through the substrate;

The connector is connected on the substrate, and is used for electrically connecting the chip package structure with an external unit.

2 . The chip package structure according to claim 1 , wherein the connector is connected to the first surface or the second surface of the substrate. 3 .

3 . The chip package structure according to claim 2 , wherein the image sensor chip and the at least one optical auxiliary chip are respectively disposed on the main body parts of the first surface and the second surface of the substrate, and The connector is connected to an edge portion of the first surface or the second surface of the substrate.

4 . The chip package structure according to claim 1 , wherein the substrate further comprises a plurality of side surfaces, and the connector is disposed on one of the side surfaces of the substrate. 5 .

5 . The chip package structure of claim 1 , wherein the first surface is a main surface of the substrate, and the second surface is a back surface of the substrate away from the main surface. 6 .

6 . The chip packaging structure according to claim 1 , wherein the image sensing module further comprises a lens module, and the lens module is arranged above the image sensing chip and is used for condensing target light signals. 7 . Or lead to the image sensor chip.

7 . The chip package structure according to claim 6 , wherein the lens module comprises a lens barrel and an optical lens accommodated in the lens barrel, the image sensor chip comprises an optical sensing array, and the optical lens The optical path alignment setting is performed with the optical sensing array.

8 . The chip package structure according to claim 7 , wherein the lens module further comprises a filter, and the filter is accommodated in the lens barrel and located between the optical lens and the image sensor. 9 . Between the sensing chips, the optical filter is used to isolate external interference light to prevent it from entering the optical sensing array.

9 . The chip packaging structure according to claim 7 , wherein the image sensing module is an optical fingerprint detection module, and the target light signal is the fingerprint detection light reflected from the finger surface, wherein the fingerprint detection light passes through the The optical lens is converged or guided to the image sensor chip, and the image sensor chip is used for detecting the fingerprint detection light for optical fingerprint imaging.

10 . The chip package structure according to claim 1 , wherein the image sensor chip is attached to the first surface of the substrate through a first adhesive, and the pads on the surface are attached through a first metal. 11 . Wires are connected to electrical connection points on the first surface of the substrate.

11 . The chip package structure according to claim 10 , wherein the optical auxiliary chip is attached to the second surface of the substrate by a second adhesive, and the pads on the surface are connected by a second metal wire. 12 . It is connected to the electrical connection point on the second surface of the substrate, and the optical auxiliary chip is electrically connected to the image sensor chip through the connection lines of the substrate.

12 . The chip package structure according to claim 1 , wherein the substrate is a silicon substrate with through-silicon vias, and the image sensor chip is connected to the first surface of the silicon substrate through a pad on the bottom surface of the image sensor chip. 13 . surface, and at least part of the pads of the image sensor chip are electrically connected to the through-silicon vias of the silicon substrate.

13 . The chip package structure according to claim 12 , wherein the optical auxiliary chip is connected to the second surface of the silicon substrate by flip-chip bonding through the pads on the bottom surface thereof, and the optical auxiliary chip is flip-chip bonded. 14 . At least part of the pads are electrically connected to the image sensor chip through the through silicon vias.

14. The chip package structure according to any one of claims 1 to 13, wherein the auxiliary module further comprises at least one capacitor, and the at least one capacitor is connected to the second surface of the substrate by soldering tin. edge area.

15 . The chip packaging structure according to claim 14 , wherein the auxiliary module further comprises a plastic sealing compound, and the plastic sealing compound seals the optical auxiliary chip and the at least one capacitor on the second side of the substrate. 16 . surface, and make the surface of the chip package structure flat.

16. A chip packaging method, comprising:

providing a substrate for chip packaging, the substrate including a first surface and a second surface;

packaging the image sensor chip on the first surface of the substrate;

encapsulating at least one optical auxiliary chip on the second surface of the substrate, wherein the at least one optical auxiliary chip is electrically connected to the image sensor chip through the substrate;

A connector is connected to the substrate, so that the chip package structure can be electrically connected with external units.

17. The chip packaging method according to claim 16, wherein the connector is connected to the first surface or the second surface of the substrate.

18 . The chip packaging method according to claim 17 , wherein the image sensor chip and the at least one optical auxiliary chip are respectively disposed on the main body parts of the first surface and the second surface of the substrate, and The connector is connected to an edge portion of the first surface or the second surface of the substrate.

19 . The chip packaging method according to claim 16 , wherein the substrate further comprises a plurality of side surfaces, and the connector is disposed on one of the side surfaces of the substrate. 20 .

20 . The chip packaging method according to claim 16 , wherein the substrate is a silicon substrate with through-silicon vias, and the connector and the image sensor chip are connected to the substrate through the same surface mount process. 21 . the first surface of the substrate; or, the connector and the at least one optical auxiliary chip are connected to the second surface of the substrate through the same surface mount process.

21. The chip packaging method according to claim 16, further comprising:

A lens module is attached above the image sensor chip, wherein the lens module includes a lens barrel, an optical lens and a filter housed in the lens barrel, and after the lens module is attached, the optical lens The optical path is aligned between the lens and the optical sensing array of the image sensing chip.

22. The chip packaging method according to claim 16, wherein the step of packaging the image sensor chip on the first surface of the substrate comprises:

Using a first adhesive to attach the image sensor chip to the first surface of the substrate;

The bonding pads on the surface of the image sensor chip and the electrical connection points on the first surface of the substrate are electrically connected through a wire bonding process through first metal wires.

23. The chip packaging method according to claim 22, wherein the step of packaging at least one optical auxiliary chip on the second surface of the substrate comprises:

attaching the at least one optical auxiliary chip to the second surface of the substrate using a second adhesive;

The bonding pads on the surface of the at least one optical auxiliary chip are electrically connected to the electrical connection points on the second surface of the substrate through a wire bonding process and through second metal wires.

24. The chip packaging method according to claim 16, wherein the substrate is a silicon substrate with through silicon vias, and the step of packaging the image sensor chip on the first surface of the substrate comprises:

The image sensor chip is connected to the first surface of the silicon substrate through the pads on the bottom surface of the image sensor chip, wherein at least part of the pads of the image sensor chip and the through silicon vias of the silicon substrate Make electrical connections.

25. The chip packaging method according to claim 24, wherein the step of packaging at least one optical auxiliary chip on the second surface of the substrate comprises:

The at least one optical auxiliary chip is connected to the second surface of the silicon substrate by flip-chip bonding through the pads on the bottom surface of the at least one optical auxiliary chip, wherein at least part of the pads of the at least one optical auxiliary chip pass through The through silicon via is electrically connected with the image sensor chip.

26. The chip packaging method according to any one of claims 16 to 25, further comprising:

connecting at least one capacitor to an edge region of the second surface of the substrate;

The at least one optical auxiliary chip and the at least one capacitor are sealed on the second surface of the substrate by using a plastic sealing compound, and the surface of the chip packaging structure is made flat.

27. The chip packaging method of claim 26, wherein the at least one capacitor and the at least one optical auxiliary chip are connected to the second surface of the substrate through the same surface mount process.

28. An electronic device, comprising a display screen and an optical fingerprint detection device located below the display screen, the optical fingerprint detection device comprising the chip packaging structure according to any one of claims 1 to 15 .