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CN109300975A - A trench-gate bipolar transistor with low electromagnetic interference noise - Google Patents

A trench-gate bipolar transistor with low electromagnetic interference noise Download PDF

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Publication number
CN109300975A
CN109300975A CN201811146778.8A CN201811146778A CN109300975A CN 109300975 A CN109300975 A CN 109300975A CN 201811146778 A CN201811146778 A CN 201811146778A CN 109300975 A CN109300975 A CN 109300975A
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type semiconductor
region
emitter
polysilicon
collector
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CN109300975B (en
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陈万军
许晓锐
王园
刘超
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明属于半导体器件技术领域，具体的说涉及一种具有低电磁干扰噪声特性的槽栅双极型晶体管。本发明的主要方案：一是采用了元胞区与假元胞区在水平方向交替排列的结构，假元胞区与金属化发射极相连，并不浮空；二是在假元胞上表面垂直延伸进器件形成多晶硅二极管结构，从而将P型半导体条与金属化发射极通过浮空欧姆接触与多晶硅二极管结构连接在一起，达到钳位P型半导体条电势的作用。在器件开启时，空穴电流对栅电容的充电作用被极大削弱，从而大大增加器件的栅极控制能力同时降低了器件的电磁干扰噪声。在器件导通时，二极管钳位P型半导体条的电势，抑制其对空穴的抽取作用，增强了器件的电导调制效应，降低了导通压降。

The invention belongs to the technical field of semiconductor devices, and in particular relates to a trench gate bipolar transistor with low electromagnetic interference noise characteristics. The main solutions of the present invention are as follows: firstly, a structure in which the cell area and the pseudo-cell area are alternately arranged in the horizontal direction is adopted, and the pseudo-cell area is connected to the metallized emitter and does not float; second, the upper surface of the pseudo-cell area is used. Vertically extending into the device to form a polysilicon diode structure, so that the P-type semiconductor strip and the metallized emitter are connected to the polysilicon diode structure through floating ohmic contacts to achieve the function of clamping the potential of the P-type semiconductor strip. When the device is turned on, the charging effect of the hole current on the gate capacitance is greatly weakened, thereby greatly increasing the gate control capability of the device and reducing the electromagnetic interference noise of the device. When the device is turned on, the diode clamps the potential of the P-type semiconductor strip, inhibits the extraction of holes, enhances the conductance modulation effect of the device, and reduces the on-voltage drop.

Description

A kind of slot grid bipolar junction transistor with low EMI noise characteristic
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of slot grid with low EMI noise characteristic Bipolar junction transistor (Trench Insulated Gate Bipolar Transisitor, referred to as: TIGBT).
Background technique
High voltage power semiconductor device is the important component of power electronic, and the motor in such as dynamical system drives Dynamic, the fields such as frequency conversion have a wide range of applications in consumer electronics.In the application, high voltage power semiconductor is needed with low-power damage Consumption, high anti-short circuit capability, the characteristics such as low EMI noise.Conventional insulator grid bipolar junction transistor (Insulated Gate Bipolar Transistor, referred to as: IGBT) obtained since it shows superior performance in mesohigh field of power electronics To being widely applied still, IGBT exists between key parameter conduction voltage drop and turn-off power loss as a kind of bipolar device Tradeoff.IGBT with floating vacation cellular improves the power consumption tradeoff of traditional IGBT, and obtains bigger short circuit Safety operation area.But IGBT (Floating-P IGBT) electromagnetic interference noise in opening process with floating vacation cellular It is too big, influence the reliability of device.
Summary of the invention
It is to be solved by this invention, aiming at the above problem, propose that a kind of potential automodulation groove gate type IGBT structure (can Referred to as SRP-IGBT), the electromagnetic interference noise in IGBT opening process is greatly reduced, and further reduced the function of device Rate loss, increases the short-circuit safety operation area of device.
To achieve the above object, the present invention adopts the following technical scheme:
A kind of slot grid bipolar junction transistor, structure are as shown in Figure 1；It is handed in the horizontal direction by false cellular region 1 and cellular region 2 For arranging；The false cellular region 1 includes collector structure, drift region structure and polysilicon diode structure；Described Collector structure includes metallize collector 3 and the P- collector positioned at metallization 3 upper surface of collector；The drift region knot Structure includes the P-type semiconductor item 6 positioned at the N- buffer layer 5 of P- collector upper surface and positioned at 5 upper surface of N- buffer layer；Described Polysilicon diode structure includes oxide layer 11, p-type polysilicon 12, N-type polycrystalline silicon 13, floating Ohmic contact 14, passivation isolation Layer 15 and metallization emitter 17；The oxide layer 11 extends into p-type half along the symmetry axis vertical direction of P-type semiconductor item 6 Groove is formed in conductor bar 6, the side of the oxide layer 11 is only contacted with P-type semiconductor item 6；The p-type polysilicon 12 In groove；The N-type polycrystalline silicon 13 extends into p-type polysilicon 12, institute along the symmetry axis vertical direction of p-type polysilicon 12 The N-type polycrystalline silicon 13 stated is more shallow than the junction depth of p-type polysilicon 12；The floating Ohmic contact 14 and P-type semiconductor item 6, oxidation The upper surface contact of layer 11, p-type polysilicon 12, the floating Ohmic contact 14 are emitted by passivation separation layer 15 and metallization Pole 17 keeps apart；The metallization emitter 17 is located at N-type polycrystalline silicon 13 and is passivated the upper surface of separation layer 15；The member Born of the same parents area 2 includes collector structure, drift region structure, emitter structure and groove structure；The collector structure includes metal Change collector 3 and the P- collector positioned at metallization 3 upper surface of collector；The drift region structure includes being located at P- collector The N- buffer layer 5 of upper surface and N-type semiconductor item 7 positioned at 5 upper surface of N- buffer layer；The emitter structure includes p-type base Area 8, the contact zone P+ 9, N+ emitter region 10 and metallization emitter 17, the emitter structure are located at the upper of N-type semiconductor item 7 Layer, and between two neighboring groove structure；The N+ emitter region 10 is located at the both ends of 2 upper surface of cellular region；The P + contact zone 9 is between two adjacent N+ emitter region 10；The metallization emitter 8 is located at the contact zone P+ 7 and N+ emitter region 6 upper surface；The metal hair emitter 17 is located at the upper surface of the contact zone P+ 9 and N+ emitter region 10；The groove knot Structure includes gate oxide 18 and polysilicon gate 16；The gate oxide 18 extends into N-type semiconductor along the vertical direction of device Groove, the gate oxide side and N+ emitter region 10, p-type base area 8, N-type semiconductor item 6 and P-type semiconductor are formed in item 7 Item 7 contacts；The polysilicon gate 16 is located in groove.It is characterized in that, the SRP-IGBT is alternately arranged by horizontal direction The false cellular region 1 of column and cellular region 2 are constituted；The false cellular region 1 and cellular region 2 is connected to one by the emitter 17 that metallizes It rises；The P-type semiconductor item 6 is connected by floating Ohmic contact 14 with polysilicon diode structure with metallization emitter 17 To together, to reach the clamping action to P-type semiconductor potential.
The total technical solution of the present invention, mainly there is at 3 points, first is that device uses cellular region and false cellular region in level side To alternately arranged structure；Second is that false cellular region is connected with the emitter that metallizes, not floating；Third is that P-type semiconductor item and gold Categoryization emitter has been connected in together by floating Ohmic contact with polysilicon diode structure.
Beneficial effects of the present invention are, by proposing new construction slot grid bipolar junction transistor (SRP-IGBT), not change Under the premise of device parameters, greatly reduce device open when electromagnetic noise interference, while reduce device power loss, Increase the short-circuit safety operation area of device.
Detailed description of the invention
Fig. 1 is SRP-IGBT structural schematic diagram of the invention；
Fig. 2 is the IGBT structure schematic diagram with floating vacation cellular；
Fig. 3 is the figure compared with the threshold voltage of SRP-IGBT provided by the invention of the IGBT with floating vacation cellular；
Fig. 4 is the figure compared with the breakdown voltage of SRP-IGBT provided by the invention of the IGBT with floating vacation cellular；
Fig. 5 is the electromagnetic interference noise and unlatching function of IGBT and SRP-IGBT provided by the invention with floating vacation cellular The tradeoff of consumption compares figure；
Fig. 6 is the figure compared with the power consumption tradeoff of SRP-IGBT provided by the invention of the IGBT with floating vacation cellular；
Fig. 7 is the figure compared with the short circuit curve of SRP-IGBT provided by the invention of the IGBT with floating vacation cellular；
Specific embodiment
With reference to the accompanying drawing, the technical schemes of the invention are described in detail:
A kind of novel cell grid bipolar junction transistor proposed by the present invention, structural schematic diagram such as Fig. 1 greatly reduce IGBT's Electromagnetic noise interference is opened, while reducing the power loss of IGBT, increasing the short-circuit safety operation area of IGBT.Of the invention Major programme is to use the alternately arranged cellular region of horizontal direction and false cellular region, and cellular region and false cellular region pass through metallization Emitter is connected, and makes false cellular region not floating；Secondly P-type semiconductor item and metallization emitter pass through floating Ohmic contact and more Crystal silicon diode structure connects together, by the potential clamper of P-type semiconductor item.
A kind of slot grid bipolar junction transistor, structure are as shown in Figure 1；It is handed in the horizontal direction by false cellular region 1 and cellular region 2 For arranging；The false cellular region 1 includes collector structure, drift region structure and polysilicon diode structure；Described Collector structure includes metallize collector 3 and the P- collector positioned at metallization 3 upper surface of collector；The drift region knot Structure includes the P-type semiconductor item 6 positioned at the N- buffer layer 5 of P- collector upper surface and positioned at 5 upper surface of N- buffer layer；Described Polysilicon diode structure includes oxide layer 11, p-type polysilicon 12, N-type polycrystalline silicon 13, floating Ohmic contact 14, passivation isolation Layer 15 and metallization emitter 17；The oxide layer 11 extends into p-type half along the symmetry axis vertical direction of P-type semiconductor item 6 Groove is formed in conductor bar 6, the side of the oxide layer 11 is only contacted with P-type semiconductor item 6；The p-type polysilicon 12 In groove；The N-type polycrystalline silicon 13 extends into p-type polysilicon 12, institute along the symmetry axis vertical direction of p-type polysilicon 12 The N-type polycrystalline silicon 13 stated is more shallow than the junction depth of p-type polysilicon 12；The floating Ohmic contact 14 and P-type semiconductor item 6, oxidation The upper surface contact of layer 11, p-type polysilicon 12, the floating Ohmic contact 14 are emitted by passivation separation layer 15 and metallization Pole keeps apart；The metallization emitter 17 is located at N-type polycrystalline silicon 13 and is passivated the upper surface of separation layer 15；The cellular Area 2 includes collector structure, drift region structure, emitter structure and groove structure；The collector structure includes metallization Collector 3 and positioned at metallization 3 upper surface of collector P- collector；The drift region structure includes being located on P- collector The N- buffer layer 5 on surface and N-type semiconductor item 7 positioned at 5 upper surface of N- buffer layer；The emitter structure includes p-type base area 8, the contact zone P+ 9, N+ emitter region 10 and metallization emitter 17, the emitter structure are located at the upper of N-type semiconductor item 7 Layer, and between two neighboring groove structure；The N+ emitter region 10 is located at the both ends of 2 upper surface of cellular region；The P + contact zone 9 is between two adjacent N+ emitter region 10；The metallization emitter 8 is located at the contact zone P+ 7 and N+ emitter region 6 upper surface；The metal hair emitter 17 is located at the upper surface of the contact zone P+ 9 and N+ emitter region 10；The groove knot Structure includes gate oxide 18 and polysilicon gate 16；The gate oxide 18 extends into N-type semiconductor along the vertical direction of device Groove, the gate oxide side and N+ emitter region 10, p-type base area 8, N-type semiconductor item 6 and P-type semiconductor are formed in item 7 Item 7 contacts；The polysilicon gate 16 is located in groove.It is characterized in that, the SRP-IGBT is alternately arranged by horizontal direction The false cellular region 1 of column and cellular region 2 are constituted；The false cellular region 1 and cellular region 2 is connected to one by the emitter 17 that metallizes It rises；The P-type semiconductor item 6 is connected by floating Ohmic contact 14 with polysilicon diode structure with metallization emitter 17 To together, to reach the clamping action to P-type semiconductor potential.
Working principle of the present invention: adding positive voltage on the metallization collector 11 of the IGBT, on metallization emitter 8 Add no-voltage, IGBT works in blocking state.At this point, the grid to IGBT adds voltage, IGBT gradually switchs to from blocking state Open state.It is opened initial stage in IGBT, laterally consumption occurs for the P-type semiconductor item of the N-type semiconductor item of cellular region and false cellular region To the greatest extent, so that the potential of P-type semiconductor item is lower than N-type semiconductor item.At this point, can be along from the hole displacement current that collector survey comes P-type semiconductor item flows to emitter side, then flows out device by polysilicon diode, it is suppressed that product of the hole near grid It is tired.Meanwhile the presence of polysilicon diode occupies most of region of false cellular emitter side, equally inhibits hole in grid Accumulation near extremely.Since the displacement current that the accumulation of this partial holes generates can charge to gate capacitance, opened to weaken IGBT Grid control ability when opening increases electromagnetic interference noise.And SRP-IGBT reduces charging of the displacement current to gate capacitance Effect, to enhance grid control ability when device is opened, reduce electromagnetic interference noise.
Under SRP-IGBT is in the conductive state, diode there are the potentials of clamper P-type semiconductor item, it is suppressed that P Extraction of the type semiconductor bar to hole, enhances the conductivity modulation effect of device, reduces conduction voltage drop.Meanwhile SRP-IGBT It, rapidly will be superfluous when off since having lateral depletion occurs for the N-type semiconductor item of cellular region and the P-type semiconductor item of false cellular region Carrier extracts device out, greatly reduces the turn-off time.So SRP-IGBT has extremely low power loss.
When SRP-IGBT is under short-circuit condition, since the potential of P-type semiconductor item is by polysilicon diode clamper, Hole current of a part from collector side exports device by polysilicon diode, to reduce the sky for flowing through the base area P- Cave electric current.And the hole current that ought flow through the base area P- is sufficiently large, can trigger the unlatching of IGBT parasitic thyristor, so that device loses Effect.For SRP-IGBT, less hole, which flows through the base area P-, greatly to inhibit the unlatching of parasitic thyristor, to increase The short-circuit safety operation area of SRP-IGBT.
It is emulated to SRP-IGBT provided by the invention and with floating vacation cellular IGBT (Floating-P IGBT) structure Comparison, further demonstrates the superiority of this structure.Fig. 3 and Fig. 4 gives the threshold value of SRP-IGBT and Floating-P IGBT The comparison of voltage and voltage endurance.In order to guarantee fair compare, it is necessary to assure SRP-IGBT and Floating-P IGBT is consistent Blocking ability and threshold voltage；Fig. 5 gives SRP-IGBT and Floating-P IGBT and opens power consumption and electromagnetic interference noise (Maxmum dVKA/dt).From fig. 5, it can be seen that (the E under identical unlatching power consumptionon), the Maxmum dV of SRP-IGBTKA/dt It is reduced to 2.82kV/ μ s from 12.86kV/ μ s, realizes 78% reduction amount, the electromagnetic interference for greatly inhibiting IGBT to open is made an uproar Sound.
Fig. 6 gives the conduction voltage drop (V of SRP-IGBT and Floating-P IGBTon) and turn-off power loss (Eoff) compromise pass It is curve.There is figure it is found that SRP-IGBT possesses the compromise curve of more optimal conduction voltage drop and turn-off power loss.In identical shutdown Under loss, the conduction voltage drop of the conduction voltage drop ratio C-IGBT of SRP-IGBT low 35%.
Fig. 7 gives the short circuit curve correlation curve of SRP-IGBT and Floating-P IGBT.There is figure it is found that SRP- IGBT fails after 10.4 μ s short-circuit impacts, and Floating-P IGBT fails after 7.6 μ s short-circuit impacts.SRP- The duration of short-circuit ratio Floating-P IGBT's of IGBT is long by 37%.
By to IGBT key parameter: the comparison of electromagnetic interference noise, power loss and anti-short circuit capability is intuitively opened up It is opposite excellent using upper performance in mesohigh power semiconductor with Floating-P IGBT structure to show structure of the invention Gesture.

Claims (6)

1.一种具有低电磁干扰噪声特性的槽栅双极型晶体管，其特征在于，沿横向方向，器件由假元胞区(1)和元胞区(2)交替排列而成；1. A trench gate bipolar transistor with low electromagnetic interference noise characteristics, characterized in that, along the lateral direction, the device is alternately arranged by a pseudo cell region (1) and a cell region (2); 所述的假元胞区(1)包括集电极结构、漂移区结构和多晶硅二极管结构；所述的集电极结构包括金属化集电极(3)和位于金属化集电极(3)上表面的P-集电极(4)；所述的漂移区结构包括位于P-集电极(4)上表面的N-缓冲层(5)、位于N-缓冲层(5)上表面的P型半导体条(6)；所述的多晶硅二极管结构包括氧化层(11)、P型多晶硅(12)、N型多晶硅(13)、浮空欧姆接触(14)、钝化隔离层(15)和金属化发射极(17)；所述的氧化层(11)沿P型半导体条(6)的对称轴垂直方向延伸入P型半导体条(6)中形成沟槽，所述的氧化层(11)的侧面仅与P型半导体条(6)接触；所述的P型多晶硅(12)位于沟槽中；所述的N型多晶硅(13)沿P型多晶硅(12)的对称轴垂直方向延伸入P型多晶硅(12)，所述的N型多晶硅(13)的结深比P型多晶硅(12)的结深浅；所述的浮空欧姆接触(14)与P型半导体条(6)、氧化层(11)、P型多晶硅(12)的上表面接触，所述的金属化发射极(17)位于N型多晶硅(13)与钝化隔离层(15)的上表面，所述的浮空欧姆接触(14)通过钝化隔离层(15)与金属化发射极(17)隔离开；The pseudo cell region (1) includes a collector structure, a drift region structure and a polysilicon diode structure; the collector structure includes a metallized collector (3) and a P on the upper surface of the metallized collector (3). - collector (4); the drift zone structure includes an N-buffer layer (5) on the upper surface of the P-collector (4), and a P-type semiconductor strip (6) on the upper surface of the N-buffer layer (5) ); the polysilicon diode structure includes an oxide layer (11), P-type polysilicon (12), N-type polysilicon (13), a floating ohmic contact (14), a passivation isolation layer (15) and a metallized emitter ( 17); the oxide layer (11) extends into the P-type semiconductor strip (6) along the vertical direction of the symmetry axis of the P-type semiconductor strip (6) to form a trench, and the side surface of the oxide layer (11) is only aligned with the P-type semiconductor strip (6). The P-type semiconductor strips (6) are in contact; the P-type polysilicon (12) is located in the trench; the N-type polysilicon (13) extends into the P-type polysilicon (13) along the vertical direction of the symmetry axis of the P-type polysilicon (12). 12), the junction depth of the N-type polysilicon (13) is shallower than that of the P-type polysilicon (12); the floating ohmic contact (14) is connected to the P-type semiconductor strip (6), the oxide layer (11) , the upper surface of the P-type polysilicon (12) is in contact, the metallized emitter (17) is located on the upper surface of the N-type polysilicon (13) and the passivation isolation layer (15), and the floating ohmic contact (14) ) is isolated from the metallized emitter (17) by a passivation isolation layer (15); 所述的元胞区(2)包括集电极结构、漂移区结构、发射极结构和沟槽结构；所述的集电极结构包括金属化集电极(3)和位于金属化集电极(3)上表面的P-集电极(4)；所述的漂移区结构包括位于P-集电极(4)上表面的N-缓冲层(5)和位于N-缓冲层(5)上表面的N型半导体条(7)；所述发射极结构包括P型基区(8)、P+接触区(9)、N+发射区(10)和金属化发射极(17)，所述的发射极结构位于N型半导体条(7)的上层，且位于相邻两个沟槽结构之间；所述的N+发射区(10)位于元胞区(2)上表面的两端；所述的P+接触区(9)位于两个相邻的N+发射区(10)之间；所述金属化发射极(17)位于P+接触区(7)和N+发射区(6)的上表面；所述的金属发发射极(7)位于P+接触区(9)和N+发射区(10)的上表面；所述的沟槽结构包括栅氧化层(18)和多晶硅栅(16)；所述的栅氧化层(18)沿器件的垂直方向延伸入N型半导体条(7)中形成沟槽，所述的栅氧化层侧面与N+发射区(10)、P型基区(8)，N型半导体条(6)和P型半导体条(7)接触；所述的多晶硅栅(16)位于沟槽中。The cell region (2) includes a collector structure, a drift region structure, an emitter structure and a trench structure; the collector structure includes a metallized collector (3) and a metallized collector (3) located on the metallized collector (3). P-collector (4) on the surface; the drift zone structure includes an N-buffer layer (5) on the upper surface of the P-collector (4) and an N-type semiconductor on the upper surface of the N-buffer layer (5) Strip (7); the emitter structure comprises a P-type base region (8), a P+ contact region (9), an N+ emitter region (10) and a metallized emitter (17), the emitter structure being located in the N-type The upper layer of the semiconductor strip (7) is located between two adjacent trench structures; the N+ emission region (10) is located at both ends of the upper surface of the cell region (2); the P+ contact region (9) ) is located between two adjacent N+ emitter regions (10); the metallized emitter electrode (17) is located on the upper surface of the P+ contact region (7) and the N+ emitter region (6); the metallized emitter electrode (7) on the upper surfaces of the P+ contact region (9) and the N+ emitter region (10); the trench structure includes a gate oxide layer (18) and a polysilicon gate (16); the gate oxide layer (18) A trench is formed extending into the N-type semiconductor strip (7) along the vertical direction of the device, and the side of the gate oxide layer is connected to the N+ emitter region (10), the P-type base region (8), the N-type semiconductor strip (6) and The P-type semiconductor strips (7) are in contact; the polysilicon gates (16) are located in the trenches. 2.根据权利要求1所述的一种低具有低电磁干扰噪声的槽栅双极型晶体管，其特征在于：2. a kind of low trench gate bipolar transistor with low electromagnetic interference noise according to claim 1, is characterized in that: 所述的假元胞区(1)和元胞区(2)通过金属化发射极连接到一起，使假元胞不浮空。The dummy cell region (1) and the cell region (2) are connected together through a metallized emitter, so that the dummy cell does not float. 3.根据权利要求1所述的一种低具有低电磁干扰噪声的槽栅双极型晶体管，其特征在于：3. a kind of low trench gate bipolar transistor with low electromagnetic interference noise according to claim 1, is characterized in that: 所述的多晶硅二极管是制作在一个垂直插入假元胞区上表面的沟槽结构。The polysilicon diode is a trench structure fabricated on the upper surface of a vertically inserted dummy cell region. 4.根据权利要求1所述的一种低具有低电磁干扰噪声的槽栅双极型晶体管，其特征在于：4. a kind of low trench gate bipolar transistor with low electromagnetic interference noise according to claim 1, is characterized in that: 所述的多晶硅二极管通过嵌入假元胞区顶部以消除该区域对空穴的收集能力，从而降低器件开启过程中空穴位移电流对栅电容的充电效应，降低电磁干扰噪声。The polysilicon diode is embedded at the top of the dummy cell region to eliminate the hole collecting ability of the region, thereby reducing the charging effect of the hole displacement current on the gate capacitance during the device opening process and reducing electromagnetic interference noise. 5.根据权利要求1所述的一种低具有低电磁干扰噪声的槽栅双极型晶体管，其特征在于：5. a kind of low trench gate bipolar transistor with low electromagnetic interference noise according to claim 1, is characterized in that: 所述的多晶硅二极管钳位了P型半导体条的电势，使得器件工作在开启状态和短路状态下时大部分空穴电流被多晶硅二极管导走。The polysilicon diode clamps the potential of the P-type semiconductor strip, so that most of the hole current is conducted away by the polysilicon diode when the device works in the open state and the short-circuit state. 6.根据权利要求1所述的一种低具有低电磁干扰噪声的槽栅双极型晶体管，其特征在于：6. a kind of low trench gate bipolar transistor with low electromagnetic interference noise according to claim 1, is characterized in that: 所述的假元胞区(1)和元胞区(2)的漂移区，全部由P型半导体条和N型半导体条在水平方向交替排列组成；或者，上半部分是P型半导体条和N型半导体条交替排列，下半部分是低掺杂的N型半导体混合组成。The drift regions of the dummy cell region (1) and the cell region (2) are all composed of P-type semiconductor strips and N-type semiconductor strips arranged alternately in the horizontal direction; or, the upper half is composed of P-type semiconductor strips and The N-type semiconductor strips are arranged alternately, and the lower half is composed of a mixture of low-doped N-type semiconductors.
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