CN109300915A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN109300915A CN109300915A CN201811155818.5A CN201811155818A CN109300915A CN 109300915 A CN109300915 A CN 109300915A CN 201811155818 A CN201811155818 A CN 201811155818A CN 109300915 A CN109300915 A CN 109300915A
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- 239000000758 substrate Substances 0.000 title claims abstract description 125
- 239000010409 thin film Substances 0.000 claims abstract description 65
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 24
- 239000001257 hydrogen Substances 0.000 claims description 24
- 229910052739 hydrogen Inorganic materials 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 abstract description 75
- 239000010410 layer Substances 0.000 description 267
- 238000010586 diagram Methods 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明提供了一种阵列基板、显示面板和显示装置，包括衬底以及位于衬底上的第一薄膜晶体管和第二薄膜晶体管，第一薄膜晶体管和第二薄膜晶体管的有源层材料不同；第一薄膜晶体管包括第一有源层、第一栅极、第一源极和第一漏极，第一有源层为低温多晶硅层；第二薄膜晶体管包括第二有源层、第二栅极、第二源极和第二漏极；第一源极、第一漏极、第二源极和第二漏极位于同一层；第一有源层和第一栅极之间具有第一栅极绝缘层，第二有源层位于第一栅极绝缘层远离衬底的一侧或者靠近衬底的一侧，但第二有源层与第一栅极绝缘层不直接接触，从而不仅可以减少阵列基板上的膜层，而且可以避免第一薄膜晶体管中的第一栅极绝缘层影响第二薄膜晶体管的性能。
The invention provides an array substrate, a display panel and a display device, comprising a substrate, a first thin film transistor and a second thin film transistor on the substrate, and the active layer materials of the first thin film transistor and the second thin film transistor are different; The first thin film transistor includes a first active layer, a first gate, a first source and a first drain, and the first active layer is a low temperature polysilicon layer; the second thin film transistor includes a second active layer, a second gate electrode, the second source electrode and the second drain electrode; the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are located in the same layer; the first active layer and the first gate electrode have a first The gate insulating layer, the second active layer is located on the side of the first gate insulating layer away from the substrate or on the side close to the substrate, but the second active layer is not in direct contact with the first gate insulating layer, so not only The film layers on the array substrate can be reduced, and the first gate insulating layer in the first thin film transistor can be prevented from affecting the performance of the second thin film transistor.
Description
Technical field
The present invention relates to field of display technology, fill more specifically to a kind of array substrate, display panel and display
It sets.
Background technique
Array substrate is generally divided into display area and surrounds the non-display area of display area.In non-display area, use
Low-temperature polysilicon film transistor (Low Temperature Poly-silicon-Thin Film Transistor, LTPS
TFT), the integrated of narrow frame and sensor circuit may be implemented；In display area, due to oxide thin film transistor (Oxide
Thin Film Transistor, Oxide TFT) there is lesser leakage current, it is thereby achieved that pixel low frequency driving, with
Reduce power consumption.
But shared due to low-temperature polysilicon film transistor in existing array substrate and oxide thin film transistor
Film layer is less, and therefore, it is necessary to increase more metal layer and insulating layer, this is resulted in, and the film layer in array substrate is more, makes
Process is cumbersome.And in order to reduce the film layer of array substrate, it needs the part film layer and oxygen of low-temperature polysilicon film transistor
The part film layer same layer of compound thin film transistor (TFT) is arranged, and still, this will lead to the part film layer of low-temperature polysilicon film transistor
The performance for influencing oxide thin film transistor, is unfavorable for the practical application of array substrate.
Summary of the invention
In view of this, the present invention provides a kind of array substrate, display panel and display device, to reduce array substrate
Film layer simplifies production process.
To achieve the above object, the invention provides the following technical scheme:
A kind of array substrate, first film transistor and the second film crystal including substrate and on the substrate
The active layer material of pipe, the first film transistor and second thin film transistor (TFT) is different；
The first film transistor includes the first active layer, first grid, the first source being sequentially located on the substrate
Pole and the first drain electrode, first active layer are low-temperature polycrystalline silicon layer；Second thin film transistor (TFT) is described including being sequentially located at
The second active layer, second grid, the second source electrode and the second drain electrode on substrate；
First source electrode, the first drain electrode, the second source electrode and the second drain electrode are located on the same floor；
There is first grid insulating layer, second active layer is located between first active layer and the first grid
The side of the first grid insulating layer far from the substrate, alternatively, second active layer is located at first grid insulation
Layer is close to the side of the substrate, but second active layer is not directly contacted with the first grid insulating layer.
Optionally, second active layer is oxide semiconductor layer.
Optionally, the first grid insulating layer has hollowed out area, the throwing of second active layer over the substrate
Shadow is located in the projection of the hollowed out area over the substrate.
Optionally, at least there is first buffer layer between second active layer and the first grid insulating layer, it is described
The hydrogen content of first buffer layer is less than the hydrogen content of the first grid insulating layer.
Optionally, also there is second buffer layer between the first buffer layer and the first grid insulating layer；
The hydrogen content of the second buffer layer is greater than the hydrogen content of the first buffer layer.
Optionally, the first buffer layer is silicon dioxide layer, and the hydrogen content of the silicon dioxide layer is greater than 0, is less than
1%.
Optionally, the second buffer layer is silicon nitride layer, and the hydrogen content of the silicon nitride layer is greater than 1%, less than 20%.
Optionally, second active layer is located at the side of the first grid insulating layer far from the substrate, and described
Second active layer is located on the same floor with the first grid.
Optionally, second active layer is located at the side of the first grid insulating layer far from the substrate, and described
Second active layer is between the first grid and the second grid.
Optionally, second thin film transistor (TFT) further includes third grid, the third grid and the first grid position
In same layer.
Optionally, the first film transistor further includes first capacitor, and the first capacitor includes first electrode and
Two electrodes, the first electrode are multiplexed the first grid, and the second electrode is located on the same floor with second active layer.
Optionally, second active layer is located at the first grid insulating layer close to the side of the substrate, and described
Second active layer is located on the same floor with first active layer.
A kind of display panel, including as above described in any item array substrates.
A kind of display device, including display panel as described above.
Compared with prior art, the technical scheme provided by the invention has the following advantages:
Array substrate, display panel and display device provided by the present invention, the first source electrode, the first drain electrode and the second source
Pole, the second drain electrode are located on the same floor, and the second active layer is located at side of the first grid insulating layer far from substrate, alternatively, second
Close to the side of substrate, therefore active layer is located at first grid insulating layer, it is possible to reduce film layer, simplified production in array substrate
Process；Also, since the second active layer and first grid insulating layer are not directly contacted with, it can thus be avoided the first film crystal
First grid insulating layer in pipe influences the performance of the second thin film transistor (TFT), is conducive to be integrated with low-temperature polysilicon film transistor
With the practical application of the array substrate of oxide thin film transistor.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of existing the schematic diagram of the section structure of array substrate；
Fig. 2 is a kind of existing the schematic diagram of the section structure of array substrate；
Fig. 3 is a kind of overlooking structure diagram of array substrate provided in an embodiment of the present invention；
Fig. 4 is a kind of the schematic diagram of the section structure of the array substrate shown in Fig. 3 along cutting line BB '；
Fig. 5 is another the schematic diagram of the section structure of array substrate provided in an embodiment of the present invention；
Fig. 6 is another the schematic diagram of the section structure of array substrate provided in an embodiment of the present invention；
Fig. 7 is another the schematic diagram of the section structure of array substrate provided in an embodiment of the present invention；
Fig. 8 is another the schematic diagram of the section structure of array substrate provided in an embodiment of the present invention；
Fig. 9 is a kind of the schematic diagram of the section structure of display panel provided in an embodiment of the present invention；
Figure 10 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
As described in background, low-temperature polysilicon film transistor and sull crystal in existing array substrate
The shared film layer of pipe is less, leads to that the film layer in array substrate is more, production process is cumbersome.As shown in FIG. 1, FIG. 1 is existing
A kind of array substrate the schematic diagram of the section structure, even if the source electrode 101 of low-temperature polysilicon film transistor 10 and drain electrode 102 with
The source electrode 110 of oxide thin film transistor 11 and drain electrode 111 same layers setting, still, the film layer in array substrate is still more.
As shown in Fig. 2, Fig. 2 is a kind of existing the schematic diagram of the section structure of array substrate, in order to maximumlly reduce battle array
The film layer of column substrate, inventor is by the bottom of the active layer 103 of low-temperature polysilicon film transistor and oxide thin film transistor
The setting of 112 same layer of grid, still, will lead to the gate insulating layer 104 and oxide of low-temperature polysilicon film transistor in this way
The active layer 113 of thin film transistor (TFT) directly contacts, and the gate insulating layer 104 of low-temperature polysilicon film transistor is rich in hydrogen
Film layer, can the performance of active layer 113 to oxide thin film transistor have an impact, cause oxide thin film transistor characteristic
Drift.
Based on this, the present invention provides a kind of array substrates, to overcome the above problem of the existing technology, including substrate
And first film transistor and the second thin film transistor (TFT) on the substrate, the first film transistor and described
The active layer material of two thin film transistor (TFT)s is different；
The first film transistor includes the first active layer, first grid, the first source being sequentially located on the substrate
Pole and the first drain electrode, first active layer are low-temperature polycrystalline silicon layer；Second thin film transistor (TFT) is described including being sequentially located at
The second active layer, second grid, the second source electrode and the second drain electrode on substrate；
First source electrode, the first drain electrode, the second source electrode and the second drain electrode are located on the same floor；
There is first grid insulating layer, second active layer is located between first active layer and the first grid
The side of the first grid insulating layer far from the substrate, alternatively, second active layer is located at first grid insulation
Layer is close to the side of the substrate, but second active layer does not contact directly with the first grid insulating layer.
The present invention also provides a kind of display panels, including array substrate as described above.
The present invention also provides a kind of display devices, including display panel as described above.
Array substrate, display panel and display device provided by the present invention, the first source electrode, the first drain electrode and the second source
Pole, the second drain electrode are located on the same floor, and the second active layer is located at side of the first grid insulating layer far from substrate, alternatively, second
Close to the side of substrate, therefore active layer is located at first grid insulating layer, it is possible to reduce film layer, simplified production in array substrate
Process；Also, since the second active layer and first grid insulating layer are not directly contacted with, it can thus be avoided the first film crystal
First grid insulating layer in pipe influences the performance of the second thin film transistor (TFT), is conducive to be integrated with low-temperature polysilicon film transistor
With the practical application of the array substrate of oxide thin film transistor.
It is core of the invention thought above, to keep the above objects, features and advantages of the present invention more obvious easily
Understand, following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is clearly and completely retouched
It states, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on the present invention
In embodiment, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a kind of array substrates, as shown in figure 3, Fig. 3 is one kind provided in an embodiment of the present invention
The overlooking structure diagram of array substrate, the array substrate include viewing area AA and the non-display area AA ' around viewing area.
Wherein, viewing area AA includes a plurality of grid line 30, multiple data lines 31 and multiple pixels 32 etc..Each pixel 32 is wrapped
Include pixel electrode 320 and at least one thin film transistor (TFT) 321, which connect with grid line 30, source electrode with
The connection of data line 31, drain electrode are connect with pixel electrode 320.Non-display area AA ' includes gate driving circuit 33 and data-driven electricity
Road 34 etc., gate driving circuit 33 and data drive circuit 34 all include multiple thin film transistor (TFT) (not shown)s.
As shown in figure 4, Fig. 4 is a kind of the schematic diagram of the section structure of the array substrate shown in Fig. 3 along cutting line BB ', the battle array
Column substrate includes substrate 40, the first film transistor 41 on substrate 40 and the second thin film transistor (TFT) 42.Wherein, substrate 40
Glass substrate is included but are not limited to, also there is buffer layer 43, the buffer layer 43 between substrate 40 and first film transistor 41
It is chosen as silicon dioxide layer.
In the embodiment of the present invention, first film transistor 41 and the second thin film transistor (TFT) 42 are all located at viewing area AA, certainly,
The present invention is not limited to this, and first film transistor 41 and the second thin film transistor (TFT) 42 can also be all located at non-display area AA ',
Alternatively, in first film transistor 41 and the second thin film transistor (TFT) 42 one be located at viewing area AA, another be located at non-display area
AA'.As long as there is array substrate first film transistor 41 and the second thin film transistor (TFT) 42 implementation of the present invention can be used simultaneously
Film layer structure in example, in other words, as long as two kinds of thin film transistor (TFT)s that array substrate has active layer material different simultaneously
Using the film layer structure in the embodiment of the present invention.
In addition, it should be noted that, first film transistor 41 and the structure of the second thin film transistor (TFT) 42 can be identical, such as
First film transistor 41 and the second thin film transistor (TFT) 42 are all only to have single gate thin-film transistors of a grid, still, this
Invention is not limited to that, that is to say, that first film transistor 41 and the structure of the second thin film transistor (TFT) 42 can also be different,
Such as, first film transistor 41 is single gate thin-film transistors only with a grid, and the second thin film transistor (TFT) 42 is with two
The double gate thin-film transistor of a grid.
But must be noted that the first film transistor 41 in the embodiment of the present invention and the second thin film transistor (TFT) 42 has
Active layer material is different, i.e., first film transistor 41 and the second thin film transistor (TFT) 42 are different two kinds of of active layer material
Thin film transistor (TFT).
As shown in figure 4, first film transistor 41 includes the first active layer 410 being sequentially located on substrate 40, the first grid
Pole 411, the first source electrode 412 and the first drain electrode 413, the first active layer 410 are low-temperature polycrystalline silicon layer.Second thin film transistor (TFT) 42 packet
Include the second active layer 420 being sequentially located on substrate 40, second grid 421, the second source electrode 422 and the second drain electrode 423.
That is, first film transistor 41 in the embodiment of the present invention is low-temperature polysilicon film transistor, i.e., the
The material of the active layer 410 of one thin film transistor (TFT) 41 is low temperature polycrystalline silicon.Second thin film transistor (TFT) 42 is chosen as sull
Transistor, the i.e. material of the active layer 420 of the second thin film transistor (TFT) 42 are oxide semiconductor.The material of the oxide semiconductor
Including IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) and zinc oxide ZnO etc..
In addition, also having second grid insulating layer 424, second grid between the second active layer 420 and second grid 421
421 and second also have the second interlayer insulating film 425 between source electrode 422.Between first active layer 410 and first grid 411 also
With first grid insulating layer 414, also there is the first interlayer insulating film 415 between first grid 411 and the first source electrode 412,
In, the first interlayer insulating film 415 includes second grid insulating layer 424 and the second interlayer insulating film 425.First source electrode 412 and
Also there is planarization layer 44,44 top of planarization layer also has to drain with the first drain electrode 413 and second respectively above two source electrode 420
The pixel electrode 45 etc. of 423 electrical connections, details are not described herein.
In the embodiment of the present invention, first grid 411, the drain electrode of the first source electrode 412, first 413, second grid 421, the second source
The material of pole 422 and the second drain electrode 423 is all metal, such as molybdenum, titanium, aluminium.Also, first grid 411, the first source electrode 412,
The structure being located on the same floor in one drain electrode 413, second grid 421, the second source electrode 422 and the second drain electrode 423 preferably uses same
Kind metal material, the structure positioned at different layers can use different metal materials, can also use same metal material.
Optionally, first grid insulating layer 414 is silicon nitride, and the hydrogen content in first grid insulating layer 414 is greater than 1%,
Still optionally further, the hydrogen content in first grid insulating layer 414 is greater than 6%, to pass through first grid insulating layer 414 to first
The hydrogenation of active layer 410 reduces the defects of first active layer 410 etc., improves the performance of the first active layer 410.Optionally,
Two gate insulating layers 424 and the second interlayer insulating film 425 are silica etc..
Since the first active layer 410 is low-temperature polycrystalline silicon layer, internal there are more defects state, main defect state is outstanding
Key is hung therefore to hydrogenate the first active layer 410 by first grid insulating layer 414, first grid insulating layer can be made
Hydrogen ion in 414 diffuses into the first active layer 410, and in conjunction with the dangling bonds in the first active layer 410, repairs defect.
In the embodiment of the present invention, the first source electrode 412, first drain electrode 413 is located at the second source electrode 422 and the second drain electrode 423
Same layer, i.e. the first source electrode 412, first drain electrode 413 is identical as the material of the second source electrode 422 and the second drain electrode 423, and using same
One process is made.Second active layer 420 is located at side of the first grid insulating layer 414 far from substrate 40, alternatively, second has
Active layer 420 is located at first grid insulating layer 414 close to the side of substrate 40, but the second active layer 420 and first grid insulating layer
414 are not directly contacted with.
In the embodiment of the present invention, due to the drain electrode 413 of the first source electrode 412, first and the second source electrode 422 and the second drain electrode 423
Material be all metal, manufacture craft is also identical, therefore, in the embodiment of the present invention by by the first source electrode 412, first drain
413 and second source electrode 422 and the second drain electrode 423 same layers setting, it is possible to reduce the film layer of array substrate simplifies production process.And
Second active layer 420 is arranged in the side of side or close substrate 40 of the first grid insulating layer 414 far from substrate 40, it can
To be further reduced the film layer of array substrate, simplify production process.Further, since the second active layer 420 insulate with first grid
Layer 414 is not directly contacted with, and first grid insulating layer 414 is directly contacted with the first active layer 410, therefore, can not only pass through richness
Hydrogeneous first grid insulating layer 414 eliminates the defects of first active layer 410 etc., can also avoid first film transistor 41
In first grid insulating layer 414 influence the second thin film transistor (TFT) 42 performance, be conducive to low-temperature polysilicon film crystal
The practical application of the array substrate of pipe and oxide thin film transistor.
In the embodiment of the present invention, the second active layer 420 is located at side of the first grid insulating layer 414 far from substrate 40, the
It is active with buffer layer and/or first grid insulating layer 414 and second between two active layers 420 and first grid insulating layer 414
420 opposite region hollow out of layer；Alternatively, the second active layer 420 is located at first grid insulating layer 414 close to the side of substrate 40,
Between second active layer 420 and first grid insulating layer 414 there is buffer layer and/or first grid insulating layer 414 to have with second
The opposite region hollow out of active layer 420.
Certainly, the present invention is not limited to this, in other embodiments, can also realize that second is active using other modes
Layer 420 is not directly contacted with first grid insulating layer 414.
In an embodiment of the invention, as shown in figure 4, first grid insulating layer 414 is opposite with the second active layer 420
Region hollow out, that is to say, that first grid insulating layer 414 has hollowed out area 414a, and the second active layer 420 is on substrate 40
Projection is located at hollowed out area 414a in the projection on substrate 40.The shapes and sizes and the second active layer of hollowed out area 414a
420 shapes and sizes are correspondingly arranged, and are directly contacted to avoid first grid insulating layer 414 with the second active layer 420.
In the present embodiment, by will hollow out or etch with the first grid insulating layer 414 of 420 corresponding region of the second active layer
Fall, to avoid the second active layer 420 from directly contacting with first grid insulating layer 414, and then avoids in first film transistor 41
First grid insulating layer 414 influence the second thin film transistor (TFT) 42 performance.
On this basis, as shown in figure 4, the second active layer 420 can be located on the same floor with first grid 411, with into one
Film layer, simplified process in the reduction array substrate of step.It should be noted that the first grid for etching away hollowed out area 414a is exhausted
After edge layer 414, buffer layer can be formed in hollowed out area 414a, so that the second active layer 420 can be with 411 same layer of first grid
Setting.It should be noted that the buffer layer is excellent when the buffer layer of the second active layer 420 and hollowed out area 414a directly contacts
It is selected as silicon dioxide layer.
Since the material of the second active layer 420 is oxide semiconductor, the material of first grid 411 is metal, therefore,
In manufacturing process, first grid 411 can be first formed on first grid insulating layer 414, then in the exhausted of hollowed out area 414a
The second active layer 420 is formed in edge layer.
As shown in figure 5, another the schematic diagram of the section structure of the Fig. 5 for array substrate provided in an embodiment of the present invention, second
Active layer 420 can not be located on the same floor with first grid 411, i.e., the second active layer 420 is located at first grid 411 and second gate
Between pole 421, such as the second active layer 420 is located at side of the first grid 411 far from substrate 40, first grid insulating layer 414 and
The opposite region hollow out of second active layer 420, and the second active layer 420 and first grid 411 or first grid insulating layer 414 it
Between have first buffer layer 426.
In the present embodiment, it will hollow out or etch away with the first grid insulating layer 414 of 420 corresponding region of the second active layer,
And first buffer layer 426 is set between the second active layer 420 and first grid insulating layer 414, more effectively to avoid second
Active layer 420 is directly contacted with first grid insulating layer 414, and then the first grid in first film transistor 41 is avoided to insulate
Layer 414 influences the performance of the second thin film transistor (TFT) 42.
In structure shown in Fig. 5, the second thin film transistor (TFT) 42 further includes third grid 428, third grid 428 and first
Grid 411 is located on the same floor.Based on this, the second thin film transistor (TFT) 42 in the embodiment of the present invention can also be double grid film crystal
Pipe.
In addition, first film transistor 41 further includes first capacitor, first capacitor includes first electrode and second electrode,
One electrode is multiplexed first grid 411, and second electrode 416 is located on the same floor with the second active layer 420.It can be with by the first capacitor
The ability that first film transistor 41 stores charge is improved, the switch performance of first film transistor 41 is improved.
It should be noted that the second active layer 420 of the second thin film transistor (TFT) 42 in the embodiment of the present invention can also wrap
Source lead 420a and drain lead 420b are included, source lead 420a is electrically connected by through-hole with the second source electrode 422, drain lead
420b is electrically connected by another through-hole with the second drain electrode 423.In the structure of Fig. 6 and Fig. 7, source lead 420a and drain electrode are drawn
Line 420b and second electrode 416 are located at same layer, and still, the present invention is not limited to this.Source lead 420a and drain lead
420b, to 420 over etching of the second active layer, can influence the performance of the second active layer 420 to avoid when forming through-hole.
As shown in fig. 6, another the schematic diagram of the section structure of the Fig. 6 for array substrate provided in an embodiment of the present invention, first
The region hollow out opposite with the second active layer 420 of gate insulating layer 414, the second active layer 420 are located at first grid 411 close to lining
The side at bottom 40, and the second active layer 420 is located on the same floor with the first active layer 410.
Based on this, second grid 421 can be located on the same floor with first grid 411, and first grid insulating layer 414 can be with
Second grid insulating layer 424 is located on the same floor, and the first interlayer insulating film 415 can be located at same with the second interlayer insulating film 425
Layer simplifies manufacture craft so as to maximumlly reduce the film layer in array substrate.
In an embodiment of the invention, as shown in fig. 7, Fig. 7 is the another of array substrate provided in an embodiment of the present invention
Kind the schematic diagram of the section structure, the second active layer 420 is located at side of the first grid insulating layer 414 far from substrate 40, and second has
At least there is first buffer layer 426, and the hydrogen content of first buffer layer 426 is small between active layer 420 and first grid insulating layer 414
In the hydrogen content of first grid insulating layer 414.Optionally, first buffer layer 426 is silicon dioxide layer, the hydrogen of the silicon dioxide layer
Content is greater than 0, less than 1%.
In structure shown in Fig. 7, first buffer layer is set between the second active layer 420 and first grid insulating layer 414
426, more effectively the second active layer 420 is avoided directly to contact with first grid insulating layer 414, and then avoid the first film brilliant
First grid insulating layer 414 in body pipe 41 influences the performance of the second thin film transistor (TFT) 42.
As shown in figure 8, another the schematic diagram of the section structure of the Fig. 8 for array substrate provided in an embodiment of the present invention, first
Also there is second buffer layer 427 between buffer layer 426 and first grid insulating layer 414.The hydrogen content of second buffer layer 427 is greater than
The hydrogen content of first buffer layer 426.
Optionally, first buffer layer 426 is silicon dioxide layer, and the hydrogen content of the silicon dioxide layer is greater than 0, less than 1%.It can
Selection of land, second buffer layer 427 are silicon nitride layer, and the hydrogen content of the silicon nitride layer is greater than 1%, less than 20%.
Due to the defects of the first active layer 410 limited amount, if the hydrogen content in first grid insulating layer 414
It is poor to the repairing effect of the first active layer 410 less than 6%, i.e., it cannot preferably repair lacking in the first active layer 410
It falls into, if the hydrogen content in first grid insulating layer 414 is greater than 20%, extra hydrogen ion, which can stay in first as new defect, to be had
In active layer 410, the stability of first film transistor 41 is influenced.
It should be noted that in the embodiment of the present invention, after forming first grid insulating layer 414, or the is being formed
After one grid 411, or after forming second buffer layer 427, need to complete activation and hydrogenation process, optionally, technique
Temperature is 440 DEG C ± 60 DEG C.
In structure shown in Fig. 8, first grid insulating layer 414 and first not only may be implemented by second buffer layer 427
Transition between buffer layer 426 improves the binding force between first grid insulating layer 414 and first buffer layer 426, moreover, also
Further the first active layer 410 can be hydrogenated, reduce the defect etc. of the first active layer 410.
Equally, in Fig. 7 and structure shown in Fig. 8, first film transistor 41 can also include first capacitor, and second is thin
Film transistor 42 can also include third grid 428, source lead 420a and drain lead 420b etc., and details are not described herein.
The embodiment of the invention also provides a kind of display panels, as shown in figure 9, Fig. 9 is provided in an embodiment of the present invention one
The schematic diagram of the section structure of kind display panel, the display panel include array substrate 1, color membrane substrates 2 and are arranged in array base
Liquid crystal layer 3 between plate 1 and color membrane substrates 2.
Wherein, which is the array substrate that any of the above-described embodiment provides.Only with liquid crystal display panel in Fig. 9
For be illustrated, the present invention is not limited to this, that is to say, that the display panel in the embodiment of the present invention can also be LED
Display panel or OLED display panel etc..
The embodiment of the invention also provides a kind of display devices, and as shown in Figure 10, Figure 10 is provided in an embodiment of the present invention
A kind of structural schematic diagram of display device, display device P include but is not limited to mobile phone, tablet computer and digital camera
Deng.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.To the upper of the disclosed embodiments
It states bright, enables those skilled in the art to implement or use the present invention.Various modifications to these embodiments are to ability
Will be apparent for the professional technician in domain, the general principles defined herein can not depart from it is of the invention
In the case where spirit or scope, realize in other embodiments.Therefore, the present invention be not intended to be limited to it is shown in this article these
Embodiment, and it is to fit to the widest scope consistent with the principles and novel features disclosed herein.
Claims (14)
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