CN109309008A - A power device and method of making the same - Google Patents
A power device and method of making the same Download PDFInfo
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- CN109309008A CN109309008A CN201811256347.7A CN201811256347A CN109309008A CN 109309008 A CN109309008 A CN 109309008A CN 201811256347 A CN201811256347 A CN 201811256347A CN 109309008 A CN109309008 A CN 109309008A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of power device and preparation method thereof, it include: the substrate of the first conduction type, first epitaxial layer of the first conduction type, groove, first silicon oxide layer, second silicon oxide layer, third silicon oxide layer, second polysilicon layer, second epitaxial layer of the second conduction type, the third epitaxial layer of first conduction type, the fourth epitaxial layer and third polysilicon layer of second conduction type, body area, source electrode, grid, drain electrode, the power device avoids the method that Conventional power devices need to connect by encapsulation with protection device, reduce device area, reduce encapsulation manufacturing cost, improve product reliability.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power device and preparation method thereof.
Background technique
VDMOS (is the abbreviation of VDMOSFET, Vertical Double Diffused Metal Oxide
Semiconductor Field Effect Transistor, vertical DMOS field effect transistor)
Drain-source the two poles of the earth respectively in the two sides of device, so that electric current is vertically circulated in device inside, increase current density, improve specified
The conducting resistance of electric current, unit area is also smaller, is a kind of power device that purposes is very extensive.The gate controller of VDMOS
Part channel is opened, and the oxide layer high-voltage resistance capability of gate location is poor (usually < 100V), is highly prone to transient voltage surge destruction,
Lead to component failure.
The transient voltage that static discharge and some other voltage surge form occur at random, is typically found in various electronics
In device.As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to voltage
The influence of surge, even results in fatal harm.Various voltage surges can induce transient current from static discharge to lightning etc.
Spike, impact of the Transient Voltage Suppressor commonly used to protection sensitive circuit by surge.Based on different applications, transient voltage
Suppressor can play the role of circuit protection by changing the clamping voltag of surge discharge path and itself.
Transient Voltage Suppressor be it is a kind of be used to protect sensitive semiconductor device, make its destroy from transient voltage surge and
Specially designed solid-state semiconductor device, it has, and clamp coefficient is small, response is fast, leakage current is small and high reliability, because
And it is widely used on voltage transient and carrying out surge protection.Transient Voltage Suppressor is suitable for the protector of high-frequency circuit
Part reduces the decaying of high-frequency circuit signal because it can reduce interference of the parasitic capacitance to circuit.
The common method of protection semiconductor devices is that Transient Voltage Suppressor is connect use with semiconductor devices at present, this
Sample increases device area and manufacturing cost, and product reliability is bad.
Summary of the invention
The embodiment of the present invention based on the above issues, proposes a kind of power device and preparation method thereof, avoids conventional function
Rate device needs the method connected by encapsulation with protection device, reduces device area, reduces encapsulation manufacturing cost, improves
Product reliability.
On the one hand, the present invention provides a kind of production methods of power device, this method comprises:
The substrate of first conduction type is provided；
Surface forms the first epitaxial layer of the first conduction type over the substrate；
Groove is formed in first epitaxial layer upper surface；
The first silicon oxide layer is formed in the bottom and side wall of the groove；
The first polysilicon layer is formed on the surface of first oxide layer；
The second silicon oxide layer is formed in the side wall of first polysilicon layer；
In first epitaxial layer upper surface formed third silicon oxide layer, one end of the third silicon oxide layer with it is described
The connection of first silicon oxide layer, the other end of the third silicon oxide layer are connect with second silicon oxide layer；
In the part that first polysilicon layer is not covered by second silicon oxide layer, injection ion forms first
Second polysilicon layer of conduction type；
The second epitaxial layer of the second conduction type is formed in second polysilicon layer upper surface；
The third epitaxial layer of the first conduction type is formed in second epitaxial layer upper surface；
It is respectively formed the fourth epitaxial layer and third polysilicon layer of the second conduction type in third epitaxial layer upper surface,
The third polysilicon layer is located at the two sides of the fourth epitaxial layer；
Form the body area of the second conduction type in first epitaxial layer, at least partly surface exposure in the body area in
The upper surface of first epitaxial layer, the one end in the body area are connect with first silicon oxide layer；
Source region is formed in the body area, at least partly surface exposure of the source region is in the upper table of first epitaxial layer
Face, one end of the source region are connect with first silicon oxide layer；
Dielectric layer is formed in first epitaxial layer upper surface；
The first metal layer is formed above the dielectric layer, the first metal layer is through the dielectric layer and the source region
Connection forms source electrode；
Second metal layer is formed above the dielectric layer, the second metal layer runs through the dielectric layer and the described 4th
Epitaxial layer connects to form grid；
Third metal layer is formed in the substrate lower surface, the third metal layer connect to form drain electrode with the substrate.
Further, the power device includes multiple second epitaxial layers and multiple third epitaxial layers, described
Second epitaxial layer and the setting of third epitaxial layer interval.
Further, the ion concentration of the third epitaxial layer is lower than the ion concentration of first epitaxial layer.
Further, the ion concentration of the fourth epitaxial layer is higher than the ion concentration of second epitaxial layer.
Further, ion is injected in the part that first polysilicon layer is not covered by second silicon oxide layer
The second polysilicon layer for forming the first conduction type, specifically includes:
The first conduction is not implanted sequentially by the part that second silicon oxide layer is covered in first polysilicon layer
Ion, argon ion and the oxonium ion of type；
First polysilicon layer upper surface described in hydrofluoric acid clean using 10%；
Short annealing, annealing temperature are 900 DEG C, and the time is 30 seconds.
Further, the thickness of first polysilicon layer is greater than 300 nanometers.
On the other hand, the present invention provides a kind of power device, which includes:
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type of the upper surface of substrate；
It is formed in the groove of first epitaxial layer upper surface；
It is formed in the first silicon oxide layer of the channel bottom and side wall；
It is formed in the first polysilicon layer of the first oxidation layer surface；
It is formed in the second silicon oxide layer of the first polysilicon layer side wall；
The third silicon oxide layer being formed in first epitaxial layer upper surface, one end of the third silicon oxide layer and institute
The connection of the first silicon oxide layer is stated, the other end of the third silicon oxide layer is connect with second silicon oxide layer；
Injection ion is formed in the part that first polysilicon layer is not covered by second silicon oxide layer the
Second polysilicon layer of one conduction type；
It is formed in the second epitaxial layer of the second conduction type of second polysilicon layer upper surface；
It is formed in the third epitaxial layer of the first conduction type of second epitaxial layer upper surface；
It is respectively formed in the fourth epitaxial layer and third polysilicon of the second conduction type of third epitaxial layer upper surface
Layer, the third polysilicon layer are located at the two sides of the fourth epitaxial layer；
It is formed in the body area of the second conduction type in first epitaxial layer, at least partly surface exposure in the body area
In the upper surface of first epitaxial layer, the one end in the body area is connect with first silicon oxide layer；
The source region being formed in the body area, at least partly surface exposure of the source region is in the upper of first epitaxial layer
Surface, one end of the source region are connect with first silicon oxide layer；
It is formed in the dielectric layer of first epitaxial layer upper surface；
The first metal layer being formed in above the dielectric layer, the first metal layer is through the dielectric layer and the source
Area connects to form source electrode；
The second metal layer being formed in above the dielectric layer, the second metal layer is through the dielectric layer and described the
Four epitaxial layers connect to form grid；
It is formed in the third metal layer of the substrate lower surface, the third metal layer connect to form leakage with the substrate
Pole.
Further, the power device includes multiple second epitaxial layers and multiple third epitaxial layers, described
Second epitaxial layer and the setting of third epitaxial layer interval.
Further, the ion concentration of the third epitaxial layer is lower than the ion concentration of first epitaxial layer.
Further, the ion concentration of the fourth epitaxial layer is higher than the ion concentration of second epitaxial layer.
The present invention is through the above technical solutions, propose a kind of power device core of trench-gate integrated static safeguard structure
Piece avoids the method that Conventional power devices need to connect by encapsulation with protection device, reduces device area, reduce envelope
Manufacturing cost is filled, product reliability is improved.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.?
In attached drawing:
Fig. 1 is the flow diagram of the production method for the power device that one embodiment of the present of invention provides；
Fig. 2 to Fig. 7 is the structural schematic diagram of the making step for the function power device that one embodiment of the present of invention provides；
Description of symbols:
1- substrate；The first epitaxial layer of 2-；The second epitaxial layer of 3-；4- third epitaxial layer；5- fourth epitaxial layer；6- groove；7-
First polysilicon layer；The second polysilicon layer of 8-；9- third polysilicon layer；The first silicon oxide layer of 10-；The second silicon oxide layer of 11-；
12- third silicon oxide layer；13- source region；14- body area；15- dielectric layer；16- the first metal layer；17- second metal layer；18- third
Metal layer.
Specific embodiment
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
A kind of power device provided in an embodiment of the present invention and preparation method thereof is carried out below in conjunction with Fig. 1 to Fig. 7 detailed
Explanation.
The embodiment of the present invention provides a kind of production method of power device, the function that one embodiment as shown in Figure 1 provides
The production method of the flow diagram of the production method of rate device, the power device includes:
Step S1: the substrate of the first conduction type is provided；
Step S2: surface forms the first epitaxial layer 2 of the first conduction type over the substrate；
Step S3: groove 6 is formed in 2 upper surface of the first epitaxial layer；
Step S4: the first silicon oxide layer 10 is formed in the bottom and side wall of the groove 6；
Step S5: the first polysilicon layer 7 is formed on the surface of first oxide layer；
Step S6: the second silicon oxide layer 11 is formed in the side wall of first polysilicon layer 7；
Step S7: third silicon oxide layer 12, the third silicon oxide layer 12 are formed in 2 upper surface of the first epitaxial layer
One end connect with first silicon oxide layer 10, the other end of the third silicon oxide layer 12 and second silicon oxide layer 11
Connection；
Step S8: first polysilicon layer 7 not by the part that second silicon oxide layer 11 is covered inject from
Son forms the second polysilicon layer 8 of the first conduction type；
Step S9: the second epitaxial layer 3 of the second conduction type is formed in 8 upper surface of the second polysilicon layer；
Step S10: the third epitaxial layer 4 of the first conduction type is formed in 3 upper surface of the second epitaxial layer；
Step S11: the fourth epitaxial layer 5 and of the second conduction type is respectively formed in 4 upper surface of third epitaxial layer
Three polysilicon layers 9, the third polysilicon layer 9 are located at the two sides of the fourth epitaxial layer 5；
Step S12: the body area 14 of the second conduction type is formed in first epitaxial layer 2, the body area 14 is at least
Part of the surface is exposed to the upper surface of first epitaxial layer 2, and the one end in the body area 14 and first silicon oxide layer 10 connect
It connects；
Source region 13 is formed in the body area 14, at least partly surface exposure of the source region 13 is in first epitaxial layer
2 upper surface, one end of the source region 13 are connect with first silicon oxide layer 10；
Dielectric layer 15 is formed in 2 upper surface of the first epitaxial layer；
Form the first metal layer 16 above the dielectric layer 15, the first metal layer 16 through the dielectric layer 15 with
The connection of source region 13 forms source electrode；
Form second metal layer 17 above the dielectric layer 15, the second metal layer 17 through the dielectric layer 15 with
The connection of fourth epitaxial layer 5 forms grid；
Third metal layer 18 is formed in the substrate lower surface, the third metal layer 18 connect to form leakage with the substrate
Pole.
Technical solution of the present invention is related to designing and manufacturing for semiconductor devices, and semiconductor refers to that a kind of electric conductivity can be controlled
System, conductive extensions can be from insulator to the material changed between conductor, and common semiconductor material has silicon, germanium, GaAs etc., and
Silicon is most powerful, one kind for being most widely used in various semiconductor materials.Semiconductor is divided into intrinsic semiconductor, p-type
Semiconductor and N-type semiconductor, free from foreign meter and without lattice defect semiconductor is known as intrinsic semiconductor, in pure silicon crystal
It mixes triad (such as boron, indium, gallium), is allowed to replace the seat of silicon atom in lattice, P-type semiconductor is just formed, pure
Silicon crystal in mix pentad (such as phosphorus, arsenic), be allowed to replace the position of silicon atom in lattice, be formed N-type and partly lead
The conduction type of body, P-type semiconductor and N-type semiconductor is different, and in an embodiment of the present invention, the first conduction type is N-type, the
Two conduction types are p-type, in an embodiment of the present invention, if not otherwise specified, the preferred doping of every kind of conduction type from
Son is all that can be changed to the ion with same conductivity type, is just repeated no more below.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate 1, or Sapphire Substrate 1 can also be
Silicon carbide substrates 1, it might even be possible to be silicon Chu substrate 1, it is preferred that the substrate 1 is silicon substrate 1, this is because 1 material of silicon substrate
Have the characteristics that low cost, large scale, conductive, avoids edge effect, yield can be increased substantially.In reality of the invention
Apply in example, the substrate 1 is the substrate 1 of the first conduction type, and first conduction type is N-type, the doping of the substrate 1 from
Son is phosphorus or arsenic etc., and 1 doping concentration of substrate is highly doped.
Referring next to attached drawing, the production method of power device described above is elaborated.
Attached drawing 2 is please referred to, step S1, S2 is executed, specifically: the substrate 1 of the first conduction type is provided；In the substrate 1
Upper surface forms the first epitaxial layer 2 of the first conduction type.Wherein epitaxial growth shape can be used in 1 upper surface of substrate
At first epitaxial layer 2 can also be formed in 1 upper surface of substrate by ion implanting and/or the method for diffusion.Into one
Step ground, can be epitaxially-formed in the 1 upper surface use of substrate, can also pass through ion implanting and/or diffusion P elements
Or the method for any combination of arsenic element or both forms first epitaxial layer 2 in 1 upper surface of substrate.Specifically, institute
The method for stating epitaxial growth or diffusion includes depositing operation.In some embodiments of the invention, depositing operation can be used to exist
1 upper surface of substrate forms first epitaxial layer 2, for example, depositing operation can be selected from electron beam evaporation, chemical gaseous phase
One of deposition, atomic layer deposition, sputtering.Preferably, described first is formed using chemical vapor deposition on the substrate 1
Epitaxial layer 2, chemical vapor deposition include process for vapor phase epitaxy.In production, chemical vapor deposition uses vapour phase epitaxy work mostly
Skill forms the first epitaxial layer 2 using process for vapor phase epitaxy in 1 upper surface of substrate, and silicon material can be improved in process for vapor phase epitaxy
The perfection of material improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.The substrate 1
Doping concentration is different from the doping concentration of first epitaxial layer 2.Preferably, the doping concentration of the substrate 1 is higher than described the
The doping concentration of one epitaxial layer 2, the resistivity of substrate 1 described in the resistivity ratio of first epitaxial layer 2 is high at this time, reduces parasitic
Resistance, to improve the breakdown reverse voltage of device.
Attached drawing 2 is please referred to, step S3 is executed, specifically: groove 6 is formed in 2 upper surface of the first epitaxial layer.Described
The groove 6 for running through first epitaxial layer 2 is formed in first epitaxial layer 2.In some embodiments of the invention, the ditch
The bottom surface of slot 6 is not connect with the substrate.Mask material, the mask material are prepared in the upper surface of first epitaxial layer 2
Specially the first photoresist forms the ditch for running through first epitaxial layer 2 on first photoresist layer by etching
Slot 6, then remove first photoresist.Wherein, the method for etching includes dry etching and wet etching, it is preferred that is used
The method of etching is dry etching, and dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching is easy
Realize that automation, treatment process are not introduced into pollution, cleannes height.
Attached drawing 2 and Fig. 3 are please referred to, step S4 is executed, specifically: the first oxygen is formed in the bottom and side wall of the groove 6
SiClx layer 10.Silicon oxide layer is filled on the groove 6 and first epitaxial layer 2, the silicon oxide layer is insulating layer, described
Sputtering can be used in silicon oxide layer or thermal oxide is formed.In some embodiments of the invention, the silicon oxide layer is thermal oxide
It is formed, in subsequent doping step, the silicon oxide layer is as protective layer, and by the layer insulation as resulting devices
Layer.Mask material is prepared in the upper surface of the silicon oxide layer, the mask material is specially the second photoresist, described second
By being etched away 6 inner part silicon oxide layer of 2 upper surface of the first epitaxial layer and the groove on photoresist layer, in the ditch
6 bottom and side wall of slot forms first silicon oxide layer 10.Wherein, the method for etching includes dry etching and wet etching, excellent
Choosing, the method for the etching used is dry etching, and dry etching includes photoablation, gaseous corrosion, plasma etching etc., and
Dry etching easily realizes that automation, treatment process are not introduced into pollution, cleannes height.
Attached drawing 4 is please referred to, step S5 is executed, specifically: the first polysilicon layer is formed on the surface of first oxide layer
7.First polysilicon layer 7 is formed by the method for extension or diffusion on the surface of first oxide layer.Specifically, described
Extension or the method for diffusion include depositing operation.In some embodiments of the invention, depositing operation can be used described
The surface of one oxide layer forms the first polysilicon layer 7, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition
One of product, atomic layer deposition, sputtering.Preferably, low-pressure chemical vapor deposition is used on the surface of first oxide layer
Product (abbreviation LPCVD, i.e. Low Pressure Chemical Vapor Deposition) forms first polysilicon layer 7,
The purity is high of first polysilicon layer 7 formed, uniformity are good.Further, the thickness of first polysilicon layer 7 is greater than
300 nanometers.
Attached drawing 5 is please referred to, step S6 and S7 are executed, specifically: the second oxygen is formed in the side wall of first polysilicon layer 7
SiClx layer 11；Third silicon oxide layer 12, one end of the third silicon oxide layer 12 are formed in 2 upper surface of the first epitaxial layer
It is connect with first silicon oxide layer 10, the other end of the third silicon oxide layer 12 is connect with second silicon oxide layer 11.
The silicon oxide layer is insulating layer, and sputtering can be used in the silicon oxide layer or thermal oxide is formed.In some implementations of the invention
Example in, the silicon oxide layer is formed for thermal oxide, in subsequent doping step, the silicon oxide layer as protective layer, and
By the interlayer insulating film as resulting devices.Second silicon oxide layer 11 with a thickness of 50-100 nanometers.
Attached drawing 5 is please referred to, step S8 is executed, specifically: in first polysilicon layer 7 not by second silica
The part injection ion that layer 11 is covered forms the second polysilicon layer 8 of the first conduction type.Further, more than described first
The part injection ion that crystal silicon layer 7 is not covered by second silicon oxide layer 11 forms the second polycrystalline of the first conduction type
Silicon layer 8, specifically includes: not being infused successively by the part that second silicon oxide layer 11 is covered in first polysilicon layer 7
Enter the ion, argon ion and oxonium ion of the first conduction type；Table on first polysilicon layer 7 described in hydrofluoric acid clean using 10%
Face；Short annealing, annealing temperature are 900 DEG C, and the time is 30 seconds.It is not aoxidized by described second in first polysilicon layer 7
The ion of the first conduction type is injected in the part that silicon layer 11 is covered, and the amount for injecting ion is 1 × 10-11, injecting voltage is
Movable charge can be concentrated on polysilicon surface, increase the electric conductivity of polysilicon by 30KeV, this process.Inject oxonium ion and
Argon ion can eliminate the defect of polysilicon surface in technical process, improve surface quality and subsequent epitaxy technique is facilitated to carry out.
Ion implanting terminate after using 10% hydrofluoric acid clean described in 7 upper surface of the first polysilicon layer, remove the damage of polysilicon surface
Wound and extra movable charge carry out a short annealing later, and annealing temperature is 900 DEG C, and the time is 30 seconds.
Attached drawing 6 is please referred to, step S9 and S10 are executed, specifically: second is formed in 8 upper surface of the second polysilicon layer
Second epitaxial layer 3 of conduction type；The third epitaxial layer 4 of the first conduction type is formed in 3 upper surface of the second epitaxial layer.Its
In can be epitaxially-formed in the 8 upper surface use of the second polysilicon layer, ion implanting and/or diffusion can also be passed through
Method forms second epitaxial layer 3 in 8 upper surface of the second polysilicon layer.It is possible to further in second polycrystalline
8 upper surface use of silicon layer is epitaxially-formed, and can also pass through ion implanting and/or diffusion boron element or phosphide element or aluminium element
Or the method for any combination of three forms second epitaxial layer 3 in 8 upper surface of the second polysilicon layer.Specifically, institute
The method for stating epitaxial growth or diffusion includes depositing operation.In some embodiments of the invention, depositing operation can be used to exist
Second polysilicon layer, 8 upper surface forms second epitaxial layer 3, for example, depositing operation can be selected from electron beam evaporation,
One of chemical vapor deposition, atomic layer deposition, sputtering.Preferably, chemical gaseous phase is used on second polysilicon layer 8
Deposition forms the second epitaxial layer 3, and chemical vapor deposition includes process for vapor phase epitaxy.In production, chemical vapor deposition makes mostly
With process for vapor phase epitaxy, the second epitaxial layer 3, gas phase are formed using process for vapor phase epitaxy in 8 upper surface of the second polysilicon layer
The perfection of silicon materials can be improved in epitaxy technique, improves the integrated level of device, reaches raising minority carrier life time, reduces storage element
Leakage current.It can be similarly epitaxially-formed in the 3 upper surface use of the second epitaxial layer, ion implanting can also be passed through
And/or the method for any combination of diffusion P elements or arsenic element or both formed in 3 upper surface of the second epitaxial layer it is described
Third epitaxial layer 4.Further, the power device includes multiple second epitaxial layers 3 and multiple third epitaxial layers
4, second epitaxial layer 3 and the third epitaxial layer 4 interval are arranged.Due to second epitaxial layer 3 and the third extension
The ionic species of layer 4 is different, by the PN junction of formation, increases the voltage endurance capability of power device, multiple second epitaxial layer, 3 Hes
The multiple interval of third epitaxial layer 4 settings can be further improved the resistance to pressure of power device, as second epitaxial layer 3
Setting number with the third epitaxial layer 4 can be depending on demand of the power device for resistance to pressure.Further, described
The ion concentration of third epitaxial layer 4 is lower than the ion concentration of first epitaxial layer 2.Third epitaxial layer described in such structure setting
4 resistivity is higher than first epitaxial layer 2, and the resistance to pressure of power device can be improved.
Attached drawing 6 is please referred to, step S11 is executed, specifically: second, which is respectively formed, in 4 upper surface of third epitaxial layer leads
The fourth epitaxial layer 5 and third polysilicon layer 9 of electric type, the third polysilicon layer 9 are located at the two of the fourth epitaxial layer 5
Side.The fourth epitaxial layer 5 and 9 upper surface of third polysilicon layer and the upper surface of first epitaxial layer 2 substantially maintain an equal level.
In some embodiments, substantially maintaining an equal level refers to the fourth epitaxial layer 5 and 9 upper surface of third polysilicon layer than described first
2 upper surface of epitaxial layer is high, and the fourth epitaxial layer 5 and 9 upper surface of third polysilicon layer may be used also in further embodiments
With lower than 2 upper surface of the first epitaxial layer, the difference in height of the two is specially in technical process in acceptable error range.It can
To be epitaxially-formed in the 4 upper surface use of third epitaxial layer, can also by ion implanting and/or diffusion boron element or
The method of any combination of phosphide element or aluminium element or three forms the fourth epitaxial layer in 4 upper surface of third epitaxial layer
5.Specifically, the method for the epitaxial growth or diffusion includes depositing operation.In some embodiments of the invention, it can be used
Depositing operation forms the fourth epitaxial layer 5 in 4 upper surface of third epitaxial layer, for example, depositing operation can be selected from electricity
One of beamlet evaporation, chemical vapor deposition, atomic layer deposition, sputtering.Preferably, it is used on the third epitaxial layer 4
Chemical vapor deposition forms fourth epitaxial layer 5, and chemical vapor deposition includes process for vapor phase epitaxy.In production, chemical vapor deposition
Product uses process for vapor phase epitaxy mostly, forms fourth epitaxial layer using process for vapor phase epitaxy in 4 upper surface of third epitaxial layer
5, the perfection of silicon materials can be improved in process for vapor phase epitaxy, improves the integrated level of device, reaches raising minority carrier life time, reduces storage
The leakage current of memory cell.The third polysilicon is formed by the method for extension or diffusion on the surface of the third epitaxial layer 4
Layer 9.Specifically, the extension or the method for diffusion include depositing operation.In some embodiments of the invention, it is heavy to can be used
Product technique forms third polysilicon layer 9 on the surface of the third epitaxial layer 4, for example, depositing operation can be selected from electron beam
One of evaporation, chemical vapor deposition, atomic layer deposition, sputtering.Preferably, it is used on the surface of the third epitaxial layer 4
Low-pressure chemical vapor deposition (abbreviation LPCVD, i.e. Low Pressure Chemical Vapor Deposition) forms institute
State third polysilicon layer 9, the purity is high of the third polysilicon layer 9 of formation, uniformity is good.As Fig. 6 power device made
In journey wherein shown in the sectional view of structure, the third polysilicon layer 9 is located at 5 two sides of fourth epitaxial layer, by the described 4th
Two sides of epitaxial layer 5 cover.Further, the ion concentration of the fourth epitaxial layer 5 is higher than second epitaxial layer 3
Ion concentration.The resistivity of fourth epitaxial layer 5 described in such structure setting is lower than second epitaxial layer 3, reduces power device
Parasitic capacitance.
Attached drawing 7 is please referred to, step S12 is executed, specifically: the second conduction type is formed in first epitaxial layer 2
Body area 14, at least partly surface exposure in the body area 14 is in the upper surface of first epitaxial layer 2, the one end in the body area 14
It is connect with first silicon oxide layer 10；Source region 13 is formed in the body area 14, at least partly surface of the source region 13 is naked
It is exposed to the upper surface of first epitaxial layer 2, one end of the source region 13 is connect with first silicon oxide layer 10；Described
One epitaxial layer, 2 upper surface forms dielectric layer 15；The first metal layer 16, the first metal layer are formed above the dielectric layer 15
16 connect to form source electrode through the dielectric layer 15 with the source region 13；Second metal layer is formed above the dielectric layer 15
17, the second metal layer 17 connect to form grid through the dielectric layer 15 with the fourth epitaxial layer 5；Under the substrate
Surface forms third metal layer 18, and the third metal layer 18 connect to form drain electrode with the substrate.
A kind of power device provided in an embodiment of the present invention is described in detail below in conjunction with Fig. 1 to Fig. 7.
The embodiment of the present invention provides a kind of power device, and the power device includes:
The substrate of first conduction type；
It is formed in the first epitaxial layer 2 of the first conduction type of the upper surface of substrate；
It is formed in the groove 6 of 2 upper surface of the first epitaxial layer；
It is formed in the first silicon oxide layer 10 of 6 bottom and side wall of groove；
It is formed in the first polysilicon layer 7 of the first oxidation layer surface；
It is formed in the second silicon oxide layer 11 of 7 side wall of the first polysilicon layer；
The third silicon oxide layer 12 being formed in 2 upper surface of the first epitaxial layer, the one of the third silicon oxide layer 12
End is connect with first silicon oxide layer 10, and the other end of the third silicon oxide layer 12 and second silicon oxide layer 11 connect
It connects；
In the part that first polysilicon layer 7 is not covered by second silicon oxide layer 11, injection ion is formed
Second polysilicon layer 8 of the first conduction type；
It is formed in the second epitaxial layer 3 of the second conduction type of 8 upper surface of the second polysilicon layer；
It is formed in the third epitaxial layer 4 of the first conduction type of 3 upper surface of the second epitaxial layer；
It is respectively formed in the fourth epitaxial layer 5 and third polycrystalline of the second conduction type of 4 upper surface of third epitaxial layer
Silicon layer 9, the third polysilicon layer 9 are located at the two sides of the fourth epitaxial layer 5；
It is formed in the body area 14 of the second conduction type in first epitaxial layer 2, at least partly table in the body area 14
Face is exposed to the upper surface of first epitaxial layer 2, and the one end in the body area 14 is connect with first silicon oxide layer 10；
The source region 13 being formed in the body area 14, at least partly surface exposure of the source region 13 is in first extension
The upper surface of layer 2, one end of the source region 13 is connect with first silicon oxide layer 10；
It is formed in the dielectric layer 15 of 2 upper surface of the first epitaxial layer；
It is formed in the first metal layer 16 of 15 top of dielectric layer, the first metal layer 16 runs through the dielectric layer 15
It connect to form source electrode with the source region 13；
It is formed in the second metal layer 17 of 15 top of dielectric layer, the second metal layer 17 runs through the dielectric layer 15
It connect to form grid with the fourth epitaxial layer 5；
It is formed in the third metal layer 18 of the substrate lower surface, the third metal layer 18 connect to be formed with the substrate
Drain electrode.
Technical solution of the present invention is related to designing and manufacturing for semiconductor devices, and semiconductor refers to that a kind of electric conductivity can be controlled
System, conductive extensions can be from insulator to the material changed between conductor, and common semiconductor material has silicon, germanium, GaAs etc., and
Silicon is most powerful, one kind for being most widely used in various semiconductor materials.Semiconductor is divided into intrinsic semiconductor, p-type
Semiconductor and N-type semiconductor, free from foreign meter and without lattice defect semiconductor is known as intrinsic semiconductor, in pure silicon crystal
It mixes triad (such as boron, indium, gallium), is allowed to replace the seat of silicon atom in lattice, P-type semiconductor is just formed, pure
Silicon crystal in mix pentad (such as phosphorus, arsenic), be allowed to replace the position of silicon atom in lattice, be formed N-type and partly lead
The conduction type of body, P-type semiconductor and N-type semiconductor is different, and in an embodiment of the present invention, the first conduction type is N-type, the
Two conduction types are p-type, in an embodiment of the present invention, if not otherwise specified, the preferred doping of every kind of conduction type from
Son is all that can be changed to the ion with same conductivity type, is just repeated no more below.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate 1, or Sapphire Substrate 1 can also be
Silicon carbide substrates 1, it might even be possible to be silicon Chu substrate 1, it is preferred that the substrate 1 is silicon substrate 1, this is because 1 material of silicon substrate
Have the characteristics that low cost, large scale, conductive, avoids edge effect, yield can be increased substantially.In reality of the invention
Apply in example, the substrate 1 is the substrate 1 of the first conduction type, and first conduction type is N-type, the doping of the substrate 1 from
Son is phosphorus or arsenic etc., and 1 doping concentration of substrate is highly doped.
Referring next to attached drawing, power device described above is elaborated.
In some embodiments of the invention, as shown in Fig. 2, the power device includes the substrate 1 of the first conduction type；
It is formed in the first epitaxial layer 2 of the first conduction type of 1 upper surface of substrate.The doping concentration of the substrate 1 and described the
The doping concentration of one epitaxial layer 2 is different.Preferably, the doping concentration of the substrate 1 is dense higher than the doping of first epitaxial layer 2
Degree, the resistivity of substrate 1 described in the resistivity ratio of first epitaxial layer 2 is high at this time, reduces dead resistance, to improve device
The breakdown reverse voltage of part.
In some embodiments of the invention, as shown in figure 3, the power device includes being formed in first epitaxial layer
The groove 6 of 2 upper surfaces；It is formed in the first silicon oxide layer 10 of 6 bottom and side wall of groove.The silicon oxide layer is insulation
Layer, sputtering can be used in the silicon oxide layer or thermal oxide is formed.In some embodiments of the invention, the silicon oxide layer is
Thermal oxide is formed, and in subsequent doping step, the silicon oxide layer is as protective layer, and by the interlayer as resulting devices
Insulating layer.
In some embodiments of the invention, as shown in figure 4, the power device includes being formed in first oxide layer
First polysilicon layer 7 on surface.It is formed more than described first on the surface of first oxide layer by the method for extension or diffusion
Crystal silicon layer 7.Specifically, the extension or the method for diffusion include depositing operation.In some embodiments of the invention, can make
The first polysilicon layer 7 is formed on the surface of first oxide layer with depositing operation, for example, depositing operation can be selected from electronics
One of beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering.Preferably, it is used on the surface of first oxide layer
Low-pressure chemical vapor deposition (abbreviation LPCVD, i.e. Low Pressure Chemical Vapor Deposition) forms institute
State the first polysilicon layer 7, the purity is high of first polysilicon layer 7 of formation, uniformity is good.Further, more than described first
The thickness of crystal silicon layer 7 is greater than 300 nanometers.
In some embodiments of the invention, as shown in figure 5, the power device includes being formed in first polysilicon
Second silicon oxide layer 11 of 7 side wall of layer；The third silicon oxide layer 12 being formed in 2 upper surface of the first epitaxial layer, described
One end of three silicon oxide layers 12 is connect with first silicon oxide layer 10, the other end of the third silicon oxide layer 12 and described the
Silicon dioxide layer 11 connects.The silicon oxide layer is insulating layer, and sputtering can be used in the silicon oxide layer or thermal oxide is formed.?
In some embodiments of the present invention, the silicon oxide layer is formed for thermal oxide, in subsequent doping step, the silicon oxide layer
As protective layer, and by the interlayer insulating film as resulting devices.Second silicon oxide layer 11 is received with a thickness of 50-100
Rice.
In some embodiments of the invention, as shown in figure 5, the power device is included in first polysilicon layer 7
Second polysilicon layer of the first conduction type that the part injection ion not covered by second silicon oxide layer 11 is formed
8。
In some embodiments of the invention, as shown in fig. 6, the power device includes being formed in second polysilicon
Second epitaxial layer 3 of the second conduction type of 8 upper surface of layer；It is formed in the first conductive-type of 3 upper surface of the second epitaxial layer
The third epitaxial layer 4 of type.Further, the power device includes outside multiple second epitaxial layers 3 and multiple thirds
Prolong layer 4, second epitaxial layer 3 and the setting of the third epitaxial layer 4 interval.Due to second epitaxial layer 3 and the third
The ionic species of epitaxial layer 4 is different, by the PN junction of formation, increases the voltage endurance capability of power device, multiple second extensions
Layer 3 and the multiple interval of third epitaxial layer 4 settings can be further improved the resistance to pressure of power device, outside described second
The setting number for prolonging layer 3 and the third epitaxial layer 4 can be depending on demand of the power device for resistance to pressure.Further
Ground, the ion concentration of the third epitaxial layer 4 are lower than the ion concentration of first epitaxial layer 2.The described in such structure setting
The resistivity of three epitaxial layers 4 is higher than first epitaxial layer 2, and the resistance to pressure of power device can be improved.
In some embodiments of the invention, as shown in fig. 6, the power device includes being respectively formed in outside the third
Prolong the fourth epitaxial layer 5 and third polysilicon layer 9 of the second conduction type of 4 upper surface of layer, the third polysilicon layer 9 is located at institute
State the two sides of fourth epitaxial layer 5.The fourth epitaxial layer 5 and 9 upper surface of third polysilicon layer and first epitaxial layer 2
Upper surface substantially maintain an equal level.In some embodiments, substantially maintain an equal level and refer to the fourth epitaxial layer 5 and the third polysilicon layer
9 upper surfaces are higher than 2 upper surface of the first epitaxial layer, and the fourth epitaxial layer 5 and the third are more in further embodiments
9 upper surface of crystal silicon layer can also be lower than 2 upper surface of the first epitaxial layer, and the difference in height of the two is specially that can connect in technical process
In the error range received.As shown in the wherein sectional view of structure in Fig. 6 power device manufacturing process, the third polysilicon layer 9
Positioned at 5 two sides of fourth epitaxial layer, two sides of the fourth epitaxial layer 5 are covered.Further, the fourth epitaxial
The ion concentration of layer 5 is higher than the ion concentration of second epitaxial layer 3.The resistance of fourth epitaxial layer 5 described in such structure setting
Rate is lower than second epitaxial layer 3, reduces the parasitic capacitance of power device.
In some embodiments of the invention, as shown in fig. 6, the power device includes being formed in first epitaxial layer
The body area 14 of the second conduction type in 2, at least partly surface exposure in the body area 14 is in the upper table of first epitaxial layer 2
Face, the one end in the body area 14 are connect with first silicon oxide layer 10；The source region 13 being formed in the body area 14, the source
At least partly surface exposure in area 13 is in the upper surface of first epitaxial layer 2, one end of the source region 13 and first oxygen
SiClx layer 10 connects；It is formed in the dielectric layer 15 of 2 upper surface of the first epitaxial layer；It is formed in the of 15 top of the dielectric layer
One metal layer 16, the first metal layer 16 connect to form source electrode through the dielectric layer 15 with the source region 13；It is formed in institute
The second metal layer 17 of 15 top of dielectric layer is stated, the second metal layer 17 is through the dielectric layer 15 and the fourth epitaxial layer
5 connections form grid；It is formed in the third metal layer 18 of the substrate lower surface, the third metal layer 18 connects with the substrate
It connects to form drain electrode.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, according to the technical solution of the present invention, proposes one
The power device chip of kind trench-gate integrated static safeguard structure, by being spaced the multiple and different conduction types of setting in the trench
Epitaxial layer and the PN junction that is formed play a protective role to the grid of power device, improve the voltage endurance capability of power device, such as
This power device that multiple epitaxial layers are arranged in the trench avoids Conventional power devices and needs by encapsulating and device being protected to connect
The method connect, reduces device area, reduces encapsulation manufacturing cost, improves product reliability.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of production method of power device characterized by comprising
The substrate of first conduction type is provided；
Surface forms the first epitaxial layer of the first conduction type over the substrate；
Groove is formed in first epitaxial layer upper surface；
The first silicon oxide layer is formed in the bottom and side wall of the groove；
The first polysilicon layer is formed on the surface of first oxide layer；
The second silicon oxide layer is formed in the side wall of first polysilicon layer；
Third silicon oxide layer, one end of the third silicon oxide layer and described first are formed in first epitaxial layer upper surface
Silicon oxide layer connection, the other end of the third silicon oxide layer are connect with second silicon oxide layer；
In the part that first polysilicon layer is not covered by second silicon oxide layer, it is conductive to form first for injection ion
Second polysilicon layer of type；
The second epitaxial layer of the second conduction type is formed in second polysilicon layer upper surface；
The third epitaxial layer of the first conduction type is formed in second epitaxial layer upper surface；
It is respectively formed the fourth epitaxial layer and third polysilicon layer of the second conduction type in third epitaxial layer upper surface, it is described
Third polysilicon layer is located at the two sides of the fourth epitaxial layer；
The body area of the second conduction type is formed in first epitaxial layer, at least partly surface exposure in the body area is in described
The upper surface of first epitaxial layer, the one end in the body area are connect with first silicon oxide layer；
Form source region in the body area, at least partly surface exposure of the source region in the upper surface of first epitaxial layer,
One end of the source region is connect with first silicon oxide layer；
Dielectric layer is formed in first epitaxial layer upper surface；
The first metal layer is formed above the dielectric layer, the first metal layer is connect through the dielectric layer with the source region
Form source electrode；
Second metal layer is formed above the dielectric layer, the second metal layer is through the dielectric layer and the fourth epitaxial
Layer connection forms grid；
Third metal layer is formed in the substrate lower surface, the third metal layer connect to form drain electrode with the substrate.
2. the production method of power device according to claim 1, which is characterized in that the power device includes multiple institutes
State the second epitaxial layer and multiple third epitaxial layers, second epitaxial layer and the setting of third epitaxial layer interval.
3. the production method of power device according to claim 1, which is characterized in that the ion of the third epitaxial layer is dense
Degree is lower than the ion concentration of first epitaxial layer.
4. the production method of power device according to claim 1, which is characterized in that the ion of the fourth epitaxial layer is dense
Degree is higher than the ion concentration of second epitaxial layer.
5. the production method of power device according to claim 1, which is characterized in that do not have in first polysilicon layer
The part injection ion covered by second silicon oxide layer forms the second polysilicon layer of the first conduction type, specific to wrap
It includes:
The first conduction type is not implanted sequentially by the part that second silicon oxide layer is covered in first polysilicon layer
Ion, argon ion and oxonium ion；
First polysilicon layer upper surface described in hydrofluoric acid clean using 10%；
Short annealing, annealing temperature are 900 DEG C, and the time is 30 seconds.
6. the production method of power device according to claim 1, which is characterized in that the thickness of first polysilicon layer
Greater than 300 nanometers.
7. a kind of power device characterized by comprising
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type of the upper surface of substrate；
It is formed in the groove of first epitaxial layer upper surface；
It is formed in the first silicon oxide layer of the channel bottom and side wall；
It is formed in the first polysilicon layer of the first oxidation layer surface；
It is formed in the second silicon oxide layer of the first polysilicon layer side wall；
The third silicon oxide layer being formed in first epitaxial layer upper surface, one end of the third silicon oxide layer and described the
One silica layer connection, the other end of the third silicon oxide layer are connect with second silicon oxide layer；
It is not led by the first of the part injection ion formation that second silicon oxide layer is covered in first polysilicon layer
Second polysilicon layer of electric type；
It is formed in the second epitaxial layer of the second conduction type of second polysilicon layer upper surface；
It is formed in the third epitaxial layer of the first conduction type of second epitaxial layer upper surface；
It is respectively formed in the fourth epitaxial layer and third polysilicon layer of the second conduction type of third epitaxial layer upper surface, institute
State the two sides that third polysilicon layer is located at the fourth epitaxial layer；
It is formed in the body area of the second conduction type in first epitaxial layer, at least partly surface exposure in the body area is in institute
The upper surface of the first epitaxial layer is stated, the one end in the body area is connect with first silicon oxide layer；
The source region being formed in the body area, at least partly surface exposure of the source region is in the upper table of first epitaxial layer
Face, one end of the source region are connect with first silicon oxide layer；
It is formed in the dielectric layer of first epitaxial layer upper surface；
The first metal layer being formed in above the dielectric layer, the first metal layer connect through the dielectric layer and the source region
It connects to form source electrode；
The second metal layer being formed in above the dielectric layer, the second metal layer is outside the dielectric layer and the described 4th
Prolong layer to connect to form grid；
It is formed in the third metal layer of the substrate lower surface, the third metal layer connect to form drain electrode with the substrate.
8. power device according to claim 7, which is characterized in that the power device includes multiple second extensions
Layer and multiple third epitaxial layers, second epitaxial layer and the setting of third epitaxial layer interval.
9. power device according to claim 7, which is characterized in that the ion concentration of the third epitaxial layer is lower than described
The ion concentration of first epitaxial layer.
10. power device according to claim 7, which is characterized in that the ion concentration of the fourth epitaxial layer is higher than institute
State the ion concentration of the second epitaxial layer.
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| CN116779662A (en) * | 2023-08-22 | 2023-09-19 | 深圳芯能半导体技术有限公司 | An antistatic IGBT chip and its manufacturing method |
| CN119170650A (en) * | 2024-11-07 | 2024-12-20 | 江西萨瑞微电子技术有限公司 | A trench type power device and a method for manufacturing the same |
| CN119277805A (en) * | 2024-12-04 | 2025-01-07 | 珠海格力电子元器件有限公司 | Trench power device and method for preparing trench power device |
| CN119300407A (en) * | 2024-12-04 | 2025-01-10 | 珠海格力电子元器件有限公司 | Trench MOS device and preparation method thereof |
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