CN109309006A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN109309006A CN109309006A CN201710622886.7A CN201710622886A CN109309006A CN 109309006 A CN109309006 A CN 109309006A CN 201710622886 A CN201710622886 A CN 201710622886A CN 109309006 A CN109309006 A CN 109309006A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000012545 processing Methods 0.000 claims abstract description 45
- 238000004380 ashing Methods 0.000 claims abstract description 42
- 238000006701 autoxidation reaction Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000003068 static effect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 53
- 235000012431 wafers Nutrition 0.000 description 13
- 238000011161 development Methods 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- -1 silicon nitride compound Chemical class 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000004615 ingredient Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor devices and forming method thereof, the forming method of the semiconductor devices includes: offer semiconductor substrate；Grid is formed on the semiconductor substrate；Offset side wall is formed on the side wall of the grid, the offset side wall includes original side wall and the oxide layer positioned at the original side wall side wall, and the oxide layer is since autoxidation generates；Ashing processing is carried out to the oxide layer, so that the offset side wall has stable thickness.The present invention program can carry out that ion implanting operation is lightly doped without artificial compensation, while effectively improving wafer manufacture efficiency, avoid the increase of manufacturing cost and human cost before the autoxidation of the oxide layer of offset side wall saturation.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
With the continuous development of semiconductor processing technology, integrated circuit integrated level is higher and higher, the feature of semiconductor devices
Size is also smaller and smaller, such as with the shortening of grid length, is easy to happen short-channel effect (Short Channel
Effect, SCE) to increase charge break-through between source and drain, and then influence proper device operation.
At this stage in order to reduce short-channel effect, generallys use offset side wall (Offset Spacer) and increases channel length,
Since the ingredient of the side wall of offset side wall is silicon nitride compound, it is straight that the silicon nitride compound meeting continued oxidation generates oxide layer
To saturation, therefore the thickness of offset side wall is also being continually increased until that thickness stablizes.Ion implanting leakage is being lightly doped using subsequent
Pole (Lightly Doped Drain, LDD) technique is carried out during ion implanting is lightly doped, is needed according to inclined after stabilization
The thickness for moving side wall, carries out that ion implanting is lightly doped between adjacent offset side wall, close to guarantee to have between different wafers
Be lightly doped ion implanted region domain sizes, namely need to be arranged from formed offset side wall to carry out between LDD photoetching process etc.
To duration (for example, 45 hours or so), wafer manufacture efficiency is caused to decline.
In the prior art, it when needing within waiting time to carry out that ion implanting is lightly doped, is often mended using artificial
The method repaid reduces the peak width for carrying out that ion implanting is lightly doped between adjacent offset side wall.But the side of artificial compensation
Method needs operator to have professional knowledge abundant and judgement experience, and increases LDD photoetching process trial operation (Pi-run)
Processing procedure cost and human cost.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor devices and forming method thereof, can be in offset side wall
Before the autoxidation saturation of oxide layer, it can carry out that ion implanting operation is lightly doped without artificial compensation, effectively improve crystalline substance
While circle manufacture efficiency, the increase of manufacturing cost and human cost is avoided.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of semiconductor devices, comprising: provide
Semiconductor substrate；Grid is formed on the semiconductor substrate；Offset side wall, the offset are formed on the side wall of the grid
Side wall includes original side wall and the oxide layer positioned at the original side wall side wall, and the oxide layer is since autoxidation generates
's；Ashing processing is carried out to the oxide layer, so that the offset side wall has stable thickness.
Optionally, carrying out ashing processing to the oxide layer includes: to be ashed using nitrogenous gas to the oxide layer
Processing, to consume the oxide layer and generate nitride.
Optionally, the nitrogenous gas includes N2H2And N2。
Optionally, the ashing temperature for carrying out ashing processing to the oxide layer is 265 degrees Celsius to 285 degrees Celsius.
Optionally, the ashing processing is completed before the autoxidation saturation time of the oxide layer.
Optionally, after carrying out ashing processing to the oxide layer, the forming method of the semiconductor devices further include:
Between adjacent offset side wall, the semiconductor substrate is carried out ion implanting is lightly doped.
Optionally, described between adjacent offset side wall, the semiconductor substrate is carried out ion implanting packet is lightly doped
Include: the exposure mask of ion implanting is lightly doped in the photoresist layer of the formation covering grid and the offset side wall as described in；With institute
Stating photoresist layer is that ion implanting is lightly doped to described in semiconductor substrate progress in exposure mask.
Optionally, the semiconductor substrate includes first area and second area, is gently mixed the semiconductor substrate
Heteroion injection includes: to carry out that ion implanting is lightly doped to the first area；Wherein, the first area is used to form static state
RAM device, the second area are used to form input/output device.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of semiconductor devices, comprising: semiconductor substrate；Grid
Pole is located in the semiconductor substrate；Offset side wall, the offset side wall include original side wall and be located at the original side wall
Side wall coating, the coating is to carry out ashing by the oxide layer of the side wall to the original side wall to handle to obtain
, the oxide layer is since autoxidation generates.
Optionally, the material of the coating includes: nitride.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In embodiments of the present invention, semiconductor substrate is provided；Grid is formed on the semiconductor substrate；In the grid
Side wall on form offset side wall, the offset side wall includes original side wall and the oxidation positioned at the original side wall side wall
Layer, the oxide layer is since autoxidation generates；Ashing processing is carried out to the oxide layer, so that the offset side wall has
There is stable thickness.Using the above scheme, the oxide layer for the original side wall side wall for being located at offset side wall can be carried out at ashing
Reason, compared with the prior art in, the oxide layer due to autoxidation generate, thickness autoxidation saturation before persistently become
Change, causes the oxide layer of different growth durations that there is different thickness, cause different offset side wall thickness inconsistent, using this
The scheme of inventive embodiments generates thinner thickness and the stable nitrogen of thickness since the oxide layer of different-thickness is ashed after processing
Compound can make different offset side walls have stable thickness, help to reduce inside single wafer or different wafer it
Between offset side wall difference in thickness, to mitigate the influence that generates to subsequent technique.
Further, in embodiments of the present invention, N can be used2H2And N2Ashing processing is carried out under preset temperature, is passed through
It consumes the oxide layer and generating nitride makes the offset side wall have stable thickness, existing be used for can also be multiplexed
The ashing treatment process of photoresist is removed, to reduce the technique research and development pressure for new processing procedure.
Further, in embodiments of the present invention, oxide layer can be ashed before carrying out that ion implanting is lightly doped
Processing, since oxide layer stops growing, helps so that the various semiconductor devices formed on the semiconductor substrate all obtain
Obtain better device performance.
Further, since static random access memory devices need that higher that ion implanted region domain sizes are lightly doped is consistent
Property, it in embodiments of the present invention, can be before carrying out SRAM device and ion implanting be lightly doped, to the side wall for being located at primary side wall
Oxide layer carry out ashing processing, facilitate the device performance for obtaining better SRAM device.
Detailed description of the invention
Fig. 1 is a kind of flow chart of method for forming semiconductor devices in the embodiment of the present invention；
Fig. 2 to Fig. 4 is a kind of the schematic diagram of the section structure of method for forming semiconductor devices in the embodiment of the present invention；
Fig. 5 to Fig. 6, which is that the part steps of the forming method of another semiconductor devices in the embodiment of the present invention are corresponding, to be cutd open
The schematic diagram of face structure；
Fig. 7 is the instrumentation plan of inspection size after a kind of development in the prior art；
Fig. 8 is the instrumentation plan for checking size in the embodiment of the present invention after a kind of development；
Fig. 9 to Figure 10, which is that the part steps of the forming method of another semiconductor devices in the embodiment of the present invention are corresponding, to be cutd open
The schematic diagram of face structure.
Specific embodiment
At this stage in order to reduce short-channel effect, generallys use offset side wall (Offset Space) and increases channel length,
Since the side wall ingredient of offset side wall is silicon nitride compound, the silicon nitride compound can continued oxidation generate oxide layer until
Saturation, therefore the thickness of offset side wall is also being continually increased until that thickness is stable.During carrying out that ion implanting is lightly doped,
It needs to be arranged from offset side wall is formed to the waiting time be lightly doped between ion implanting, cause under wafer manufacture efficiency
Drop.
In the prior art, when needing within the waiting time to carry out that ion implanting is lightly doped, one kind of use
Method is to increase exposure area in the LDD photoetching process before carrying out that ion implanting is lightly doped by artificial compensation, to reduce
The peak width that ion implanting is lightly doped is carried out between adjacent offset side wall.Specifically, more early carry out that ion note is lightly doped
Enter, the dynamics of artificial compensation is bigger, that is, needs that bigger exposure area is arranged.
But the method for artificial compensation needs operator to have professional knowledge abundant and judgement experience, and increases
The processing procedure cost and human cost of LDD photoetching process trial operation.Therefore, wafer manufacture efficiency can improved by needing a kind of method
While, avoid the increase of processing procedure cost and human cost.
In embodiments of the present invention, semiconductor substrate is provided；Grid is formed on the semiconductor substrate；In the grid
Side wall on form offset side wall, the offset side wall includes original side wall and the oxidation positioned at the original side wall side wall
Layer, the oxide layer is since autoxidation generates；Ashing processing is carried out to the oxide layer, so that the offset side wall has
There is stable thickness.Using the above scheme, the oxide layer for the original side wall side wall for being located at offset side wall can be carried out at ashing
Reason, compared with the prior art in, the oxide layer due to autoxidation generate, thickness autoxidation saturation before persistently become
Change, causes the oxide layer of different growth durations that there is different thickness, cause different offset side wall thickness inconsistent, using this
The scheme of inventive embodiments generates the nitride of thinner thickness since the oxide layer of different-thickness is ashed after processing, can be with
Make different offset side walls that there is stable thickness, helps to reduce offset side wall between single wafer inside or different wafers
Difference in thickness, to mitigate the influence that generates to subsequent technique.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 1 is a kind of flow chart of method for forming semiconductor devices in the embodiment of the present invention.The semiconductor devices is formed
Method may include step S101 to step S104:
Step S101: semiconductor substrate is provided；
Step S102: grid is formed on the semiconductor substrate；
Step S103: forming offset side wall on the side wall of the grid, the offset side wall include original side wall and
Positioned at the oxide layer of the original side wall side wall, the oxide layer is since autoxidation generates；
Step S104: carrying out ashing processing to the oxide layer, so that the offset side wall has stable thickness.
Above-mentioned each step is illustrated below with reference to Fig. 2 to Fig. 4.
Referring to Fig. 2, semiconductor substrate 100 is provided, grid 130 is formed in the semiconductor substrate 100, in the grid
The original side wall 110 of offset side wall is formed on 130 side wall.
In embodiments of the present invention, the semiconductor substrate 100 is silicon substrate.In other embodiments, the semiconductor
The material of substrate 100 can also be silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium, and the semiconductor substrate 100 may be used also
Think the germanium substrate on the silicon substrate or insulator on insulator.
The grid 130 can gate oxide, polysilicon on the surface by being sequentially formed at the semiconductor substrate 100
Layer is constituted with cap layer, be can also be high-dielectric coefficient metal gates (High-k metal gate, HKMG), be can also be fin
Covering protrudes from semiconductor substrate surface in formula field effect transistor (Fin Field Effect Transistor, FinFET)
Fin top and side wall grid.It should be pointed out that in embodiments of the present invention, for forming the specific of grid 130
Mode is with no restriction.
The original side wall 110 of offset side wall, the original side wall of the offset side wall are formed on the side wall of the grid 130
110 material can be silicon nitride.
In specific implementation, the offset side wall for covering the semiconductor substrate 100 and the grid 130 can be initially formed
Layer, then the offset side wall layer is performed etching, to form the original side wall 110 being retained on the side wall of the grid 130.
Referring to Fig. 3, offset side wall 114 includes the oxidation of original side wall 110 and the side wall positioned at the original side wall 110
Layer 111, the oxide layer 111 are and to be properly termed as native oxide layer since autoxidation generates.
Specifically, after performing etching to the offset side wall layer, original side wall 110 is formed, the ingredient of side wall is nitrogen
SiClx compound, to improve the consistency of the original side wall 110.
Further, the silicon nitride compound meeting autoxidation generates oxide layer 111 until saturation, duration is by having
The making technology of body and determine, in a certain specific embodiment, can be 45 hours or so.It is described in the duration
The thickness of oxide layer 111 persistently changes, and the thickness of the offset side wall 114 is also in lasting variation.
Conventionally, as the thickness of the offset side wall 114 persistently changes, cause adjacent offset side wall 114 it
Between distance it is inconsistent, carry out that ion implanting is lightly doped at this time between adjacent offset side wall 114, be easy to cause and ion is lightly doped
Different location in same semi-conductive substrate 100 (such as wafer) can occur for injection zone size difference, the size difference
On, or occur between different semiconductor substrates (such as wafer).
Referring to Fig. 4, ashing processing is carried out to the oxide layer 111 (referring to Fig. 3), so that the offset side wall 114 has
Stable thickness.
In specific implementation, carrying out ashing processing to oxide layer may include: to carry out ash to oxide layer using nitrogenous gas
Change processing, to consume oxide layer and generate nitride 112.Thickness is generated after being ashed processing due to the oxide layer of different-thickness
Relatively thin and stable thickness nitride 112, can make different offset side walls have stable thickness, and difference in thickness compared with
It is small.
Specifically, the nitrogenous gas may include N2H2And N2。
The ashing temperature for carrying out ashing processing to the oxide layer is 265 degrees Celsius to 285 degrees Celsius.It preferably, can be with
Using 270 degrees Celsius, 275 degrees Celsius or 280 degrees Celsius.
In embodiments of the present invention, N can be used2H2And N2Ashing processing is carried out under preset temperature, by described in consumption
Oxide layer 111 (referring to Fig. 3) and generate nitride 112 make the offset side wall 114 have stable thickness, can also be multiplexed
The existing ashing treatment process for being used to remove photoresist, to reduce the technique research and development pressure for new processing procedure.
Further, the ashing processing is before the autoxidation saturation time of the oxide layer 111 (referring to Fig. 3)
It completes.Specifically, the thickness of offset side wall is continuing to increase before the autoxidation saturation time of oxide layer, at this time into
Row ashing helps that offset side wall is made to have stable thickness, and improves the consistency of thickness of different offset side walls.
In embodiments of the present invention, the oxide layer for the original side wall side wall for being located at offset side wall can be carried out at ashing
Reason, compared with the prior art in, the oxide layer due to autoxidation generate, thickness autoxidation saturation before persistently become
Change, causes the oxide layer of different growth durations that there is different thickness, cause different offset side wall thickness inconsistent, using this
The scheme of inventive embodiments generates thinner thickness and the stable nitrogen of thickness since the oxide layer of different-thickness is ashed after processing
Compound can make different offset side walls have stable thickness, help to reduce inside single wafer or different wafer it
Between offset side wall difference in thickness, to mitigate the influence that generates to subsequent technique.
Fig. 5 to Fig. 6, which is that the part steps of the forming method of another semiconductor devices in the embodiment of the present invention are corresponding, to be cutd open
The schematic diagram of face structure.
Referring to Fig. 5, grid 230 is formed on semiconductor substrate 200, and offset side wall is formed on the side wall of grid 230
Original side wall 210.Offset side wall 214 includes the nitride of original side wall 210 and the side wall positioned at the original side wall 210
212.The nitride is to carry out ashing by the oxide layer of the side wall to the original side wall 210 to handle, the oxygen
Changing layer is since autoxidation generates.
After carrying out ashing processing to the oxide layer, the forming method of the semiconductor devices further includes adjacent
Between offset side wall 214, the semiconductor substrate 200 is carried out that ion implanting 222 is lightly doped.
Specifically, semiconductor substrate 200 is carried out that ion implanting 222 is lightly doped to may include: to form the covering grid
230 and the photoresist layer 220 of the offset side wall 214 exposure mask of ion implanting 222 is lightly doped as described in；With the photoresist
Layer 220 carries out the semiconductor substrate 200 for exposure mask described ion implanting 222 to be lightly doped.
Referring to Fig. 6, is formed in the semiconductor substrate 200 of 230 side of grid and ion implanted regions 224 are lightly doped.
Specifically, ion implantation technology can be used, ion implanted regions 224 are lightly doped in formation.
In embodiments of the present invention, ashing processing can be carried out to oxide layer before carrying out that ion implanting is lightly doped, by
It stops growing in oxide layer, helps so that the various semiconductor devices formed in the semiconductor substrate 200 all obtain more
Good device performance.
It is the instrumentation plan of inspection size after a kind of development in the prior art referring to Fig. 7, Fig. 7.
Specifically, it after forming the photoresist layer 220 of covering grid and offset side wall, needs by being checked after development
(After Development Inspection, ADI) technology detects the size of photoresist layer 220, to determine with photoresist layer
Whether 220 area sizes that ion implanting is lightly doped formed for exposure mask meet the requirements.
As shown in fig. 7, then forming patterned photoresist layer since the offset side wall thickness on each gate lateral wall is different
It when 220, is easy to happen that boundary is uneven, leads to occur after exposure development asking for photoresist dross effect and ADI measurement inaccuracy
Topic.
Wherein, due to checking size 701 after the development that will obtain based on exposure mask width measurement less than normal, and based on bigger than normal
It checks that size 711 is compared, and is differed greatly after the development that exposure mask width measurement obtains, leads to the wound of ADI measurement formula (recipe)
Build difficulty increase.
Fig. 8 is the instrumentation plan for checking size in the embodiment of the present invention after a kind of development.As shown in figure 8, each grid
Offset side wall consistency of thickness on side wall, photoresist dross effect reduce, and help to improve the measurement of inspection size 801 after development
Accuracy.
The other content of the related forming method to another semiconductor devices shown in Fig. 5 to Fig. 8, please refers to Fig. 1
To the description of the forming method of the semiconductor devices shown in Fig. 4, details are not described herein again.
Fig. 9 to Figure 10, which is that the part steps of the forming method of another semiconductor devices in the embodiment of the present invention are corresponding, to be cutd open
The schematic diagram of face structure.
Referring to Fig. 9, grid 330 is formed in semiconductor substrate 300, and offset side wall is formed on the side wall of grid 330
Original side wall 310.Offset side wall 314 includes the nitride of original side wall 310 and the side wall positioned at the original side wall 310
312.The nitride is to carry out ashing by the oxide layer of the side wall to the original side wall 310 to handle, the oxygen
Changing layer is since autoxidation generates.
The semiconductor substrate 300 may include first area A and second area B, carry out at ashing to the oxide layer
After reason, to the semiconductor substrate 300 carry out the step of ion implanting is lightly doped may include: to the first area A into
Ion implanting is lightly doped in row；Wherein, the first area A is used to form static random access memory devices (Static Random
Access Memory, SRAM), the second area B is used to form input/output device (Input/Output, I/O).
Specifically, requirement of the different components for dimensional uniformity is different, by taking SRAM device and I/O device as an example, needs
In SRAM device region have it is higher ion implanted regions dimensional uniformity is lightly doped, and it also requires different wafers it
Between SRAM device region also have ion implanted regions dimensional uniformity be lightly doped.
Further, after carrying out ashing processing to oxide layer, covering grid 330, offset side wall 314 and institute are formed
The exposure mask of ion implanting 322 is lightly doped in the photoresist layer 320 for stating the second area B in semiconductor substrate 300 as described in；With institute
Stating photoresist layer 320 is that ion implanting 322 is lightly doped to described in the first area A progress in the semiconductor substrate 300 in exposure mask.
It further, can also include that other regions on second area B and semiconductor substrate 300 are lightly doped
The step (not shown) of ion implanting.
Specifically, the light of covering grid 330, offset side wall and the first area A in the semiconductor substrate 300 are formed
Photoresist layer (not shown) is as the exposure mask that ion implanting is lightly doped；It is exposure mask in the semiconductor substrate 300 using photoresist layer
Second area B carry out that ion implanting is lightly doped.Wherein, difference can be used in the first area A and second area B
Material carry out that ion implanting is lightly doped.
Referring to Fig.1 0, ion implanted regions 324 are lightly doped in the first area A formation in semiconductor substrate 300, are partly leading
Ion implanted regions 325 are lightly doped in second area B formation in body substrate 300.
Specifically, carrying out the step of ion implanting is lightly doped in first area A can carry out after the ashing process, namely
Ashing processing is carried out before carrying out SRAM device and ion implanting is lightly doped, there is higher be lightly doped in SRAM device to meet
The demand of ion implanted regions dimensional uniformity.
Wherein, it will be appreciated by persons skilled in the art that it includes shape that ion implanting, which is lightly doped, in the progress SRAM device
At photoresist layer be used as described in the exposure mask of ion implanting is lightly doped the step of.
It should be pointed out that being carried out if carrying out ion implanting is lightly doped the step of ratio in second area B in first area A
The step of ion implanting is lightly doped is early, then is not limited to carry out ashing processing before carrying out I/O device and ion implanting is lightly doped.?
I.e. in embodiments of the present invention, for carrying out the step of ion implanting is lightly doped in second area B and being ashed the successive suitable of processing
Sequence is with no restriction.
It in embodiments of the present invention, can be before carrying out SRAM device and ion implanting be lightly doped, to positioned at primary side wall
The oxide layer of 310 side wall carries out ashing processing, facilitates the device performance for obtaining better SRAM device.
The other content of the related forming method to another semiconductor devices shown in Fig. 9 to Figure 10, please refers to Fig. 1
To the description of the forming method of the semiconductor devices shown in Fig. 8, details are not described herein again.
The embodiment of the invention also provides a kind of semiconductor devices, may include: semiconductor substrate；Grid is located at described
In semiconductor substrate；Offset side wall, the offset side wall include original side wall and cover positioned at the side wall of the original side wall
Cap rock, the coating are to carry out ashing by the oxide layer of the side wall to the original side wall to handle, the oxidation
Layer is since autoxidation generates.
Further, the material of the coating may include nitride.
Referring to Fig. 6, the semiconductor devices may include semiconductor substrate 200, grid 230 and offset side wall 214.
Wherein, the grid 230 can be located in the semiconductor substrate 200, and the offset side wall 214 may include original
The coating 212 of beginning side wall 210 and the side wall positioned at the original side wall 210, the coating 212 are by the original
The oxide layer of the side wall of beginning side wall 210 carries out what ashing was handled, and the oxide layer is since autoxidation generates.
Later, it in the semiconductor substrate 200, can continue to complete to form semiconductor based on the offset side wall 214
The processing step of device.Specific processing step can be that well known to a person skilled in the art any appropriate processing steps, here
It repeats no more.
Related other descriptions to the semiconductor devices, please refer to the description of the forming method of above-mentioned semiconductor device,
Details are not described herein again.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided；
Grid is formed on the semiconductor substrate；
Form offset side wall on the side wall of the grid, the offset side wall includes original side wall and is located at the primary side
The oxide layer of wall side wall, the oxide layer are since autoxidation generates；
Ashing processing is carried out to the oxide layer, so that the offset side wall has stable thickness.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that be ashed to the oxide layer
Processing includes: to carry out ashing processing to the oxide layer using nitrogenous gas, to consume the oxide layer and generate nitride.
3. the forming method of semiconductor devices according to claim 2, which is characterized in that the nitrogenous gas includes N2H2
And N2。
4. the forming method of semiconductor devices according to claim 2, which is characterized in that be ashed to the oxide layer
The ashing temperature of processing is 265 degrees Celsius to 285 degrees Celsius.
5. the forming method of semiconductor devices according to claim 2, which is characterized in that the ashing processing is described
It is completed before the autoxidation saturation time of oxide layer.
6. the forming method of semiconductor devices according to claim 1, which is characterized in that be ashed to the oxide layer
After processing, further includes:
Between adjacent offset side wall, the semiconductor substrate is carried out ion implanting is lightly doped.
7. the forming method of semiconductor devices according to claim 6, which is characterized in that described in adjacent offset side wall
Between, the semiconductor substrate is carried out that ion implanting is lightly doped include:
The exposure mask of ion implanting is lightly doped in the photoresist layer of the formation covering grid and the offset side wall as described in；
Ion implanting is lightly doped to described in semiconductor substrate progress using the photoresist layer as exposure mask.
8. the forming method of semiconductor devices according to claim 6, which is characterized in that the semiconductor substrate includes the
One region and second area, the semiconductor substrate is carried out that ion implanting is lightly doped include:
The first area is carried out ion implanting is lightly doped；
Wherein, the first area is used to form static random access memory devices, and the second area is used to form input/defeated
Device out.
9. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Grid is located in the semiconductor substrate；
Offset side wall, the offset side wall includes the coating of original side wall and the side wall positioned at the original side wall, described
Coating is to carry out ashing by the oxide layer of the side wall to the original side wall to handle, and the oxide layer is due to certainly
So oxidation generates.
10. semiconductor devices according to claim 9, which is characterized in that the material of the coating includes:
Nitride.
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