CN109257024B

CN109257024B - Sensitive amplifier circuit

Info

Publication number: CN109257024B
Application number: CN201811144062.4A
Authority: CN
Inventors: 王鑫
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2018-09-29
Filing date: 2018-09-29
Publication date: 2022-06-17
Anticipated expiration: 2038-09-29
Also published as: CN109257024A

Abstract

The invention discloses a sensitive amplifier circuit, comprising: nine PMOS transistors, seven NMOS transistors, two capacitors, two inverters, an operational amplifier, a voltage-controlled current source and a storage unit; the first capacitor and the second capacitor control the compensation current of the first PMOS transistor and the second PMOS transistor; the memory cell current and the first voltage-controlled current source current influence the compensation current through the first capacitor and the second capacitor, and the effect of dynamically changing the compensation current is achieved. The invention can greatly increase the speed of the comparative current and realize a high-speed sensitive amplifier circuit.

Description

Sensitive amplifier circuit

Technical Field

The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a Sense Amplifier (SA) circuit.

Background

The traditional sensitive amplifier mainly realizes the effect of improving the speed by current comparison and matching with a latch acceleration method.

Fig. 1 shows a conventional sense amplifier circuit, which is composed of four PMOS transistors PM0 to PM3, six NMOS transistors NM0 to NM5, two capacitors C1 and C2, two voltage-controlled current sources DY1 and DY2, and an RS flip-flop RS.

The current lref is a current flowing out of the drain of the PMOS transistor PM1 into the node VD 0; the current lcell is the current flowing from the drain of PMOS transistor PM2 into node VD 1.

LATCH is a LATCH circuit, the reference memory cell CKDY is composed of a capacitor C1 and a voltage-controlled current source DY1 in fig. 1, and the reference memory cell CCDY is composed of a capacitor C2 and a voltage-controlled current source DY 2.

The waveform diagram of the circuit shown in fig. 1 is shown in fig. 2.

In the circuit shown in fig. 1, the voltage at the node VE during charging is VDD-Vt, VDD is the power supply voltage, and Vt is the threshold voltage of the PMOS transistor PM1, which has an influence on the charging speed, and the time for the latch circuit to accelerate becomes longer when Iref and Icell are closer to each other.

Disclosure of Invention

The invention aims to provide a sensitive amplifier circuit which can greatly increase the speed of comparison current and realize high-speed sensitive amplifier circuit.

To solve the above technical problem, the sense amplifier circuit of the present invention includes: nine PMOS transistors, seven NMOS transistors, two capacitors, two inverters, an operational amplifier, a voltage-controlled current source and a storage unit;

the source electrode of the first PMOS transistor, the source electrode of the fourth PMOS transistor, the drain electrode of the third PMOS transistor and the drain electrode of the second PMOS transistor are connected with a power supply voltage VDD end;

the source electrode of the third PMOS transistor is connected with the drain electrode of the first PMOS transistor, the connected node is marked as LD, the source electrode of the second PMOS transistor is connected with the drain electrode of the fourth PMOS transistor, and the connected node is marked as RD; one end of the first capacitor is connected with the node LD, the other end of the first capacitor is connected with the grid electrode of the second PMOS transistor, and the connected node is marked as RG; one end of the second capacitor is connected with the node RD, the other end of the second capacitor is connected with the grid electrode of the first PMOS transistor, and the connected node is marked as LG; a gate of the third PMOS transistor and a gate of the fourth PMOS transistor input a preparation signal PRE;

the inverting input end of the first operational amplifier is connected with the node LD, the non-inverting input end of the first operational amplifier is connected with the node RD, and the output end of the first operational amplifier is used as the output end OUT of the circuit;

the drain electrode of the first NMOS transistor is connected with a node LD, the source electrode of the first NMOS transistor is connected with the input end of the first phase inverter and one end of the storage unit, the connected node is marked as A, the other end of the storage unit is grounded, and the output end of the first phase inverter is connected with the grid electrode of the first NMOS transistor;

the source electrode of the second NMOS transistor is connected with a node RD, the drain electrode of the second NMOS transistor is connected with the input end of the second inverter and the positive end of the first voltage-controlled current source, the connected node is marked as B, and the negative end of the first voltage-controlled current source is grounded; the output end of the second inverter is connected with the grid electrode of the second NMOS transistor;

the drain electrode of the seventh PMOS transistor is connected with a power supply voltage end VDD, the grid electrode of the seventh PMOS transistor is input with an inverted enable signal SAENB, and the source electrode of the seventh PMOS transistor is connected with the source electrode of the fifth PMOS transistor and the drain electrode of the sixth PMOS transistor; the drain electrode of the fifth PMOS transistor, the grid electrode of the sixth PMOS transistor, the grid electrode of the fourth NMOS transistor and the source electrode of the third NMOS transistor are connected with a node LD; a source of the sixth PMOS transistor, a drain of the fourth NMOS transistor, a gate of the fifth PMOS transistor, and a gate of the third NMOS transistor NM3 are connected to a node RD;

the drain electrode of the third NMOS transistor is connected with the source electrode of the fourth NMOS transistor and the drain electrode of the fifth NMOS transistor, the grid electrode of the fifth NMOS transistor inputs an enabling signal SAEN, and the source electrode of the fifth NMOS transistor is grounded;

the source electrode of the eighth PMOS transistor is connected with the drain electrode of the sixth NMOS transistor and the node LG, the drain electrode of the eighth PMOS transistor is connected with the source electrode of the sixth NMOS transistor, and the bias voltage signal PBIAS of the PMOS transistor provided by the outside is input; a gate of the eighth PMOS transistor receives a ready signal PRE, and a gate of the sixth NMOS transistor receives a precharge signal PREB;

a source electrode of the ninth PMOS transistor is connected with a drain electrode of the seventh NMOS transistor and a node RG, a drain electrode of the ninth PMOS transistor is connected with a source electrode of the seventh NMOS transistor, and a bias voltage signal PBIAS of the PMOS transistor provided from the outside is input; the gate of the ninth PMOS transistor receives the ready signal PRE, and the gate of the seventh NMOS transistor receives the precharge signal PREB.

The invention greatly increases the speed of the comparative current on the premise of not sacrificing the charging speed. The purpose of high-speed SA is achieved.

By adopting the circuit of the invention, the currents (compensation currents) of the first PMOS transistor and the second PMOS transistor are controlled by the first capacitor and the second capacitor, and a fixed compensation current mirrored from the outside is not adopted any more, or a method for directly mirroring the current of the memory cell and the current of the voltage-controlled current source (the method can greatly reduce the charging speed) is adopted. The memory cell current and the first voltage-controlled current source current influence the compensation current through the first capacitor and the second capacitor, and the effect of dynamically changing the compensation current is achieved. Therefore, the speed of comparing the currents can be greatly improved, and the purpose of high-speed SA is achieved by matching the latch unit formed by the fifth PMOS transistor, the sixth PMOS transistor, the third NMOS transistor and the fourth NMOS transistor.

Drawings

The invention will be described in further detail with reference to the following detailed description and accompanying drawings:

FIG. 1 is a schematic diagram of a prior art sense amplifier circuit;

FIG. 2 is a waveform diagram of the sense amplifier circuit of FIG. 1;

FIG. 3 is a schematic diagram of one embodiment of an improved sense amplifier circuit;

FIG. 4 is a waveform diagram (one) of the sense amplifier circuit shown in FIG. 3;

fig. 5 is a waveform diagram (two) of the sense amplifier circuit shown in fig. 3.

Detailed Description

Referring to fig. 3, the improved sense amplifier circuit of the present invention includes, in the following embodiments: nine PMOS transistors PM 1-PM 9, seven NMOS transistors NM 1-NM 7, two capacitors C1 and C2, two inverters FX1 and FX2, an operational amplifier YF1, a voltage-controlled current source DY3 and a memory cell.

The sources of PMOS transistors PM1, PM4 and the drains of PMOS transistors PM3, PM2 are connected to the supply voltage terminal VDD.

The source of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM1, and the node at which it is connected is denoted as LD, and the source of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM4, and the node at which it is connected is denoted as RD. One end of the capacitor C1 is connected to the node LD, the other end is connected to the gate of the PMOS transistor PM2, and the connected node is denoted as RG; the capacitor C2 has one end connected to the node RD and the other end connected to the gate of the PMOS transistor PM1, and the node at which the capacitor C2 is connected is denoted as LG. The gate of the PMOS transistor PM3 and the gate of the PMOS transistor PM4 input the ready signal PRE. The capacitors C1, C2 and the PMOS transistors PM1, PM2 constitute a compensation current unit.

The inverting input terminal of the operational amplifier YF1 is connected to the node LD, the non-inverting input terminal thereof is connected to the node RD, and the output terminal thereof serves as the output terminal OUT of the circuit. The operational amplifier YF1 is an output unit of the circuit.

The drain of the NMOS transistor NM1 is connected to the node LD, the source thereof is connected to the input of the first inverter FX1 and one end of the memory cell, the node of the connection is denoted as a, and the other end of the memory cell is grounded. An output terminal of the first inverter FX1 is connected to a gate of the NMOS transistor NM 1. First inverter FX1 clamps the voltage at node a.

The source of the NMOS transistor NM2 is connected to the node RD, the drain thereof is connected to the input terminal of the second inverter FX2 and the positive terminal of the voltage-controlled current source DY3, the connected node is denoted as B, and the negative terminal of the voltage-controlled current source DY3 is grounded. An output terminal of the second inverter FX2 is connected to a gate of the NMOS transistor NM 2. The second inverter FX2 clamps the voltage at node B.

The drain of the PMOS transistor PM7 is connected to the power supply voltage terminal VDD, the gate thereof receives the inverted enable signal SAENB (a signal obtained by inverting the enable signal SAEN by one stage), the source thereof is connected to the source of the PMOS transistor PM5 and the drain of the PMOS transistor PM6,

the drain of the PMOS transistor PM5, the gate of the PMOS transistor PM6, the gate of the NMOS transistor NM4, and the source of the NMOS transistor NM3 are connected to the node LD. The source of the PMOS transistor PM6, the drain of the NMOS transistor NM4, the gate of the PMOS transistor PM5, and the gate of the NMOS transistor NM3 are connected to a node RD. The drain of the NMOS transistor NM3 is connected to the source of the NMOS transistor NM4 and the drain of the NMOS transistor NM5, the gate of the NMOS transistor NM5 inputs the enable signal SAEN, and the source thereof is grounded. The PMOS transistors PM5, PM6 and the NMOS transistors NM3, NM4 constitute a latch unit.

The source of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM6 and the node LG, and the drain of the PMOS transistor PM8 is connected to the source of the NMOS transistor NM6, and the bias voltage signal PBIAS of the externally supplied PMOS transistor is input. The gate of the PMOS transistor PM8 receives a ready signal PRE, and the gate of the NMOS transistor NM6 receives a precharge signal PREB (PREB is a signal obtained by inverting the ready signal PRE in one stage).

The source of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM7 and the node RG, and the drain of the PMOS transistor PM9 is connected to the source of the NMOS transistor NM7, and the bias voltage signal PBIAS of the externally supplied PMOS transistor is input. The gate of the PMOS transistor PM9 receives the ready signal PRE, and the gate of the NMOS transistor NM7 receives the precharge signal PREB.

The PMOS transistor PM8 and the NMOS transistor NM6, and the PMOS transistor PM9 and the NMOS transistor NM7 open the path from the nodes LG and RG to the bias voltage signal PBIAS, so that the voltage is charged to the bias voltage PBIAS, an initial voltage is provided, and the initial state currents of the PMOS transistor PM1 and the PMOS transistor PM2 are consistent at the moment of entering the second stage.

1. During the precharge phase, the PMOS transistors PM3, PM4 are turned on, and the nodes LD, RD are charged to the power supply voltage VDD; the node RG, LG point opens a path to the bias voltage PBIAS of the externally provided PMOS transistor, and the voltage is charged to the bias voltage PBIAS. The PMOS transistors PM3, PM4 constitute a precharge unit. Reference numeral 1 in fig. 4 and reference numeral 1 in fig. 5 denote the precharge phase.

2. In the reading stage, when the memory cell current (denoted as Icell) is smaller than the current (denoted as Iref) of the voltage-controlled current source DY3, the gates of the PMOS transistors PM1 and PM2 are disconnected and the bias voltage PBIAS terminal is connected, and due to the coupling action of the capacitors C1 and C2, the node RG is influenced by the node LD and the node LG is influenced by the node RD; the voltage drop rate of the node RD is greater than that of the node LD, and therefore, the voltage drop rate of the node LG is greater than that of the node RG. The current (Ip1) of the PMOS transistor PM1 is larger than the current (Ip2) of the PMOS transistor PM 2. The current at node LD is equal to Icell-Ip 1; the current of node RD is equal to Iref-Ip2, Icell < Iref, Ip1> Ip2, so that Icell-Ip1< < Iref-Ip2, the voltage separation speed of nodes LD and RD is increased, and the voltage drop speed of node RD is greater than that of node LD. The waveform is shown in detail in reference numeral 2 in fig. 4.

Otherwise, the same applies. In a reading stage, when the memory cell current is greater than the current of the voltage-controlled current source DY3, the gates of the PMOS transistors PM1 and PM2 are disconnected and the bias voltage PBIAS terminal is connected, and due to the coupling effect of the capacitors C1 and C2, the node RG is affected by the node LD and the node LG is affected by the node RD; the voltage drop speed of the node RD is less than that of the node LD, so that the voltage drop speed of the node LG is less than that of the node RG; the current of the PMOS transistor PM1 is smaller than the current of the PMOS transistor PM 2; the current at node LD is equal to Icell-Ip 1; the current of node RD is equal to Iref-Ip2, Icell > Iref, and Ip1< Ip2, so Icell-Ip1> > Iref-Ip2, the voltage separation speed of nodes LD and RD is increased, and the voltage drop speed of node RD is less than that of node LD. The waveform is shown in detail in reference numeral 2 in fig. 5.

3. In the latch stage, when the nodes LD and RD are separated by 0.1 × VDD (i.e., the voltage of the two nodes has a difference of 0.1 × VDD), the latch unit controlled by the enable signal SAEN is turned on to accelerate the inversion of the nodes LD and RD, so that the nodes LD and RD are rapidly changed to VDD and GND. And (6) latching and outputting. Reference numeral 3 in fig. 4 and reference numeral 3 in fig. 5 denote the latch stages. "+" indicates a multiplication number.

The invention ensures the voltage of the nodes LD and RD at VDD in the pre-charging stage, improves the pre-charging speed, realizes the dynamic change of the compensation current Ip1 and Ip2 along with the relation between the Icell current and the Iref current through the capacitors C1 and C2 in the reading stage, and greatly accelerates the comparison time. Finally, the high-speed sensitive amplifier used in NVM (non-volatile memory) is realized by combining with a latch structure.

The present invention has been described in detail with reference to the specific embodiments, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims

1. A sense amplifier circuit, comprising: nine PMOS transistors, seven NMOS transistors, two capacitors, two inverters, an operational amplifier, a voltage-controlled current source and a storage unit;

the source electrode of the second NMOS transistor is connected with a node RD, the drain electrode of the second NMOS transistor is connected with the input end of the second inverter and the positive end of the first voltage-controlled current source, and the negative end of the first voltage-controlled current source is grounded; the output end of the second inverter is connected with the grid electrode of the second NMOS transistor;

the source electrode of the ninth PMOS transistor is connected with the drain electrode of the seventh NMOS transistor and the node RG, the drain electrode of the ninth PMOS transistor is connected with the source electrode of the seventh NMOS transistor, and a bias voltage signal PBIAS of the PMOS transistor provided by the outside is input; the gate of the ninth PMOS transistor receives the ready signal PRE, and the gate of the seventh NMOS transistor receives the precharge signal PREB.

2. The circuit of claim 1, wherein: the first capacitor, the second capacitor, the first PMOS transistor and the second PMOS transistor form a compensation current unit, and the compensation current of the first PMOS transistor and the compensation current of the second PMOS transistor are controlled through the first capacitor and the second capacitor.

3. A circuit as claimed in claim 1 or 2, wherein: the current of the storage unit and the current of the first voltage-controlled current source influence the compensation current through the first capacitor and the second capacitor, and the effect of dynamically changing the compensation current is achieved.

4. The circuit of claim 1, wherein: the first inverter clamps the voltage of node a and the second inverter clamps the voltage of node B.

5. The circuit of claim 1, wherein: the eighth PMOS transistor, the sixth NMOS transistor, the ninth PMOS transistor and the seventh NMOS transistor open a path from the nodes LG and RG to the bias voltage signal PBIAS, so that the voltages of the nodes LG and RG are charged to the bias voltage PBIAS, an initial voltage is provided, and the initial state currents of the first PMOS transistor and the second PMOS transistor are ensured to be consistent when the second stage is started.

6. The circuit of claim 1, wherein: the third PMOS transistor and the fourth PMOS transistor form a pre-charging unit, in the pre-charging stage, the third PMOS transistor and the fourth PMOS transistor are turned on, and nodes LD and RD are charged to the power supply voltage VDD; the nodes RG and LG are opened to the bias voltage PBIAS of the PMOS transistor provided by the outside, and the voltages of the nodes RG and LG are charged to the bias voltage PBIAS.

7. The circuit of claim 6, wherein: and the voltage of the nodes LD and RD is ensured to be at the power supply voltage VDD in the pre-charging stage, so that the pre-charging speed is improved.

8. The circuit of claim 1, wherein: in a reading stage, when the current of the memory cell is smaller than the current of the first voltage-controlled current source, the grid of the first PMOS transistor and the grid of the second PMOS transistor are disconnected with the connection of the bias voltage PBIAS end, due to the coupling effect of the first capacitor and the second capacitor, the node RG is influenced by the node LD, and the node LG is influenced by the node RD; the voltage drop speed of the node RD is greater than that of the node LD, so that the voltage drop speed of the node LG is greater than that of the node RG; the current of the first PMOS transistor is larger than that of the second PMOS transistor; the current at node LD is equal to Icell-Ip 1; the current of the node RD is equal to Iref-Ip2, Icell < Iref, Ip1> Ip2, so that Icell-Ip1< < Iref-Ip2, the voltage separation speed of the node LD and the voltage of the node RD is accelerated, and the voltage drop speed of the node RD is greater than that of the node LD; where Icell is the memory cell current, Iref is the first voltage controlled current source current, Ip1 is the first PMOS transistor current, and Ip2 is the second PMOS transistor current.

9. The circuit of claim 1, wherein: in a reading stage, when the current of the memory cell is larger than the current of the first voltage-controlled current source, the grid electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor are disconnected with the connection of the bias voltage PBIAS end, due to the coupling effect of the first capacitor and the second capacitor, the node RG is influenced by the node LD, and the node LG is influenced by the node RD; the voltage drop speed of the node RD is less than that of the node LD, so that the voltage drop speed of the node LG is less than that of the node RG; the current of the first PMOS transistor is smaller than that of the second PMOS transistor; the current at node LD is equal to Icell-Ip 1; the current of the node RD is equal to Iref-Ip2, Icell > Iref and Ip1< Ip2, so that Icell-Ip1> > Iref-Ip2, the voltage separation speed of the nodes LD and RD is accelerated, and the voltage drop speed of the node RD is smaller than that of the node LD; where Icell is the memory cell current, Iref is the first voltage controlled current source current, Ip1 is the first PMOS transistor current, and Ip2 is the second PMOS transistor current.

10. A circuit as claimed in claim 8 or 9, wherein: in the reading stage, the compensation current Ip1 is realized through the first capacitor and the second capacitor, and Ip2 can generate dynamic change along with the relation between the current Icell and the current Iref, so that the speed of comparing the currents is improved.

11. The circuit of claim 1, wherein: the fifth PMOS transistor, the sixth PMOS transistor, the third NMOS transistor and the fourth NMOS transistor form a latch unit; in the latch stage, when the nodes LD and RD are separated by 0.1 × VDD, namely the voltage of the two nodes has the difference of 0.1 × VDD, the latch unit controlled by the enable signal SAEN is opened, the overturning of the nodes LD and RD is accelerated, so that the nodes are rapidly changed into VDD and GND, and the output is latched; where "+" denotes a multiplication number.