CN109216352B - BCD semiconductor integrated device - Google Patents

Abstract

The invention provides a BCD semiconductor integrated device, comprising 13 devices, the 13 devices share a P-type substrate and an N-type epitaxial layer, and each part is connected by a deep P-sink layer and a deep P-sink layer extending into the P-type substrate. The isolation electrode above the P-sink layer realizes electrical isolation between devices. The invention uses the oxide layer medium of the low threshold voltage MOS tube as the gate oxide layer of the low threshold high voltage power LDMOS device, and separates the surface of the low threshold voltage MOS tube with a low concentration well. The region is set as the well region of the low-threshold high-voltage power LDMOS device, and the gate electrode is set at the axis of symmetry and introduced into the JFET, so that the low-threshold voltage LDMOS current path and the main PN junction withstanding the breakdown voltage are different, avoiding the device due to low concentration. Therefore, the present invention utilizes the low-threshold MOS transistor and LDMOS in the BCD process platform to realize the low-threshold LDMOS with complete process compatibility without adding any process menu and mask.

Description

A BCD semiconductor integrated device

technical field

The invention belongs to the field of semiconductor power devices, and in particular relates to a process-compatible BCD semiconductor device. The BCD semiconductor device integrates power LDMOS, CMOS, Bipolar, low threshold NMOS, low threshold PMOS, low threshold LDMOS, power diode and the like.

Background technique

With the increasing degree of electrification of the industry, the requirements for high-voltage and high-current devices are getting higher and higher. Different application conditions have more and more requirements on the threshold voltage and breakdown voltage of the device. The threshold voltage of conventional LDMOS structures is generally above 1.5V, while the threshold voltage of low-threshold MOS transistors can be as low as 0.1V or even below 0.1V. The invention develops a BCD semiconductor device integrating the low-threshold LDMOS device based on the low-threshold voltage design of a high-voltage LDMOS device.

SUMMARY OF THE INVENTION

The invention aims to solve the problem that the conventional BCD process platform cannot achieve low threshold voltage, and develops a BCD process platform integrating low threshold LDMOS by utilizing the low threshold voltage of the low-voltage MOS structure.

The technical solution adopted by the present invention to solve the above technical problems is: using the oxide layer medium of the low threshold voltage MOS tube as the gate oxide layer of the low threshold high voltage power LDMOS device, and setting the surface low concentration well region of the low threshold voltage MOS tube to a low value The well region of the threshold high voltage power LDMOS device, and the gate electrode is set at the symmetry axis and introduced into the JFET, so that the low threshold voltage LDMOS current path is different from the main PN junction that bears the breakdown voltage, avoiding the device caused by the low concentration well region. the early punch-through problem.

In order to realize the above-mentioned purpose of the invention, the technical scheme of the present invention is as follows:

A BCD semiconductor integrated device includes 13 devices, a low-threshold nMOS transistor 101, a low-threshold pMOS transistor 102, a low-threshold nLDMOS transistor 103, a low-threshold pLDMOS transistor 104, an NMOS transistor 105, a PMOS transistor 106, an nLDMOS transistor 107, and a pLDMOS transistor 108. The first type of NPN tube 109, the first type of PNP tube 110, the second type of NPN tube 111, the second type of PNP tube 112, and the power diode 113; 13 devices share a P-type substrate 10 and an N-type epitaxial layer 9 , the electrical isolation between the devices is achieved between each part through the deep P-sink layer 12 extending into the P-type substrate 10 and the isolation electrode 30 above the deep P-sink layer 12:

The low-threshold nMOS transistor 101 includes: an N-type epitaxial layer 9 epitaxially formed on a P-type substrate 10; Two heavily doped N-type contacts 1 and one P-type contact 2, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two N-type contacts 1, and the gate electrode 31 is placed on the semiconductor surface. On the gate oxide layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two N-type contacts 1, and the body contact electrode 39 is placed on the P-type contact 2;

The low-threshold pMOS transistor 102 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10, a low-concentration N-well 3 formed on the surface of the N-type epitaxial layer 9 by ion implantation, and placed on the inner surface of the low-concentration N-well 3 Two heavily doped P-type contacts 2 and one N-type contact 1, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two P-type contacts 2, and the gate electrode 31 is placed on the semiconductor surface. On the gate oxide layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two P-type contacts 2, and the body contact electrode 39 is placed on the N-type contact 1;

The low-threshold nLDMOS transistor 103 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9 , and ion implantation in the second N-well 7 The formed two low-concentration P-wells 4 are separated by a second N-well 7, and the inner surface of the low-concentration P-well 4 includes a heavily doped N-type contact 1 and a contact with it. An adjacent P-type contact 2 is placed on the two N-type contacts 1 on the left and right sides of the second N-well 7 respectively, the STI oxide layer 23 whose surface acts as an isolation, and the gate oxide layer 21 are placed on the semiconductor surface and the two The heavily doped N-type contact 1 on the inner surface of the low-concentration P-well 4 is connected, the gate electrode 31 is placed on the gate oxide layer 21, and the source electrode 32 is located on the N-type contact 1 on the surface of the low-concentration P-well and its adjacent P It is shorted above the type contact 2, and the drain electrode 33 is located on the surface of the N type contact 1 of the second N well 7;

The low-threshold pLDMOS transistor 104 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9 , and ion implantation in the second P-well 8 The formed two low-concentration N-wells 3 are separated by a second P-well 8, and the inner surface of the low-concentration N-well 3 includes a heavily doped N-type contact 1 and a contact with it. An adjacent P-type contact 2 is placed on the two P-type contacts 2 on the left and right sides of the second P-well 8 respectively, the STI oxide layer 23 whose surface plays an isolation role, and the gate oxide layer 21 are placed on the semiconductor surface and the two The heavily doped P-type contact 2 on the inner surface of the low-concentration N-well 3 is connected, the gate electrode 31 is placed on the gate oxide layer 21, and the source electrode 32 is located on the N-type contact 1 on the surface of the low-concentration P-well and its adjacent P The top of the type contact 2 is shorted, and the drain electrode 33 is located on the surface of the P type contact 2 in the second P well 8;

The NMOS transistor 105 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a first P-well 6 formed on the surface of the N-type epitaxial layer 9 by ion implantation, and placed in the inner surface of the first P-well 6 to be heavily doped Two miscellaneous N-type contacts 1 and one P-type contact 2, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two N-type contacts 1, and the gate electrode 31 is placed on the gate oxide layer On the layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two N-type contacts 1, and the body contact electrode 39 is located on the P-type contact 2;

The PMOS transistor 106 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a first N-well 5 formed on the surface of the N-type epitaxial layer 9 by ion implantation, and placed in the inner surface of the first N-well 5 to be heavily doped Two miscellaneous P-type contacts 2 and one N-type contact 1, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two P-type contacts 2, the gate electrode 31 is placed on the gate oxide layer On the layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two P-type contacts 2, and the body contact electrode 39 is located on the N-type contact 1;

The nLDMOS transistor 107 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed on the surface of the N-type epitaxial layer 9 by diffusion, and an ion implantation formed in the middle of the second N-well 7 The first P-well 6 is placed in the two N-type contacts 1 heavily doped on the inner surface of the first P-well 6 and a P-type contact 2 between the two N-type contacts 1 is placed in the second N-well 7 The two N-type contacts 1 on the left and right sides of the surface, the STI oxide layer 23 with an isolation function on the surface, the two gate oxide layers 21 are placed on the semiconductor surface, and the gate oxide layer 21 separates the surfaces on the left and right sides of the first P well 6 respectively. Cover, and cover part of the inner surface of the first P well 6 heavily doped N-type contact 1 and the surface of the second N well 7, the gate electrode 31 is placed on the gate oxide layer 21, and the source electrode 32 is located on the surface of the first P well 6. Above two N-type contacts 1 and one P-type contact 2 between the two N-type contacts 1, and short-circuit the two N-type contacts 1 and the P-type contact 2 between them, the drain electrode 33 is located at the second N-type contact 2 the surface of the N-type contact 1 of the well 7;

The pLDMOS transistor 108 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed on the surface of the N-type epitaxial layer 9 by diffusion, and an ion implantation formed in the middle of the second P-well 8 The first N-well 5 is placed in the two P-type contacts 2 heavily doped on the inner surface of the first N-well 5 and an N-type contact 1 between the two P-type contacts 2 is placed in the second P-well 8 The two P-type contacts 2 on the left and right sides of the surface, the STI oxide layer 23 whose surface acts as an isolation, the two gate oxide layers 21 are placed on the semiconductor surface, and the gate oxide layer 21 separates the surfaces on the left and right sides of the first N well 5 respectively. Cover, and cover part of the inner surface of the first N well 5 heavily doped P-type contact 2 and the surface of the second P well 8, the gate electrode 31 is placed on the gate oxide layer 21, and the source electrode 32 is located on the surface of the first N well 5. Above two P-type contacts 2 and one N-type contact 1 between the two P-type contacts 2, and short-circuit the two P-type contacts 2 and one N-type contact 1 between them, the drain electrode is located at the second P the surface of the P-type contact 2 of the well 8;

The first type NPN tube 109 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9 , and passing through the middle of the second N-well 7 The first P-well 6 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the first P-well 6 and a P-type contact 2 isolated from the medium, and placed in the inner surface of the second N-well 7 and heavily doped A miscellaneous N-type contact 1, the STI oxide layer 23 whose surface acts as an isolation, the emitter 38 placed on the surface of the N-type contact 1 in the first P-well 6, and the emitter 38 placed on the surface of the P-type contact 2 in the first P-well 6. The base electrode 36, the collector electrode 37 placed on the surface of the N-type contact 1 in the second N well 7;

The first type of PNP tube 110 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9 , and passing through the middle of the second P-well 8 The first N-well 5 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the first N-well 5 and a P-type contact 2 isolated from the dielectric, and placed in the inner surface of the second P-well 8 and heavily doped A miscellaneous P-type contact 2, the STI oxide layer 23 whose surface acts as an isolation, the emitter 38 placed on the surface of the P-type contact 2 in the first N well 5, and the emitter 38 placed on the surface of the N-type contact 1 in the first N well 5. The base electrode 36, the collector electrode 37 placed on the surface of the P-type contact 2 in the second P well 8;

The second type of NPN tube 111 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9 , and passing through the middle of the second N-well 7 The low-concentration P-well 4 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the low-concentration P-well 4 and a P-type contact 2 isolated from the medium, and placed in the second N-well 7. The inner surface is heavily doped A miscellaneous N-type contact 1, the STI oxide layer 23 with isolation on the surface, the emitter 38 on the surface of the N-type contact 1 in the low-concentration P-well 4, and the emitter 38 on the surface of the P-type contact 2 in the low-concentration P-well 4. The base electrode 36, the collector electrode 37 placed on the surface of the N-type contact 1 in the second N well 7;

The second type of PNP tube 112 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed on the surface of the N-type epitaxial layer 9 by diffusion, and passing through the middle of the second P-well 8 The low-concentration N-well 3 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the low-concentration N-well 3 and a P-type contact 2 isolated from the dielectric, and placed in the second P-well 8. The inner surface is heavily doped A miscellaneous P-type contact 2, the STI oxide layer 23 whose surface acts as an isolation, the emitter 38 placed on the surface of the P-type contact 2 in the low-concentration N-well 3, and the emitter 38 placed on the surface of the N-type contact 1 in the low-concentration N-well 3. The base electrode 36, the collector electrode 37 placed on the surface of the P-type contact 2 in the second P well 8;

The power diode 113 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10, a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9, and placed in the inner surface of the second P-well 8 to be heavily doped An N-type contact 1 and a P-type contact 2 isolated from the dielectric, the STI oxide layer 23 with isolation on the surface, the cathode 35 placed on the surface of the N-type contact 1 and the anode 34 placed on the surface of the P-type contact 2.

As a preferred method, the isolation method between each device is replaced by using deep trenches to be etched and then filled with dielectric to achieve isolation, the deep dielectric trenches 20 are filled with oxide layers and silicon nitride dielectrics, and the bottom of the deep dielectric trenches 20 extends into the P-type substrate. 10 is inside or tangent to the upper surface of the P-type substrate 10 ; the top of the deep dielectric trench 20 is in contact with the STI oxide layer 23 .

As a preferred way, the isolation method between each device is replaced by an isolation ring, an N-type buried layer and an N-sink layer 11, each part is isolated by a reverse-biased PN junction, and the NBL layer 13 is placed on the P-type substrate 10. Between the N-type epitaxial layer 9 and the N-type epitaxial layer 9, it is realized by surface ion implantation or high-energy ion implantation before growing the N-type epitaxial layer 9. An N-sink layer 11 is provided between each device, and the N-sink layer The lower surface of 11 extends into the NBL layer 13 or is tangent to the NBL layer, and the upper surface passes through the STI oxide layer 23 and leads to the surface through the isolation electrode 30; The N-sink layer 11 , the NBL layer 13 and the N-type epitaxial layer 9 form a reverse-biased PN junction to achieve device isolation.

As a preferred way, the isolation method between each device is replaced by an isolation ring, an N-type buried layer and an N-sink layer 11, each part is isolated by a reverse-biased PN junction, and the NBL layer 13 is placed on the P-type substrate 10. Between the P-type epitaxial layer 14 and the P-type epitaxial layer 14, it is realized by surface ion implantation or high-energy ion implantation before growing the P-type epitaxial layer 14. An N-sink layer 11 and an N-sink layer are arranged between each device. The lower surface of 11 extends into the NBL layer 13 or is tangent to the NBL layer, and the upper surface passes through the STI oxide layer 23 and leads to the surface through the isolation electrode 30; The N-sink layer 11 , the NBL layer 13 and the P-type epitaxial layer 14 form a reverse-biased PN junction to achieve device isolation.

As a preferred method, an SOI substrate is used, an oxide layer 24 is arranged between the P-type substrate 10 and the N-type epitaxial layer 9, and the isolation method between the devices is replaced by using deep groove etching and then filling with a dielectric to form a deep groove. In the dielectric trench 20 , the lower end surface of the deep dielectric trench 20 is in contact with the oxide layer 24 , and the deep dielectric trench 20 and the oxide layer 24 jointly realize isolation between devices.

As a preferred method, an SOI substrate is used, and the epitaxial layer is the P-type epitaxial layer 14, an oxide layer 24 is provided between the P-type substrate 10 and the P-type epitaxial layer 14, and the isolation method between the devices is replaced by The deep dielectric trench 20 is formed by filling the medium after deep trench etching. The lower end face of the deep dielectric trench 20 is in contact with the oxide layer 24 , and the deep dielectric trench 20 and the oxide layer 24 jointly realize isolation between devices.

As a preferred way, device isolation is achieved by using a LOCOS thermally grown oxide layer.

As a preferred way, the P-sink and N-sink for isolation are formed by multiple implants.

As a preferred manner, low-threshold NMOS transistors, low-threshold PMOS transistors, low-threshold nLDMOS transistors, and low-threshold pLDMOS transistors use channel modulation injection to achieve low channel concentration.

Preferably, the semiconductor material used is silicon or silicon carbide.

The working principle of the integrated low-threshold power device in this embodiment is described below by taking a low-threshold nLDMOS as an example.

When the LDMOS is in the on state, the gate electrode 31 inverts the surface carriers of the second N-well 7 below by applying a voltage to form the source electrode 32-N-type contact 1-Low-concentration P-well 4 Surface inversion layer-JFET region -Nwell area-N-type contact 1-Drain electrode 33 electrons move directionally, due to the low concentration of low-concentration P-well 4 and the thin gate oxide layer 21, the threshold voltage of the device can be as low as 0.1V or less; when the LDMOS is in the off state When the voltage applied to the gate electrode 31 and the source electrode 32 is 0, the high voltage is applied to the drain electrode 33, and the voltage is mainly dropped at the PN junction of the second N well 7 and the low concentration P well 4. By adjusting the voltage of the low concentration P well 4 The width prevents the device from punching through, ultimately achieving high breakdown voltage and low threshold voltage LDMOS devices.

A low-threshold pLDMOS works similarly.

The beneficial effects of the present invention are: using the low-threshold MOS transistor and the conventional LDMOS in the conventional BCD process platform, a low-threshold LDMOS with complete process compatibility is realized without adding any process menu and mask.

Description of drawings

FIG. 1 shows a BCD semiconductor integrated device of Embodiment 1;

FIG. 2 shows a BCD semiconductor integrated device of Embodiment 2;

FIG. 3 shows a BCD semiconductor integrated device of Embodiment 3;

FIG. 4 shows a BCD semiconductor integrated device of Embodiment 4;

FIG. 5 shows a BCD semiconductor integrated device of Embodiment 5;

FIG. 6 shows a BCD semiconductor integrated device of Embodiment 6;

FIG. 7 shows a BCD semiconductor integrated device of the seventh embodiment.

Among them, 101 is a low-threshold nMOS transistor, 102 is a low-threshold pMOS transistor, 103 is a low-threshold nLDMOS transistor, 104 is a low-threshold pLDMOS transistor, 105 is an NMOS transistor, 106 is a PMOS transistor, 107 is an nLDMOS transistor, 108 is a pLDMOS transistor, 109 is a first type NPN tube, 110 is a first type PNP tube, 111 is a second type NPN tube, 112 is a second type PNP tube, and 113 is a power diode;

1 is an N-type contact, 2 is a P-type contact, 3 is a low-concentration N-well, 4 is a low-concentration P-well, 5 is the first N-well, 6 is the first P-well, 7 is the second N-well, and 8 is the first N-well Two P wells, 9 is an N-type epitaxial layer, 10 is a P-type substrate, 11 is an N-sink layer, 12 is a deep P-sink layer, 13 is an NBL layer, 14 is a P-type epitaxial layer, and 20 is a deep dielectric trench , 21 is gate oxide layer, 23 is STI oxide layer, 24 is oxide layer, 30 is isolation electrode: 31 is gate electrode, 32 is source electrode, 33 is drain electrode, 34 is anode, 35 is cathode, 36 is base , 37 is the collector, 38 is the emitter, 39 is the body contact electrode, 41 is the channel implanted low-concentration N-type region, and 42 is the channel implanted into the low-concentration P-type region.

Detailed ways

Below in conjunction with the accompanying drawings and embodiments, the technical solutions of the present invention are described in detail:

Example 1

As shown in FIG. 1, a BCD semiconductor integrated device is characterized by including 13 devices, namely: low threshold nMOS transistor 101, low threshold pMOS transistor 102, low threshold nLDMOS transistor 103, low threshold pLDMOS transistor 104, NMOS transistor 105, PMOS transistor 106, nLDMOS transistor 107, pLDMOS transistor 108, first type NPN transistor 109, first type PNP transistor 110, second type NPN transistor 111, second type PNP transistor 112, power diode 113; shared by 13 devices A P-type substrate 10 and an N-type epitaxial layer 9, each part is electrically connected between the devices through the deep P-sink layer 12 extending into the P-type substrate 10 and the isolation electrode 30 above the deep P-sink layer 12 isolation:

The low-threshold nMOS transistor 101 includes: an N-type epitaxial layer 9 epitaxially formed on a P-type substrate 10; Two heavily doped N-type contacts 1 and one P-type contact 2, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two N-type contacts 1, and the gate electrode 31 is placed on the semiconductor surface. On the gate oxide layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two N-type contacts 1, and the body contact electrode 39 is placed on the P-type contact 2;

The low-threshold pMOS transistor 102 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10, a low-concentration N-well 3 formed on the surface of the N-type epitaxial layer 9 by ion implantation, and placed on the inner surface of the low-concentration N-well 3 Two heavily doped P-type contacts 2 and one N-type contact 1, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two P-type contacts 2, and the gate electrode 31 is placed on the semiconductor surface. On the gate oxide layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two P-type contacts 2, and the body contact electrode 39 is placed on the N-type contact 1;

The low-threshold nLDMOS transistor 103 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9 , and ion implantation in the second N-well 7 The formed two low-concentration P-wells 4 are separated by a second N-well 7, and the inner surface of the low-concentration P-well 4 includes a heavily doped N-type contact 1 and a contact with it. An adjacent P-type contact 2 is placed on the two N-type contacts 1 on the left and right sides of the second N-well 7 respectively, the STI oxide layer 23 whose surface acts as an isolation, and the gate oxide layer 21 are placed on the semiconductor surface and the two The N-type contact 1 is connected, the gate electrode 31 is placed on the gate oxide layer 21, the source electrode 32 is located above the N-type contact 1 on the surface of the low-concentration P-well and the adjacent P-type contact 2, and the drain electrode is shorted. 33 is located on the surface of the N-type contact 1 of the second N-well 7;

The low-threshold pLDMOS transistor 104 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9 , and ion implantation in the second P-well 8 The formed two low-concentration N-wells 3 are separated by a second P-well 8, and the inner surface of the low-concentration N-well 3 includes a heavily doped N-type contact 1 and a contact with it. An adjacent P-type contact 2 is placed on the two P-type contacts 2 on the left and right sides of the second P-well 8 respectively, the STI oxide layer 23 whose surface plays an isolation role, and the gate oxide layer 21 are placed on the semiconductor surface and the two The P-type contact 2 is connected, the gate electrode 31 is placed on the gate oxide layer 21, the source electrode 32 is located above the N-type contact 1 on the surface of the low-concentration P-well and the adjacent P-type contact 2, and the drain electrode is shorted. 33 is located on the surface of the P-type contact 2 in the second P-well 8;

The NMOS transistor 105 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a first P-well 6 formed on the surface of the N-type epitaxial layer 9 by ion implantation, and placed in the inner surface of the first P-well 6 to be heavily doped Two miscellaneous N-type contacts 1 and one P-type contact 2, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two N-type contacts 1, and the gate electrode 31 is placed on the gate oxide layer On the layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two N-type contacts 1, and the body contact electrode 39 is located on the P-type contact 2;

The PMOS transistor 106 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a first N-well 5 formed on the surface of the N-type epitaxial layer 9 by ion implantation, and placed in the inner surface of the first N-well 5 to be heavily doped Two miscellaneous P-type contacts 2 and one N-type contact 1, the surface of the STI oxide layer 23 for isolation, the gate oxide layer 21 is placed on the semiconductor surface and connects the two P-type contacts 2, the gate electrode 31 is placed on the gate oxide layer On the layer 21, the source electrode 32 and the drain electrode 33 are respectively located above the two P-type contacts 2, and the body contact electrode 39 is located on the N-type contact 1;

The nLDMOS transistor 107 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed on the surface of the N-type epitaxial layer 9 by diffusion, and an ion implantation formed in the middle of the second N-well 7 The first P-well 6 is placed in the two N-type contacts 1 heavily doped on the inner surface of the first P-well 6 and a P-type contact 2 between the two N-type contacts 1 is placed in the second N-well 7 The two N-type contacts 1 on the left and right sides of the surface, the STI oxide layer 23 with an isolation function on the surface, the two gate oxide layers 21 are placed on the semiconductor surface, and the gate oxide layer 21 separates the surfaces on the left and right sides of the first P well 6 respectively. Cover, and cover part of the inner surface of the first P well 6 heavily doped N-type contact 1 and the surface of the second N well 7, the gate electrode 31 is placed on the gate oxide layer 21, and the source electrode 32 is located on the surface of the first P well 6. Above two N-type contacts 1 and one P-type contact 2 between the two N-type contacts 1, and short-circuit the two N-type contacts 1 and the P-type contact 2 between them, the drain electrode 33 is located at the second N-type contact 2 the surface of the N-type contact 1 of the well 7;

The pLDMOS transistor 108 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed on the surface of the N-type epitaxial layer 9 by diffusion, and an ion implantation formed in the middle of the second P-well 8 The first N-well 5 is placed in the two P-type contacts 2 heavily doped on the inner surface of the first N-well 5 and an N-type contact 1 between the two P-type contacts 2 is placed in the second P-well 8 The two P-type contacts 2 on the left and right sides of the surface, the STI oxide layer 23 whose surface acts as an isolation, the two gate oxide layers 21 are placed on the semiconductor surface, and the gate oxide layer 21 separates the surfaces on the left and right sides of the first N well 5 respectively. Covers and covers part of the inner surface of the first N well 5 heavily doped P-type contact 2 and the surface of the second P well 8 , the gate electrode 31 is placed on the gate oxide layer 21 , and the source electrode 32 is located on two sides of the surface of the first N well 5 . Above the two P-type contacts 2 and one N-type contact 1 between the two P-type contacts 2, and short-circuit the two P-type contacts 2 and one N-type contact 1 between them, the drain electrode is located in the second P-well The P-type of 8 contacts the surface of 2;

The first type NPN tube 109 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9 , and passing through the middle of the second N-well 7 The first P-well 6 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the first P-well 6 and a P-type contact 2 isolated from the medium, and placed in the inner surface of the second N-well 7 and heavily doped A miscellaneous N-type contact 1, the STI oxide layer 23 whose surface acts as an isolation, the emitter 38 placed on the surface of the N-type contact 1 in the first P-well 6, and the emitter 38 placed on the surface of the P-type contact 2 in the first P-well 6. The base electrode 36, the collector electrode 37 placed on the surface of the N-type contact 1 in the second N well 7;

The first type of PNP tube 110 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9 , and passing through the middle of the second P-well 8 The first N-well 5 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the first N-well 5 and a P-type contact 2 isolated from the dielectric, and placed in the inner surface of the second P-well 8 and heavily doped A miscellaneous P-type contact 2, the STI oxide layer 23 whose surface acts as an isolation, the emitter 38 placed on the surface of the P-type contact 2 in the first N well 5, and the emitter 38 placed on the surface of the N-type contact 1 in the first N well 5. The base electrode 36, the collector electrode 37 placed on the surface of the P-type contact 2 in the second P well 8;

The second type of NPN tube 111 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second N-well 7 formed by diffusion on the surface of the N-type epitaxial layer 9 , and passing through the middle of the second N-well 7 The low-concentration P-well 4 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the low-concentration P-well 4 and a P-type contact 2 isolated from the medium, and placed in the second N-well 7. The inner surface is heavily doped A miscellaneous N-type contact 1, the STI oxide layer 23 with isolation on the surface, the emitter 38 on the surface of the N-type contact 1 in the low-concentration P-well 4, and the emitter 38 on the surface of the P-type contact 2 in the low-concentration P-well 4. The base electrode 36, the collector electrode 37 placed on the surface of the N-type contact 1 in the second N well 7;

The second type of PNP tube 112 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10 , a second P-well 8 formed on the surface of the N-type epitaxial layer 9 by diffusion, and passing through the middle of the second P-well 8 The low-concentration N-well 3 formed by ion implantation is placed in an N-type contact 1 heavily doped on the inner surface of the low-concentration N-well 3 and a P-type contact 2 isolated from the dielectric, and placed in the second P-well 8. The inner surface is heavily doped A miscellaneous P-type contact 2, the STI oxide layer 23 whose surface acts as an isolation, the emitter 38 placed on the surface of the P-type contact 2 in the low-concentration N-well 3, and the emitter 38 placed on the surface of the N-type contact 1 in the low-concentration N-well 3. The base electrode 36, the collector electrode 37 placed on the surface of the P-type contact 2 in the second P well 8;

The power diode 113 includes: an N-type epitaxial layer 9 epitaxially formed on the P-type substrate 10, a second P-well 8 formed by diffusion on the surface of the N-type epitaxial layer 9, and placed in the inner surface of the second P-well 8 to be heavily doped An N-type contact 1 and a P-type contact 2 isolated from the dielectric, the STI oxide layer 23 with isolation on the surface, the cathode 35 placed on the surface of the N-type contact 1 and the anode 34 placed on the surface of the P-type contact 2.

In this embodiment, the low-threshold LDMOS and the low-threshold MOS transistor share the same gate oxide layer process and the same well region, and the low-threshold voltage is achieved by enhancing the gate electrode's control of channel carriers through the low-concentration well region. The channel in low-threshold LDMOS devices is generally short. By placing the gate electrode at the center of the device and forming a JFET region under the gate electrode, the short-channel effect can be effectively reduced, and the device withstand voltage and conduction direction current are different. , to avoid device punch-through breakdown. In this embodiment, only the doping types of the low-concentration N-well 3 and the low-concentration P-well 4 are limited. Conventional LDMOS and low-threshold LDMOS drift regions are formed by ion implantation. N-type impurities are implanted to form a second N-well 7 and P-type impurities are formed to form a second P-well 8. Generally, the depth of the second N-well 7 exceeds the low-concentration P-well. 4 and the first P-well 6, the second P-well 8 is deeper than the low-concentration N-well 3 and the first N-well 5. In this embodiment, the depth comparison between the low-concentration N-well 3 and the low-concentration P-well 4 , the depth comparison between the first N-well 5 and the first P-well 6 , and the depth between the second N-well 7 and the second P-well 8 The comparison, the depth comparison between the N-type contact 1 and the P-type contact 2 are not limited, and can be designed through specific processes.

Example 2

As shown in FIG. 2 , a BCD semiconductor device of this embodiment, compared with Embodiment 1, is different in that: the isolation method between each device adopts deep trench etching and then fills the medium to achieve isolation, and the deep dielectric trench 20 The oxide layer and silicon nitride dielectric are filled, the bottom of the deep dielectric trench 20 extends into the interior of the P-type substrate 10 or is tangent to the upper surface of the P-type substrate 10 ; the top of the deep dielectric trench 20 is in contact with the STI oxide layer 23 .

Example 3

As shown in FIG. 3 , a BCD semiconductor device of this embodiment, compared with Embodiment 1, is different in that an isolation ring, an N-type buried layer and an N-sink layer 11 are used for the isolation between each device. Each part is separated by a reverse biased PN junction, and the NBL layer 13 is placed between the P-type substrate 10 and the N-type epitaxial layer 9, which is realized by surface ion implantation before growing the N-type epitaxial layer 9, or by high-energy Ion implantation is formed, an N-sink layer 11 is arranged between each device, the lower surface of the N-sink layer 11 extends into the NBL layer 13 or is tangent to the NBL layer, and the upper surface passes through the STI oxide layer 23 and passes through the isolation electrode 30 Lead-out surface; isolation electrode 30 plus positive high voltage is transmitted to NBL layer 13 through N-sink layer 11, N-sink layer 11, NBL layer 13 and N-type epitaxial layer 9 form a reverse-biased PN junction to achieve device isolation.

Example 4

As shown in FIG. 4 , a BCD semiconductor device of this embodiment, compared with Embodiment 1, is different in that the N-type epitaxial layer 9 is replaced by a P-type epitaxial layer 14 , and the isolation method between each device adopts isolation. Ring and N-type buried layer and N-sink layer 11, each part is separated by reverse biased PN junction, NBL layer 13 is placed between P-type substrate 10 and P-type epitaxial layer 14, which is realized by growing P-type Before the epitaxial layer 14 is formed by surface ion implantation, or formed by high-energy ion implantation, an N-sink layer 11 is provided between each device, and the lower surface of the N-sink layer 11 extends into the NBL layer 13 or is tangent to the NBL layer, The upper surface passes through the STI oxide layer 23 and leads to the surface through the isolation electrode 30; the isolation electrode 30 applies a positive high voltage and is transmitted to the NBL layer 13 through the N-sink layer 11, and the N-sink layer 11, the NBL layer 13 and the P-type epitaxial layer 14 are formed. The reverse biased PN junction achieves device isolation.

Example 5

As shown in FIG. 5 , a BCD semiconductor device of this embodiment, compared with Embodiment 1, is different in that this embodiment uses an SOI (Silicon-On-Insulator, silicon-on-insulator) substrate, and the P-type substrate is A layer of oxide layer 24 is arranged between the bottom 10 and the N-type epitaxial layer 9, and a deep dielectric groove 20 is formed by filling a medium between the devices after deep groove etching, and the lower end face of the deep dielectric groove 20 is connected to the oxide layer 24, The deep dielectric trench 20 and the oxide layer 24 together achieve isolation between devices.

Example 6

As shown in FIG. 6 , a BCD semiconductor device of this embodiment, compared with Embodiment 1, is different in that a SOI substrate is used, and the epitaxial layer is a P-type epitaxial layer 14 . A layer of oxide layer 24 is arranged between the epitaxial layers 14, and deep dielectric grooves 20 are formed by filling the dielectric between the devices after deep groove etching. The lower end face of the deep dielectric groove 20 is connected to the oxide layer 24. Together with oxide layer 24, isolation between devices is achieved.

Example 7

As shown in FIG. 7 , a BCD semiconductor device of this embodiment, compared with Embodiment 1, is different in that the upper surface and gate of the low-concentration P-well 4 in the low-threshold nMOS transistor 101 and the low-threshold nLDMOS transistor 103 A channel is implanted between the lower surface of the oxide layer 21 and the low-concentration P-type region 42 is set, and a trench is set between the upper surface of the low-concentration N well 3 in the low-threshold pMOS transistor 102 and the low-threshold pLDMOS transistor 104 and the lower surface of the gate oxide layer 21 The channel is implanted into the low-concentration N-type region 41 . The advantage of this embodiment is that the low concentration of the channel surface can be formed by the channel adjustment process, and the concentration of the low-concentration N-well 3 and the low-concentration P-well 4 can be effectively increased.

It is worth noting that:

The core claimed in the present invention is a low-threshold-voltage lateral high-voltage power device compatible with BCD process, and the gate oxide layer formation process and well region implantation process related to the low-threshold-voltage NMOS transistor compatible with BCD process and the device threshold voltage are applied to In the conventional LDMOS device manufacturing process, the existing punch-through breakdown problem is eliminated, and a high-voltage LDMOS device with a low threshold voltage that can meet the withstand voltage requirements is realized. The realization process is completely compatible with the conventional BCD process, and no mask is added.

The N-sink and P-sink layers used for isolation can be combined with multiple injections and other injection processes used in this platform to improve the carrier concentration of the sink layer;

When the epitaxial layer is N-type, the N-type epitaxial layer 9 can be used as the drift region of nLDMOS; similarly, when the epitaxial layer is P-type, the P-type epitaxial layer 14 can be used as the drift region of pLDMOS;

In addition to using the STI in the embodiment, the isolation of each part of the device surface included in the present invention can also be achieved by growing a field oxide layer through the LOCOS process.

The semiconductor material used in the present invention is Si, which is also applicable to other semiconductor materials.

Claims (10)

1. A BCD semiconductor integrated device is characterized by comprising 13 devices which are respectively as follows: the transistor comprises a low-threshold nMOS (101), a low-threshold pMOS (102), a low-threshold nLDMOS (103), a low-threshold pLDMOS (104), an NMOS (105), a PMOS (106), an nLDMOS (107), a pLDMOS (108), a first NPN (109), a first PNP (110), a second NPN (111), a second PNP (112) and a power diode (113); the 13 devices share a P-type substrate (10) and an N-type epitaxial layer (9), and each part is electrically isolated from the other parts through an isolation electrode (30) extending into a deep P-sink layer (12) of the P-type substrate (10) and above the deep P-sink layer (12):

the low-threshold nMOS transistor (101) includes: the transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a low-concentration P well (4) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped N-type contacts (1) and a P-type contact (2) arranged on the inner surface of the low-concentration P well (4), and an STI (shallow trench isolation) oxide layer (23) with the surface having an isolation effect, wherein a gate oxide layer (21) is arranged on the surface of a semiconductor and connects the two N-type contacts (1), a gate electrode (31) is arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) are respectively arranged above the two N-type contacts (1), and a body contact electrode (39) is arranged on the P-type;

the low-threshold pMOS tube (102) includes: the field-effect transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a low-concentration N well (3) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped P-type contacts (2) and an N-type contact (1) which are arranged on the inner surface of the low-concentration N well (3), an STI (shallow trench isolation) oxide layer (23) with the surface playing a role in isolation, a gate oxide layer (21) arranged on the surface of a semiconductor and connecting the two P-type contacts (2), a gate electrode (31) arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) respectively arranged above the two P-type contacts (2), and a body contact electrode (39) arranged on the N-type;

the low-threshold nLDMOS transistor (103) comprises: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second N well (7) formed on the surface of the N-type epitaxial layer (9) through diffusion, two low-concentration P wells (4) formed in the second N well (7) through ion implantation, the two low-concentration P wells (4) are separated by the second N well (7), the inner surfaces of the low-concentration P wells (4) respectively comprise a heavily doped N-type contact (1) and a P-type contact (2) adjacent to the heavily doped N-type contact (1), the two N-type contacts (1) arranged on the left side surface and the right side surface of the second N well (7) respectively, STI (shallow trench isolation) oxide layers (23) with surfaces playing an isolating role, a gate oxide layer (21) is arranged on the surface of a semiconductor and is connected with the heavily doped N-type contacts (1) on the inner surfaces of the two low-concentration P wells (4), a gate electrode (31) is arranged on the gate oxide layer (21), and a source electrode (32) is arranged above the N-type contact Short-circuiting the N-type contact, wherein the drain electrode (33) is positioned on the surface of the N-type contact (1) of the second N-well (7);

the low-threshold pLDMOS transistor (104) comprises: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, two low-concentration N wells (3) formed in the second P well (8) through ion implantation, the two low-concentration N wells (3) are separated by the second P well (8), the inner surfaces of the low-concentration N wells (3) respectively comprise a heavily doped N-type contact (1) and a P-type contact (2) adjacent to the heavily doped N-type contact (1), the two P-type contacts (2) respectively arranged on the left side surface and the right side surface of the second P well (8), STI (shallow trench isolation) oxide layers (23) with surfaces playing an isolating role, a gate oxide layer (21) is arranged on the surface of a semiconductor and is connected with the heavily doped P-type contacts (2) on the inner surfaces of the two low-concentration N wells (3), a gate electrode (31) is arranged on the gate oxide layer (21), and a source electrode (32) is arranged above the N-type contact ( Short-circuiting the drain electrode (33), and locating the drain electrode on the surface of the P-type contact (2) in the second P well (8);

the NMOS transistor (105) includes: the transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a first P well (6) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped N-type contacts (1) and a P-type contact (2) arranged on the inner surface of the first P well (6), and an STI (shallow trench isolation) oxide layer (23) with the surface having an isolation effect, wherein a gate oxide layer (21) is arranged on the surface of a semiconductor and connects the two N-type contacts (1), a gate electrode (31) is arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) are respectively arranged above the two N-type contacts (1), and a body contact electrode (39) is arranged on the P-type contact (2);

the PMOS tube (106) comprises: the field-effect transistor comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a first N well (5) formed on the surface of the N-type epitaxial layer (9) through ion implantation, two heavily doped P-type contacts (2) and an N-type contact (1) which are arranged on the inner surface of the first N well (5), an STI (shallow trench isolation) oxide layer (23) with the surface playing a role in isolation, a gate oxide layer (21) arranged on the surface of a semiconductor and used for connecting the two P-type contacts (2), a gate electrode (31) arranged on the gate oxide layer (21), a source electrode (32) and a drain electrode (33) respectively arranged above the two P-type contacts (2), and a body contact electrode (39) arranged on the N-type contact (;

the nLDMOS tube (107) comprises: an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second N-well (7) formed on the surface of the N-type epitaxial layer (9) through diffusion, a first P-well (6) formed in the middle of the second N-well (7) through ion implantation, two heavily doped N-type contacts (1) arranged on the inner surface of the first P-well (6) and one P-type contact (2) between the two N-type contacts (1), two N-type contacts (1) respectively arranged on the left side surface and the right side surface of the second N-well (7), STI oxide layers (23) with isolation functions on the surfaces, two gate oxide layers (21) are arranged on the surface of a semiconductor, the gate oxide layers (21) respectively cover the surfaces on the left side and the right side of the first P-well (6) and cover the surfaces of the heavily doped part N-type contacts (1) and the surface of the second N-well (7) in the inner surface of the first P-well (6), a gate electrode (, the source electrode (32) is positioned above the two N-type contacts (1) on the surface of the first P well (6) and one P-type contact (2) between the two N-type contacts (1), the two N-type contacts (1) and the P-type contact (2) between the two N-type contacts are in short circuit, and the drain electrode (33) is positioned on the surface of the N-type contact (1) of the second N well (7);

the pLDMOS tube (108) includes: an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P-well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, a first N-well (5) formed in the middle of the second P-well (8) through ion implantation, two heavily doped P-type contacts (2) arranged on the inner surface of the first N-well (5) and one N-type contact (1) between the two P-type contacts (2), two P-type contacts (2) respectively arranged on the left side surface and the right side surface of the second P-well (8), STI oxide layers (23) with isolation functions on the surfaces, two gate oxide layers (21) are arranged on the surface of a semiconductor, the gate oxide layers (21) respectively cover the surfaces on the left side and the right side of the first N-well (5) and cover the surfaces of the heavily doped part P-type contacts (2) and the surface of the second P-well (8) on the inner surface of the first N-well (5), a gate electrode (, the source electrode (32) is positioned above the two P-type contacts (2) on the surface of the first N well (5) and one N-type contact (1) between the two P-type contacts (2), the two P-type contacts (2) and the N-type contact (1) between the two P-type contacts are in short circuit, and the drain electrode is positioned on the surface of the P-type contact (2) of the second P well (8);

the first type of NPN tube (109) includes: the manufacturing method comprises the steps of forming an N-type epitaxial layer (9) on a P-type substrate (10) in an epitaxial mode, forming a second N well (7) on the surface of the N-type epitaxial layer (9) through diffusion, forming a first P well (6) in the middle of the second N well (7) through ion implantation, placing an N-type contact (1) heavily doped on the inner surface of the first P well (6) and a P-type contact (2) isolated from the first P well in a medium mode, placing an N-type contact (1) heavily doped on the inner surface of the second N well (7), forming an STI (shallow trench isolation) oxide layer (23) with the surface playing an isolating role, placing an emitter (38) on the surface of the N-type contact (1) in the first P well (6), placing a base (36) on the surface of the P-type contact (2) in the first P well (6), and placing a collector (37) on the surface of the N-type contact;

the first type of PNP tube (110) includes: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, a first N well (5) formed in the middle of the second P well (8) through ion implantation, an N-type contact (1) heavily doped on the inner surface of the first N well (5) and a P-type contact (2) isolated from the N-type contact with a medium, a P-type contact (2) heavily doped on the inner surface of the second P well (8), an STI oxide layer (23) with the surface playing an isolating role, an emitter (38) arranged on the surface of the P-type contact (2) in the first N well (5), a base (36) arranged on the surface of the N-type contact (1) in the first N well (5), and a collector (37) arranged on the surface of the P-type contact (2) in the second P well (8);

the second NPN tube (111) comprises: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second N-well (7) formed on the surface of the N-type epitaxial layer (9) through diffusion, a low-concentration P-well (4) formed in the middle of the second N-well (7) through ion implantation, an N-type contact (1) arranged on the inner surface of the low-concentration P-well (4) in a heavily doped mode and a P-type contact (2) isolated from the N-type contact with a medium, an N-type contact (1) arranged on the inner surface of the second N-well (7) in a heavily doped mode, an STI oxide layer (23) with the surface playing an isolating role, an emitter (38) arranged on the surface of the N-type contact (1) in the low-concentration P-well (4), a base (36) arranged on the surface of the P-type contact (2) in the low-concentration P-well (4), and a collector;

a second type of PNP tube (112) includes: the semiconductor device comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, a low-concentration N well (3) formed in the middle of the second P well (8) through ion implantation, an N-type contact (1) arranged on the inner surface of the low-concentration N well (3) in a heavily doped mode and a P-type contact (2) isolated from the N-type contact in a medium mode, a P-type contact (2) arranged on the inner surface of the second P well (8) in a heavily doped mode, an STI oxide layer (23) with the surface playing an isolating role, an emitter (38) arranged on the surface of the P-type contact (2) in the low-concentration N well (3), a base (36) arranged on the surface of the N-type contact (1) in the low-concentration N well (3), and a collector (37) arranged on the;

the power diode (113) comprises: the structure comprises an N-type epitaxial layer (9) formed on a P-type substrate (10) in an epitaxial mode, a second P well (8) formed on the surface of the N-type epitaxial layer (9) through diffusion, an N-type contact (1) arranged on the inner surface of the second P well (8) in heavy doping and a P-type contact (2) isolated from the N-type contact, an STI (shallow trench isolation) oxide layer (23) with the surface playing an isolation role, a cathode (35) arranged on the surface of the N-type contact (1) and an anode (34) arranged on the surface of the P-type contact (2).

2. The BCD semiconductor integrated device according to claim 1, wherein: the isolation mode among all devices is replaced by the mode of filling a medium after deep groove etching to realize isolation, the deep medium groove (20) is filled with an oxide layer and a silicon nitride medium, and the bottom of the deep medium groove (20) extends into the P-type substrate (10) or is tangent to the upper surface of the P-type substrate (10); the top of the deep dielectric groove (20) is connected with the STI oxide layer (23).

3. A BCD semiconductor integrated device according to claim 1, characterized in that: the isolation mode among each device is replaced by an isolation ring, an N-type buried layer and an N-sink layer (11), each part is isolated by utilizing a reverse bias PN junction, an NBL layer (13) is arranged between a P-type substrate (10) and an N-type epitaxial layer (9), the isolation mode is realized by surface ion implantation before the growth of the N-type epitaxial layer (9) or high-energy ion implantation, the N-sink layer (11) is arranged between each device, the lower surface of the N-sink layer (11) extends into the NBL layer (13) or is tangent to the NBL layer, and the upper surface penetrates through an STI oxide layer (23) and is led out of the surface through an isolation electrode (30); the isolation electrode (30) is applied with positive high voltage and is transmitted to the NBL layer (13) through the N-sink layer (11), and the N-sink layer (11), the NBL layer (13) and the N-type epitaxial layer (9) form reverse bias PN solid existing device isolation.

4. The BCD semiconductor integrated device according to claim 1, wherein: the isolation mode among each device is replaced by adopting an isolation ring, an N-type buried layer and an N-sink layer (11), each part is isolated by utilizing a reverse bias PN junction, an NBL layer (13) is arranged between a P-type substrate (10) and a P-type epitaxial layer (14), the isolation mode is realized by surface ion implantation before the growth of the P-type epitaxial layer (14) or high-energy ion implantation, the N-sink layer (11) is arranged between each device, the lower surface of the N-sink layer (11) extends into the NBL layer (13) or is tangent to the NBL layer, and the upper surface of the N-sink layer (11) penetrates through an STI oxide layer (23) and is led out of the surface through an isolation electrode (30); the isolation electrode (30) is applied with positive high voltage and is transmitted to the NBL layer (13) through the N-sink layer (11), and the N-sink layer (11), the NBL layer (13) and the P-type epitaxial layer (14) form reverse bias PN solid existing device isolation.

5. The BCD semiconductor integrated device according to claim 1, wherein: an SOI substrate is adopted, an oxide layer (24) is arranged between a P-type substrate (10) and an N-type epitaxial layer (9), the isolation mode between devices is replaced by a deep groove etching mode, a medium is filled into the deep groove etching mode to form a deep medium groove (20), the lower end face of the deep medium groove (20) is connected with the oxide layer (24), and the deep medium groove (20) and the oxide layer (24) jointly realize isolation between the devices.

6. The BCD semiconductor integrated device according to claim 1, wherein: an SOI substrate is adopted, the epitaxial layer is a P-type epitaxial layer (14), an oxide layer (24) is arranged between the P-type substrate (10) and the P-type epitaxial layer (14), the isolation mode between devices is replaced by adopting a deep groove to etch and then fill a medium to form a deep medium groove (20), the lower end face of the deep medium groove (20) is connected with the oxide layer (24), and the deep medium groove (20) and the oxide layer (24) realize isolation between the devices together.

7. A BCD semiconductor integrated device according to any of claims 1-6, characterized in that: and the STI oxide layer (23) with the surface playing the role of isolation is replaced by a LOCOS thermal growth oxide layer to realize the device isolation.

8. The BCD semiconductor integrated device according to claim 1, wherein: the P-sink for isolation is formed by multiple implants.

9. A BCD semiconductor integrated device according to any of claims 1-6, characterized in that: the low-threshold NMOS tube, the low-threshold PMOS tube, the low-threshold nLDMOS tube and the low-threshold pLDMOS tube use channel adjusting injection to realize low concentration of a channel.

10. A BCD semiconductor integrated device according to any of claims 1-6, characterized in that: the semiconductor material used is silicon or silicon carbide.

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