CN109188812A - Array substrate, testing method thereof, display panel and display device - Google Patents
Array substrate, testing method thereof, display panel and display device Download PDFInfo
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- CN109188812A CN109188812A CN201811172986.5A CN201811172986A CN109188812A CN 109188812 A CN109188812 A CN 109188812A CN 201811172986 A CN201811172986 A CN 201811172986A CN 109188812 A CN109188812 A CN 109188812A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- H10P74/277—
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
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Abstract
本发明公开了一种阵列基板、其测试方法、显示面板及显示装置，包括N条数据输入线，N个分别与各数据输入线相连的数据信号输入端子，测试控制端子，N个与各数据输入线一一对应的测试模块，以及第一测试信号输出端子；第M个测试模块，用于在加载于测试控制端子的信号以及加载于第M+1条数据输入线上的信号的控制下，将加载于第M条数据输入线上的信号提供给第一测试信号输出端子。上述结构可以对每条数据输入线单独测试，在第一测试信号输出端子处连接测试设备，即可对每条数据输入线的信号进行测试。对数据输入线的电学测试不再受测试位置的局限，测试方法简单快速，不需要破坏阵列基板上的绝缘层。
The invention discloses an array substrate, a testing method thereof, a display panel and a display device, comprising N data input lines, N data signal input terminals respectively connected with the data input lines, test control terminals, and N data input terminals connected with each data input line. The test modules corresponding to the input lines one-to-one, and the first test signal output terminal; the Mth test module is used under the control of the signal loaded on the test control terminal and the signal loaded on the M+1th data input line , the signal loaded on the Mth data input line is provided to the first test signal output terminal. With the above structure, each data input line can be tested individually, and the signal of each data input line can be tested by connecting the test equipment at the first test signal output terminal. The electrical test on the data input line is no longer limited by the test position, the test method is simple and fast, and the insulating layer on the array substrate does not need to be damaged.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate, its test method, display panel and displays
Device.
Background technique
As display technology is constantly reformed, display panel manufacturing process is increasingly refined, the line of signal wire in display panel
Width requirement is more and more finer, since the complexity of manufacture craft increases, so that there may be all for the display panel to complete
Mostly bad, the reason for causing these bad may be display chip output abnormality, and fanout area route is impaired, data selector
(Multiplexer) it is damaged, display area route is impaired or electrostatic discharge protective circuit is abnormal etc..And above-mentioned reason is required to test
The signal of data line is as analysis foundation.
Currently, the first is production emulation data-signal to there are two types of the test modes of the data signal line of display panel
Line (Dummy Source), and connecting test terminal test the signal of emulation data signal line, but this design can only
The signal for testing perimeter data signal wire cannot test whole routes in display panel.Second is incited somebody to action using laser microprobe platform
Insulating layer on data signal line is removed with laser bombardment, is reused probe connection oscillograph and is gone to test, but this test method
For destructive testing, and success rate is less than 70%.Therefore it provides a kind of strong operability and display panel whole line can be tested
The testing scheme on road is urgent problem to be solved.
Summary of the invention
The present invention provides a kind of array substrate, its test method, display panel and display devices, to array substrate
In total data signal wire carry out signal testing.
In a first aspect, the present invention provides a kind of array substrate, comprising: display area and adjacent with the display area non-
Display area；The non-display area includes: circuit region and the test section adjacent with the circuit region；
The circuit region includes: N data input line, N number of data-signal being connected respectively with each Data In-Line
Input terminal, testing and control terminal and N number of and each one-to-one test module of Data In-Line；The test section
It include: the first test signal output terminal；
Test module described in m-th, for loading on the signal of the testing and control terminal and loading on the M+1 articles
Under the control of signal on the Data In-Line, the M articles will be loaded on described in signal on Data In-Line be supplied to it is described
First test signal output terminal；
Wherein, 1≤M≤N, and M and N are positive integer.
In one possible implementation, in above-mentioned array substrate provided by the invention, mould is tested described in m-th
Block, comprising: first switch transistor and second switch transistor；
The control electrode of the first switch transistor connects the testing and control terminal, and the of the first switch transistor
Second pole of Data In-Line described in the M articles of one pole connection, the first switch transistor connects the second switch transistor
The first pole；Data In-Line described in the M+1 articles of the control electrode connection of the second switch transistor, the second switch crystal
The second pole connection of pipe the first test signal output terminal.
In one possible implementation, in above-mentioned array substrate provided by the invention, the circuit region further include:
First output signal line；The test section further include: the second test signal output terminal；
The testing and control terminal is connected by first output signal line with the second test signal output terminal.
In one possible implementation, in above-mentioned array substrate provided by the invention, the circuit region further include:
With each one-to-one third switching transistor of test module, first switch control signal end；Second output signal line；
The test section further include: third tests signal output terminal；
First switch control signal end tests signal output by second output signal line and the third
Terminal is connected；
The control electrode of third switching transistor described in m-th connects first switch control signal end, the third
First pole of switching transistor connects the M data input line, described in the second pole connection of the third switching transistor
First test signal output terminal.
In one possible implementation, in above-mentioned array substrate provided by the invention, the circuit region further include:
4th switching transistor, second switch control signal end, tests signal input terminal, third output signal line and the 4th
Output signal line；The test section further include: the 4th test signal output terminal；
Second switch control signal end tests signal wire and the 4th test signal output by the third
Terminal is connected；
The control electrode of 4th switching transistor connects second switch control signal end, and the 4th switch is brilliant
First pole of body pipe connects the test signal input terminal, and the second pole of the 4th switching transistor is defeated by the described 4th
Signal wire connection the first test signal output terminal out.
Second aspect, the present invention provide a kind of test method based on any of the above-described array substrate, comprising:
First control signal is loaded to testing and control terminal, data-signal is loaded to m-th data signal input terminal, it is right
The M+1 data signal input terminal loads second control signal, believes the remainder data in addition to m-th and M+1
Number input terminal load third controls signal, and the signal of control M data input line is supplied to the first test signal output end
Son；
Detect the signal of the first test signal output terminal；
Wherein, 1≤M≤N, and M and N are positive integer.
In one possible implementation, in above-mentioned test method provided by the invention, the array substrate is also wrapped
It includes: third switching transistor, the test method further include:
First control signal is being loaded to testing and control terminal, data-signal is loaded to m-th data signal input terminal,
Second control signal is loaded to the M+1 data signal input terminal, to the remainder data in addition to m-th and M+1
While signal input terminal loads third control signal, to the 4th control signal of first control signal terminal load, institute is controlled
State the closing of third switching transistor.
In one possible implementation, in above-mentioned test method provided by the invention, the array substrate is also wrapped
It includes: the 4th switching transistor, the test method further include:
First control signal is being loaded to testing and control terminal, data-signal is loaded to m-th data signal input terminal,
Second control signal is loaded to the M+1 data signal input terminal, to the remainder data in addition to m-th and M+1
While signal input terminal loads third control signal, to the 5th control signal of second control signal terminal load, institute is controlled
State the closing of the 4th switching transistor.
The third aspect, the present invention provide a kind of display panel, including any of the above-described array substrate.
Fourth aspect, the present invention provide a kind of display device, including above-mentioned display panel.
The present invention has the beneficial effect that:
Array substrate, its test method, display panel and display device provided by the invention, comprising: display area and with
The adjacent non-display area in display area；Non-display area includes: circuit region and the test section adjacent with circuit region；Circuit region
It include: N data input line, N number of data signal input terminal being connected respectively with each Data In-Line, testing and control terminal,
And the N number of and one-to-one test module of each Data In-Line；Test section includes: the first test signal output terminal；M-th
Test module, for loading on the signal of testing and control terminal and loading on the signal in M+1 data input line
Under control, the signal loaded in M data input line is supplied to the first test signal output terminal；Wherein, 1≤M≤
N, and M and N are positive integer.Above-mentioned array base-plate structure provided in an embodiment of the present invention can be independent to every data input line
Test, the final electrical testing for realizing total data input line.Wherein, test module is connected to two adjacent Data In-Lines
Between, load the signal of testing and control terminal and load can will be right under the control of the signal of adjacent data input line
The test signal for the Data In-Line answered is supplied to the first test signal output terminal.Thus, it is only necessary to test signal first
Output terminal connecting test equipment can test the signal of every data input line.To the electricity of Data In-Line
The limitation of test no longer tested person position, test method is simple and quick, does not need the insulating layer destroyed in array substrate.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without any creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is one of the structural schematic diagram of arraying bread board provided in an embodiment of the present invention；
Fig. 2 is the second structural representation of arraying bread board provided in an embodiment of the present invention；
Fig. 3 is the third structural representation of arraying bread board provided in an embodiment of the present invention；
Fig. 4 is the four of the structural schematic diagram of arraying bread board provided in an embodiment of the present invention；
Fig. 5 is the domain of the non-display area of array substrate provided in an embodiment of the present invention；
Fig. 6 is the cross section structure schematic diagram of test module provided in an embodiment of the present invention；
Fig. 7 is signal wire connection relationship diagram provided in an embodiment of the present invention；
Fig. 8 is the cross section structure schematic diagram of test signal output terminal provided in an embodiment of the present invention；
Fig. 9 is the domain of the test section of array substrate provided in an embodiment of the present invention；
Figure 10 is circuit connecting relation schematic diagram in test section provided in an embodiment of the present invention；
Figure 11 is the flow chart of the test method of array substrate provided in an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into
It is described in detail to one step, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
All other embodiment, shall fall within the protection scope of the present invention.
Array substrate, its test method, display surface of specific embodiment of the invention offer are provided with reference to the accompanying drawing
Plate and display device.
As shown in Figure 1, array substrate provided in an embodiment of the present invention, comprising: display area AA and with display area AA
It is believed that non-display area BB.Further, non-display area BB further include: circuit region B1 and the survey adjacent with circuit region B1
Try area B2.
Wherein, circuit region B1 includes: N data input line 10, N number of data letter being connected respectively with each Data In-Line 10
Number input terminal Data, testing and control terminal ST and N number of with the one-to-one test module 20 of each Data In-Line 10；It surveys
Trying area B2 includes: the first test signal output terminal ctd.
The effect of test module in above-mentioned array substrate provided in an embodiment of the present invention is all the same, tests mould with m-th
For for block, m-th test module, for loading on the signal of testing and control terminal ST and loading on the M+1 articles number
Under control according to the signal in input line, it is defeated that the signal loaded in M data input line is supplied to the first test signal
Terminal ctd out；Wherein, 1≤M≤N, and M and N are positive integer.
Specifically, as shown in Figure 1, above-mentioned array substrate provided in an embodiment of the present invention, every data input line pass through more
Road gate (Multiplexer, abbreviation MUN) is connect with the data signal line 10 ' of display area, then driving chip (driving
IC) signal exported can be by each data signal line 10 ' of Data In-Line transmission line.As long as so detecting every data input line
Whether the signal loaded on 10 is abnormal, for determining driving IC, being fanned out to cabling and whether binding region interior cabling mentions extremely
For judgment basis.
Using the structure of above-mentioned array substrate provided in an embodiment of the present invention, every data input line can individually be surveyed
Examination, the final electrical testing for realizing total data input line.Wherein, test module be connected to two adjacent Data In-Lines it
Between, it can be by correspondence under the control of the signal of adjacent data input line in the signal of testing and control terminal and load loading
The test signal of Data In-Line be supplied to the first test signal output terminal.Thus, it is only necessary to defeated in the first test signal
Connecting test equipment at terminal out can test the signal of every data input line.It is worth noting that the last item
The corresponding test module of Data In-Line can connect the last item Data In-Line and the first data input line, and add
It is loaded in the signal of testing and control terminal and loads the last item data under the control of the signal of the first data input line
The test signal of input line is supplied to the first test signal output terminal and carries out electrical testing.It is provided in an embodiment of the present invention above-mentioned
For the structure in array substrate circuit area to the limitation of the electrical testing no longer tested person position of Data In-Line, test method is simply fast
Speed does not need the insulating layer destroyed in array substrate.Relatively existing electrical testing, the embodiment of the present invention use above-mentioned array base
For the structure of plate to the electrical testing of Data In-Line in terms of failure analysis, such as line badness can save 60% or more
Time.For product developer, it is this can in the method for test product internal data line signal, can be faster and better comment
Estimate, testing product performance.
In the specific implementation, as shown in Fig. 2, the specific structure of each test module is identical, by taking m-th test module as an example,
M-th test module 20, comprising: first switch transistor T1 and second switch transistor T2；The control of first switch transistor T1
The first pole of connecting test control terminal ST in pole processed, first switch transistor T1 connect M data input line, and first switch is brilliant
The first pole of the second pole connection second switch transistor T2 of body pipe T1；The control electrode of second switch transistor T2 connects M+1
Data input line, the first test of the second pole connection signal output terminal ctd of second switch transistor T2.
Specifically, when carrying out the signal testing of Data In-Line, in the transmission of the M data input line of confirmation detection
After signal, first control signal can be exported so that first switch transistor is on to testing and control terminal by driving IC
State, while second control signal is exported so that second switch transistor is in the conductive state to M+1 data input line, this
The normal test signal of Shi Xiang M data input line output can then make M data input line and the first test signal defeated
Access is formed between terminal out, then can test by oscillograph connection the first test signal output terminal to the M articles number
According to the signal of input line.At the same time, it can be inputted to the remainder data in addition to the M articles and M+1 data input line
Line exports third control signal so that the second transistor in the corresponding test module of remainder data input line is in closing shape
State thus can individually test the signal of M data input line, not by the interference of other Data In-Lines.For battle array
Every data input line in column substrate can repeat above-mentioned test method, thus to every data input line in array substrate
Signal individually test.
Further, as shown in Fig. 2, circuit region B1 further include: the first output signal line 11；Test section B2 further include: the
Two test signal output terminal st；Testing and control terminal ST passes through the first output signal line 11 and the second test signal output terminal
St is connected.
First output signal line 11 can connect the control electrode of first switch transistor in each test module 20, by that will survey
Examination control terminal ST is connected by the first output signal line 11 with the second test signal output terminal st, then being examined by oscillograph
Survey the signal of the second test signal output terminal st, it can detect whether testing and control terminal ST output signal is normal.
In above-mentioned array substrate provided in an embodiment of the present invention, as shown in figure 3, circuit region B1 further include: with it is each described
Test module one-to-one third switching transistor T3, the sub- CTSW1 of first switch control signal end；Second output signal line
12；Test section B2 further include: third tests signal output terminal ctsw1；The sub- CTSW1 of first switch control signal end passes through second
Output signal line 12 is connected with third test signal output terminal ctsw1；The control electrode of m-th third switching transistor T3 connects
The first pole of the sub- CTSW1 of first switch control signal end, third switching transistor T3 connect M data input line, and third is opened
Close the first test of the second pole connection signal output terminal ctd of transistor T3.
In practical applications, the signal testing of Data In-Line can be carried out after lighting test, above-mentioned first opens
Closing the sub- CTSW1 of control signal end and the second output signal line 12 can be the switch control signal end being arranged in lighting test
Son and signal wire.It is that each third switch crystalline substance is controlled by the sub- CTSW1 of first switch control signal end in existing test method
The conducting of body pipe, then the successively signal to each data input signal terminal load data-signal to test in every data input line.
However in this way when driving IC exception output signal wrong, since each third switching transistor is in conducting shape
State, data signal input terminal corresponding to every data input line are possible to the data-signal of loading error, all numbers
It is believed that number can be provided to the first test signal output terminal ctd, then detected by the first test signal output terminal ctd
Signal cannot then understand it is signal error in any data input line.Therefore in embodiments of the present invention, setting test mould
Block is connected between two adjacent data input lines, after lighting test terminates, is carried out to the signal of each Data In-Line
When test, the 4th control signal of CTSW1 load sub- to first switch control signal end is so that the corresponding third of each test module is opened
It closes transistor and is in closed state, then first opening of being then controlled by test module of the signal for loading on each Data In-Line
Transistor and second switch transistor are closed, the letter of each Data In-Line is connected without being caused by each third switching transistor
Number to the first test signal output terminal ctd output, the problem of obscuring of signal of test is caused.
Further, as shown in figure 4, circuit region B1 further include: the 4th switching transistor T4, second switch control signal end
Sub- CTSW2 tests signal input terminal CTD, third output signal line 13 and the 4th output signal line 14；Test section B2 is also
It include: the 4th test signal output terminal ctsw2；The sub- CTSW2 of second switch control signal end tests signal wire 13 by third
It is connected with the 4th test signal output terminal ctsw2；The control electrode connection second switch of 4th switching transistor T4 controls signal
The first pole connecting test signal input terminal CTD of terminal CTSW2, the 4th switching transistor T4, the 4th switching transistor T4's
Second pole passes through the first test of the 4th output signal line 14 connection signal output terminal ctd.
In the specific implementation, can make to drive IC to the sub- CTSW2 of second switch control signal end apply the 5th control signal with
The 4th switching transistor is set to be in state.The signal for avoiding driving IC from loading to test signal input terminal CTD generates test
It influences.And switching transistor when being in floating compared to being in close state for, can generate big electric leakage signal, be
Influence of the switching transistor electric leakage to test signal is avoided, applies the 5th control to the sub- CTSW2 of second switch control signal end
Signal is so that the 4th switching transistor is in state.
In above-mentioned array substrate provided in an embodiment of the present invention include each switching transistor can be thin film transistor (TFT), these are thin
Film transistor can be formed simultaneously with each thin film transistor (TFT) in driving circuit.P-type transistor can be selected in thin film transistor (TFT) or N-type is brilliant
Body pipe, it is not limited here.The non-display area domain of array substrate is as shown in figure 5, the first output signal line 11, second exports
Signal wire 12, third output signal line 13 and the 4th output signal line 14 can same layer formed, the control electrode of each switching transistor
It can be formed with each output signal line same layer.Each Data In-Line 10 may be formed at the metal layer on each output signal line,
When Data In-Line needs to connect with output signal line, via hole can be used and be attached.
When the driving transistor in array substrate and the switching transistor in test module are all made of thin film transistor (TFT),
The breadth length ratio that transistor is driven in the breadth length ratio of thin film transistor (TFT) in test module and driving circuit can be arranged unanimously, to protect
The performance for demonstrate,proving thin film transistor (TFT) is consistent, avoids the accuracy due to the test signal of transistor performance differentia influence.
Wherein, the structure of second switch transistor T2 and third switching transistor T3 are as shown in fig. 6, its manufacture craft can adopt
With low-temperature polysilicon bulk silicon technological, buffer layer 22 is formed on underlay substrate 21, forms the figure of active layer P on the buffer layer,
Gate insulation layer 23 is covered on active layer P, is formed the figure of grid (G1 and G2) on gate insulation layer 23, is formed interlayer on grid
Insulating layer 24 forms the via hole of exposure active layer on interlayer insulating film 24, forms source-drain electrode on interlayer insulating film 24
The figure of (S1, D1, S2, D2) forms flatness layer 25 on source-drain electrode, and protective layer 26 is formed on flatness layer 25.Array base
Double-gate structure can be used in each thin film transistor (TFT) on plate, improves response speed and avoids excessive leakage current.
As shown in fig. 7, the signal wire in gate metal layer Gate can be attached with Source and drain metal level SD by via hole,
For example, connection between the source-drain electrode and output signal line of switching transistor can be used such as figure in domain as shown in Figure 5
Connection relationship shown in 7, these connection via holes can be formed simultaneously when forming the via hole of contact electrode of source-drain electrode.It is specific
Manufacturing process steps it is similar to the above, furthermore repeat no more.
The cross section structure of each test signal terminal (ET Pad) of test section as shown in figure 8, its manufacturing process can with it is above-mentioned
Production process it is almost the same, the difference is that, the via hole being formed between Source and drain metal level SD and gate metal layer Gate
It is more compared to the via hole of circuit region, the metal layer of test section can in this way contacted more preferable, form flatness layer 25
After protective layer 26, test section can be performed etching, exposure Source and drain metal level forms conductive layer 27 on the source-drain metal layer
Figure, the conductive layer can be used the transparent conductive materials such as ITO and made, can be by the folder of oscillograph when carrying out electrical testing
Tool is in contact with conductive layer 27, to test the signal of each Data In-Line.
Due to array substrate provided in an embodiment of the present invention, test module is added in circuit region, therefore corresponding in test section
Ground needs to increase the signal output terminal for test control signal and first switch control signal, as shown in figure 9, can be
Increase by two signal output terminals st and ctsw2 on the basis of existing test plot structure.In addition to this, as shown in figure 9, also wrapping
It includes: flexible circuit board (Flexible Printed Circuit, abbreviation FPC) connection terminal 1, silver paste connection terminal 2, test letter
Number output terminal 3 (i.e. existing electrical testing terminal), alignment mark 4 bind area's connection terminal 5, are fanned out to cabling 6.Each connection
The effect of terminal is identical as effect in the prior art, and details are not described herein again.
Similarly, it due to the change of circuit region and test section, then is also required to make corresponding change on lighting jig,
As shown in Figure 10, two contact probes additionally can be set for two newly-increased signal output terminals on lighting jig, for mentioning
For lighting test signal.
It in practical applications, may include Three models in following table to the electrical testing of display panel.
First before the display panel that completes, unbound driving IC, test signal is provided to display from signal source PG
Each data signal line of panel exports, and carries out lighting electrical testing (Cell ET) to display panel, and whether detection display panel is deposited
In bad point.The binding driving IC after display panel lighting test no exceptions, then carry out mould group electrical testing (Module
ET), test signal is provided by driving IC.Offer of the embodiment of the present invention can be carried out again after mould group electrical testing does not generate exception
Above-mentioned Data In-Line electrical testing (Test ET), whether the signal for testing each Data In-Line abnormal.Above-mentioned three kinds of electricity
It is as shown above for the on-load voltage of each signal terminal to learn test pattern.
The test method of above-mentioned array substrate based on the embodiment of the present invention is specifically introduced below, such as Figure 11
Shown, test method provided in an embodiment of the present invention can specifically include following steps:
S10, first control signal is loaded to testing and control terminal, to m-th data signal input terminal load data letter
Number, second control signal is loaded to the M+1 data signal input terminal, to its remainder in addition to m-th and M+1
Signal is controlled according to signal input terminal load third, it is defeated that the signal of control M data input line is supplied to the first test signal
Terminal out；
The signal of S20, detection the first test signal output terminal；
Wherein, 1≤M≤N, and M and N are positive integer.
Specifically, above-mentioned test module includes that first switch transistor and second close transistor, the two switching transistors
Circuit connecting relation referring to fig. 2, to M data input line carry out electrical testing when, testing and control terminal can be loaded
First control signal, control first switch transistor processing load the on state, to the M+1 data signal input terminal
Two control signals, the second switch transistor controlled in test module corresponding with M data input line are also at conducting shape
State, to except m-th and M+1 and in addition to remainder data signal input terminal load third control signal, so as to remove the M articles
The second switch transistor in the corresponding test module of remainder data input line other than Data In-Line is in closed state；
At this point, can detect this at the first test signal output terminal when loading data-signal to m-th data signal input terminal
Signal in data input line repeats the achievable test to total data input line of aforesaid operations.
Further, when above-mentioned array substrate provided in an embodiment of the present invention further includes third switching transistor, structure
As shown in figure 3, above-mentioned test method may also include that
First control signal is being loaded to testing and control terminal, data-signal is loaded to m-th data signal input terminal,
Second control signal is loaded to the M+1 data signal input terminal, to the remainder data in addition to m-th and M+1
While signal input terminal loads third control signal, to the 4th control signal of first control signal terminal load, control the
Three switching transistors are closed.
Specifically, when the signal loaded on to each Data In-Line is tested, first control signal terminal can be added
The 4th control signal is carried, control third switching transistor handles closed state always, when breaking down to avoid driving IC, the
One test signal output terminal can not detect that the signal of which data input line breaks down.
Further, when above-mentioned array substrate provided in an embodiment of the present invention further include: when four switching transistors, structure
As shown in figure 4, above-mentioned test mode may also include that
First control signal is being loaded to testing and control terminal, data-signal is loaded to m-th data signal input terminal,
Second control signal is loaded to the M+1 data signal input terminal, to the remainder data in addition to m-th and M+1
While signal input terminal loads third control signal, to the 5th control signal of second control signal terminal load, control the
Four switching transistors are closed.
Specifically, when the signal loaded on to each Data In-Line is tested, second control signal terminal can be added
The 5th control signal is carried, the 4th switching transistor of control is in close state always, and the 4th switching transistor is avoided to be in suspension joint
State also avoids the test structure of the CTD data signal input line of driving IC or FPC output from having an impact.
Thin film transistor (TFT) or semiconductor field can be used in above-mentioned each switching transistor provided in an embodiment of the present invention,
This is without limitation.The control of transistor extremely grid, the first extremely source electrode, second extremely drains, and the function of source electrode and drain electrode can
To exchange.When above-mentioned each transistor is all made of N-type transistor, above-mentioned control transistor the first control letter in the conductive state
Number, second control signal can be high level signal, the third control signal that control transistor is in close state, the 4th control letter
Number and the 5th control signal can be low level signal；And when above-mentioned each transistor is all made of P-type transistor, above-mentioned control is brilliant
Body pipe first control signal in the conductive state, second control signal can be low level signal, and control transistor, which is in, closes
The third of state controls signal, and the 4th control signal and the 5th control signal can be high level signal.
Based on the same inventive concept, the specific embodiment of the invention additionally provides a kind of display panel, which includes
The above-mentioned arraying bread board that the specific embodiment of the invention provides, the principle and above-mentioned array phase solved the problems, such as due to the display panel
Seemingly, therefore the implementation of the display device may refer to the implementation of above-mentioned display panel, and overlaps will not be repeated.
In addition, the specific embodiment of the invention additionally provides a kind of display device, which includes that the present invention is specific real
The above-mentioned display panel of example offer is applied, which can be the displays such as liquid crystal display panel, liquid crystal display, LCD TV dress
It sets.Since the principle that the display device solves the problems, such as is similar to above-mentioned display panel, the implementation of the display device can be joined
See the implementation of above-mentioned display panel, overlaps will not be repeated.
Above-mentioned array substrate, its test method, display panel and display device provided in an embodiment of the present invention, comprising: aobvious
Show region and the non-display area adjacent with display area；Non-display area includes: circuit region and the survey adjacent with circuit region
Try area；Circuit region includes: N data input line, and N number of data signal input terminal being connected respectively with each Data In-Line is surveyed
Try control terminal and the N number of and one-to-one test module of each Data In-Line；Test section includes: that the first test signal is defeated
Terminal out；M-th test module, for loading on the signal of testing and control terminal and loading on the input of M+1 data
Under the control of signal on line, the signal loaded in M data input line is supplied to the first test signal output terminal；
Wherein, 1≤M≤N, and M and N are positive integer.Above-mentioned array base-plate structure provided in an embodiment of the present invention can be to every number
It is individually tested according to input line, the final electrical testing for realizing total data input line.Wherein, test module is connected to adjacent two
Between root Data In-Line, load testing and control terminal signal and load adjacent data input line signal control
System is lower can be supplied to the first test signal output terminal for the test signal of corresponding Data In-Line.Thus, it is only necessary to
Connecting test equipment at first test signal output terminal, can test the signal of every data input line.To data
The limitation of the electrical testing of input line no longer tested person position, test method is simple and quick, does not need to destroy in array substrate
Insulating layer.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
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