CN109088532B - A current mode segmented gate drive circuit with active clamp - Google Patents

Abstract

A current type segmented gate drive circuit with active clamping belongs to the technical field of electronic circuits. The low-side drive module is used for enhancing the drive capability of a pulse width modulation signal and taking the pulse width modulation signal as a grid control signal of a lower power tube; the high-side logic module converts a power supply rail of a pulse width modulation signal into a floating power supply rail and then takes the power supply rail as a high-side driving control signal, the high-side driving module generates a grid control signal of an upper power tube under the control of the high-side driving control signal, and the high-side driving module and the upper power tube form a current mirror to carry out constant current charging on the grid driving signal; the middle-side bias module is used for ensuring that the upper power tube is not broken down and ensuring that the upper power tube is in a saturation region during the working period. The invention saves the area of a chip layout, reduces the cost of a peripheral circuit and has smaller driving-level noise under the condition of meeting the driving capability.

Description

A current mode segmented gate drive circuit with active clamp

technical field

The invention belongs to the technical field of electronic circuits, and relates to a current-mode segmented gate drive circuit with active clamping.

Background technique

In order to reduce the conduction loss of the power transistor in the power management chip, the gate potential as high as possible is usually required. For AC-DC power chips such as flyback transformer Flyback, high voltage drive is usually required. In order to make the gate signal driving signal voltage high enough to break down the external power transistor, the chip usually needs to use an additional low-dropout linear regulator LDO to provide a separate suitable higher-voltage power rail to power the entire driving circuit. The typical implementation block diagram is shown in the figure As shown in 1, firstly, the LDO is used to supply the chip supply voltage VDD with a suitable high-voltage power rail Vcc to supply power to the drive circuit, and the pulse width modulation signal PWM is divided into the upper power logic signal and the lower power logic signal under the action of the upper/lower power tube control signal generation unit. Power tube logic signal, in which the upper power tube logic signal branch is the dotted box ① It requires Vcc and Vcc-5V high-voltage floating power rails, of which 5V is the output voltage of the LDO inside the power management chip, and the lower power tube logic signal branch is like the dotted line Box ② requires a 5V-0V power rail, and then, under the action of the drive enhancement unit, the drive signals HS_G and LS_G with enhanced drive capability are generated to drive the internal voltage-resistant upper and lower power tubes HP1 and HN1 of the last stage. The gate driving signal DRV drives the external high voltage power transistor M3.

However, this traditional gate drive circuit has four power rails, 5V, 0V, Vcc, and Vcc-5V. The 5V power rail is provided by the LDO of the system itself, the Vcc power rail needs to be provided by an additional LDO, and the Vcc-5V power rail is A floating circuit is required to generate. Due to the need for sufficient driving capacity, a large voltage regulator capacitor is usually required and cannot be integrated on-chip. External large capacitors must be used, which increases the cost of peripheral circuits; the Vcc-5V power rail needs to supply power to the driver enhancement unit to stabilize Piezoelectric capacitors can be integrated but need to consume a large layout area and increase the chip cost.

SUMMARY OF THE INVENTION

Aiming at the problems existing in the above-mentioned traditional gate drive circuits, such as the need for additional LDOs and external large capacitors, which leads to the increase of the cost of peripheral circuits and the increase of the layout area, the present invention proposes a current-mode segmented gate drive circuit with active clamping, Using segmented current drive, the noise of the drive stage is lower under the condition of satisfying the drive capability; no additional LDO is needed to provide the power rail of the drive circuit, and no external capacitor is required, which saves the chip layout area and reduces the cost of peripheral circuits.

The technical scheme of the present invention is:

A current mode segmented gate drive circuit with active clamping is suitable for a power management chip, the power management chip includes a low dropout linear voltage regulator, and the current mode segmented gate drive circuit includes a power stage and a A low-side drive module, the power stage includes an upper power transistor MP0, a lower power transistor HN2 and a thirteenth PMOS transistor HP2, and the low-side drive module enhances the drive capability of the pulse width modulation signal PWM generated by the power management chip Then it is used as the gate control signal LDRV of the lower power transistor HN2, and the drain of the lower power transistor HN2 is connected to the drain of the thirteenth PMOS transistor HP2 and is output as the output end of the current-mode segmented gate drive circuit. The gate drive signal DRV, the source of which is connected to the power ground PGND;

The current-mode segmented gate drive circuit further includes a high-side logic module, a high-side drive module, a mid-side bias module and an active clamp module,

The high-side logic module is used to convert the power rail of the pulse width modulation signal PWM to a floating power rail as a high-side drive control signal HDRV_Ctrl, and the floating power rail is the power supply voltage VDD minus the low dropout linear voltage regulator the output voltage of the device to the power supply voltage VDD;

The high-side driver module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fourteenth PMOS transistor HP3, a first NMOS transistor MN1, a second NMOS transistor MN2, The third NMOS transistor MN3, the fourth NMOS transistor HN3, the fifth NMOS transistor HN4, the third resistor R3, the seventh resistor RST and the first current source I1,

The gate of the first NMOS transistor MN1 is connected to the sampling signal DRV_Sense of the gate driving signal DRV, its drain is connected to the source of the fourth NMOS transistor HN3, and its source is connected to the source of the second NMOS transistor MN2 and passes the first current Ground GND after source I1;

The gate of the fourth NMOS transistor HN3 is connected to the output voltage of the low-dropout linear regulator, and its drain is connected to the gate and drain of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2;

The gate of the second NMOS transistor MN2 is connected to the first reference voltage REF1, and the drain thereof is connected to the source of the third NMOS transistor MN3;

The gate of the third NMOS transistor MN3 is connected to the pulse width modulation signal PWM, and the drain thereof is connected to the source of the fifth NMOS transistor HN4;

The gate of the fifth NMOS transistor HN4 is connected to the output voltage of the low-dropout linear regulator, and the drain thereof is connected to the drains of the second PMOS transistor MP2, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 and the fourteenth PMOS transistor The gate of the tube HP3 is connected to the power supply voltage VDD after passing through the seventh resistor RST;

The gate of the third PMOS transistor MP3 is connected to the inversion signal of the high-side drive control signal HDRV_Ctrl, and its source is connected to the sources of the first PMOS transistor MP1, the second PMOS transistor MP2 and the fourth PMOS transistor MP4 and is connected to the power supply voltage VDD;

The source of the fourteenth PMOS transistor HP3 is connected to the gate of the fourth PMOS transistor MP4 and the gate of the upper power transistor MP0, and is connected to the power supply voltage VDD through the third resistor R3, and its drain is grounded to GND;

The source of the upper power transistor MP0 is connected to the power supply voltage VDD, and its drain is connected to the source of the thirteenth PMOS transistor HP2;

The mid-side bias module includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fifteenth PMOS transistor HP4, a sixth NMOS transistor HN5, and a seventh NMOS transistor HN6 , the fourth resistor R4, the first capacitor C1, the second current source I2 and the third current source I3,

The gate of the sixth NMOS transistor HN5 is connected to the output voltage of the low-dropout linear regulator, its source is grounded to GND through the second current source I2, and its drain is connected to the gate and drain of the fifth PMOS transistor MP5 and the gates of the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8;

The gate of the seventh PMOS transistor MP7 is connected to the drain of the sixth PMOS transistor MP6, the source of the thirteenth PMOS transistor HP2 and one end of the fourth resistor R4, and its source is connected to the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 It is connected to the power supply voltage VDD with the source of the eighth PMOS transistor MP8, and its drain is connected to the gate of the fifteenth PMOS transistor HP4 and the drain of the seventh NMOS transistor HN6, and is connected to the fourth resistor R4 through the first capacitor C1. another side;

The gate of the seventh NMOS transistor HN6 is connected to the output voltage of the low-dropout linear regulator, and its source is grounded to GND after passing through the third current source I3;

The source of the fifteenth PMOS transistor HP4 is connected to the drain of the eighth PMOS transistor MP8 and the gate of the thirteenth PMOS transistor HP2, and its drain is grounded to GND;

The active clamping module is used for clamping the gate driving signal DRV.

Specifically, the active clamp module includes an eighth NMOS transistor HN7, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a fifth resistor R5, a sixth Resistor R6, fourth current source I4 and Zener Z,

The gate of the tenth PMOS transistor MP10 is connected to the gate and drain of the ninth PMOS transistor MP9 and is grounded to GND after passing through the fourth current source I4, and its source is connected to the source of the ninth PMOS transistor MP9 and is connected to the low dropout linear The output voltage of the voltage regulator, the drain of which is connected to the gate of the twelfth PMOS transistor MP12 and the source of the eleventh PMOS transistor MP11;

The gate of the eleventh PMOS transistor MP11 is connected to the second reference voltage REF2, and the drain thereof is connected to the source of the eighth NMOS transistor HN7 and grounded to GND;

The gate of the eighth NMOS transistor HN7 is connected to the drain of the twelfth PMOS transistor MP12 through the fifth resistor R5 on the one hand, and is grounded to GND through the sixth resistor R6 on the other hand, and its drain is connected to the cathode of the Zener Z and the the gate drive signal DRV;

The anode of the Zener transistor Z is connected to the source of the twelfth PMOS transistor MP12.

Specifically, the current-mode segmented gate drive circuit further includes a series connection consisting of a first resistor R1 and a second resistor R2 connected between the output end of the current-mode segmented gate drive circuit and the power ground PGND structure, whose series point outputs the sampling signal DRV_Sense.

The beneficial effects of the present invention are:

1. There is no need for additional LDOs to provide power rails, which simplifies the system circuit, saves the chip layout area, does not require additional voltage regulator capacitors, and reduces the cost of peripheral circuits.

2. The floating power rail only supplies power to simple gate-level circuits, which reduces the area of the voltage regulator capacitor and saves the layout area of the chip.

3. The drive circuit is driven by segmented current, and the noise of the drive stage is smaller under the condition of satisfying the drive capability.

Description of drawings

Figure 1 is a topology diagram of a traditional high-voltage gate drive circuit.

FIG. 2 is a topological structure diagram of a current-mode segmented gate drive circuit with active clamping proposed by the present invention.

FIG. 3 is a schematic structural diagram of a high-side driving module in the present invention.

FIG. 4 is a schematic structural diagram of a mid-side bias module in the present invention.

FIG. 5 is a schematic structural diagram of a circuit implementation of the active clamp module in the present invention.

FIG. 6 is a basic timing logic diagram in the present invention.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in FIG. 2, a current-mode segmented gate drive circuit with active clamping proposed by the present invention is used to generate a gate drive signal DRV for driving an external power transistor, and is suitable for power management chips. The present invention includes power stage, a low-side driver module, a high-side logic module, a high-side driver module, a mid-side bias module and an active clamp module, wherein the power stage includes an upper power transistor MP0, a lower power transistor HN2 and a thirteenth PMOS transistor HP2, Among them, the upper power tube MP0 and the lower power tube HN2 are internal power tubes of the power management chip. Due to the large current spike in the power stage, under the influence of the didt effect, the ground potential will vibrate, so the power stage is connected to the power ground PGND; the low side The driving module is used to enhance the driving ability of the pulse width modulation signal PWM generated by the power management chip, and use it as the gate control signal LDRV of the lower power tube HN2, and the gate control signal LDRV of the lower power tube HN2 output by the low-side driving module In the same phase as the pulse width modulation signal PWM, the power rail is 0V to the output voltage of the low dropout linear regulator LDO in the power management chip; the high-side logic module uses the floating power rail circuit to convert the power rail of the pulse width modulation signal PWM to a floating power supply After the rail is used as the high-side drive control signal HDRV_Ctrl, the power rail of the pulse width modulation signal PWM is 0V to the output voltage of the low dropout linear regulator LDO in the power management chip, and the floating power rail is the power supply voltage VDD minus the LDO in the power management chip From the output voltage to the power supply voltage VDD, the following takes the output voltage of the low-dropout linear regulator LDO in the power management chip as 5V as an example, the function of the high-side logic module is to change the power rail of the pulse width modulation signal PWM from 0V to 5V Convert to VDD-5V to VDD, use the digital signal converted to the floating power rail as the high-side drive control signal HDRV_Ctrl, the high-side drive control signal HDRV_Ctrl and the pulse width modulation signal PWM are digital signals in the same phase; the high-side drive module is on the high-side The gate control signal HDRV of the upper power transistor MP0 is generated under the control of the drive control signal HDRV_Ctrl. The high-side drive module and the upper power transistor MP0 form a current mirror to charge the gate drive signal DRV of the external power transistor with constant current. The middle-side bias module Ensure that the drain-source voltage of the upper power tube MP0 will not be too large to be broken down, and at the same time ensure that the upper power tube MP0 is in the saturation region during operation; the power rail of the low-side driver module is powered by the 0-5V power rail; the high-side driver module and The mid-side bias module is directly powered by the power supply voltage of the power management chip, that is, the power supply voltage VDD, and does not require an additional LDO to establish a new power rail; the power driver stage is responsible for generating the gate drive signal DRV, and the active clamp module is used to detect the gate drive. The signal DRV, when the voltage of the gate drive signal DRV rises to a preset voltage value, reaches a stable preset value under the action of the loop, so the gate drive signal DRV is finally stabilized under the action of the active clamp circuit. at the preset higher voltage.

The specific control method is analyzed in detail below in conjunction with the specific circuit.

The high-side drive module proposed by the present invention is used to provide segment gate drive current: the schematic diagram of the circuit is shown in FIG. 3 , including a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor. MP4, the fourteenth PMOS transistor HP3, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor HN3, the fifth NMOS transistor HN4, the third resistor R3, the seventh resistor RST and the first A current source I1, wherein the seventh resistor RST is a large resistor, the gate of the first NMOS transistor MN1 is connected to the sampling signal DRV_Sense of the gate driving signal DRV, its drain is connected to the source of the fourth NMOS transistor HN3, and its source is connected to the first NMOS transistor HN3. The sources of the two NMOS transistors MN2 are grounded after passing through the first current source I1; the gate of the fourth NMOS transistor HN3 is connected to the output voltage of the low dropout linear regulator, and its drain is connected to the gate and drain of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2; the gate of the second NMOS transistor MN2 is connected to the first reference voltage REF1, and its drain is connected to the source of the third NMOS transistor MN3; the gate of the third NMOS transistor MN3 is connected to the pulse width The modulation signal PWM, its drain is connected to the source of the fifth NMOS tube HN4; the gate of the fifth NMOS tube HN4 is connected to the output voltage of the low dropout linear regulator, and its drain is connected to the second PMOS tube MP2 and the third PMOS tube The drains of MP3 and the fourth PMOS transistor MP4 and the gate of the fourteenth PMOS transistor HP3 are connected to the power supply voltage VDD through the seventh resistor RST; the gate of the third PMOS transistor MP3 is connected to the inversion of the high-side drive control signal HDRV_Ctrl The signal is NHDRV_Ctrl, the source of which is connected to the sources of the first PMOS transistor MP1, the second PMOS transistor MP2 and the fourth PMOS transistor MP4 and is connected to the power supply voltage VDD; the source of the fourteenth PMOS transistor HP3 is connected to the fourth PMOS transistor MP4. The gate and the gate of the upper power transistor MP0 are connected to the power supply voltage VDD through the third resistor R3, and its drain is grounded; the source of the upper power transistor MP0 is connected to the power supply voltage VDD, and its drain is connected to the thirteenth PMOS transistor HP2. source.

The sampling signal DRV_Sense of the gate driving signal DRV can be obtained by a series structure composed of a first resistor R1 and a second resistor R2, and the first resistor R1 and the second resistor R2 are connected in series and parallel to the output end of the current mode segmented gate drive circuit and the second resistor R2. Between the power ground and PGND, the series point outputs the sampling signal DRV_Sense. During the period when the pulse width modulation signal PWM is at a high level, the voltage division detection unit formed by the first resistor R1 and the second resistor R2 detects the voltage value of the output gate drive signal DRV .

The sampling signal DRV_Sense obtained by sampling controls the current flowing through the fourth PMOS transistor MP4 through the differential pair formed by the first NMOS transistor MN1 and the second NMOS transistor MN2. After the pulse width modulation signal PWM is high, the gate driving signal DRV is initially 0, the voltage of the sampling signal DRV_Sense is much lower than the first reference voltage REF1, and the current all flows through the seventh resistor RST and the fourth PMOS transistor MP4. The fourth PMOS transistor MP4, the fourteenth PMOS transistor HP3, the third resistor R3 and the upper power transistor MP0 actually constitute a beta-helper current mirror. Since the seventh resistor RST is relatively large, the tail current, that is, the first current source I1 all flows through the fourth PMOS transistor MP4. At this time, the source current (that is, the sink current or the outflow current) capability of the drive circuit, the current of the upper power tube MP0 can be expressed as:

Wherein (W/L) _MP0 and (W/L) _MP4 are the width-length ratios of the upper power tube MP0 and the fourth PMOS tube MP4, and the current I _MP0 flowing through the upper power tube MP0 charges the gate of the external power tube, The voltage of the gate driving signal DRV rises linearly according to the constant current charging, and the sampling signal DRV_Sense also rises linearly. When the sampling signal DRV_Sense rises to the vicinity of the first reference voltage REF1, under the action of the differential pair formed by the first NMOS transistor MN1 and the second NMOS transistor MN2, the first PMOS transistor MP1 and the second PMOS transistor MP2 also begin to flow current. , the current flowing through the fourth PMOS transistor MP4 also gradually decreases, and the Source current capability of the driving circuit decreases. Until the voltages of the sampling signal DRV_Sense and the first reference voltage REF1 are equal, the current flowing through the fourth PMOS transistor MP4 is 0, and the upper power transistor MP0 no longer provides driving capability to the external power transistors. The high-side driving module dynamically adjusts the driving current by detecting the voltage of the gate driving signal DRV, thus realizing the current segmented driving.

4 is a circuit structure diagram of a mid-side bias module, including a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fifteenth PMOS transistor HP4, and a sixth NMOS transistor HN5 , the seventh NMOS transistor HN6, the fourth resistor R4, the first capacitor C1, the second current source I2 and the third current source I3, the gate of the sixth NMOS transistor HN5 is connected to the output voltage of the low dropout linear regulator, and its source The electrode is grounded after passing through the second current source I2, and its drain is connected to the gate and drain of the fifth PMOS transistor MP5 and the gates of the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8; the gate of the seventh PMOS transistor MP7 is connected to The drain of the sixth PMOS transistor MP6, the source of the thirteenth PMOS transistor HP2 and one end of the fourth resistor R4, the sources of which are connected to the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8 And connected to the power supply voltage VDD, its drain is connected to the gate of the fifteenth PMOS transistor HP4 and the drain of the seventh NMOS transistor HN6, and is connected to the other end of the fourth resistor R4 after passing through the first capacitor C1; the seventh NMOS transistor HN6 The gate is connected to the output voltage of the low-dropout linear regulator, and its source is grounded through the third current source I3; the source of the fifteenth PMOS tube HP4 is connected to the drain of the eighth PMOS tube MP8 and the thirteenth PMOS tube HP2 , and its drain is grounded.

In order to ensure that the β-helper current mirror formed by the fourth PMOS transistor MP4, the fourteenth PMOS transistor HP3, the third resistor R3 and the upper power transistor MP0 can be mirrored normally, the upper power transistor MP0 should be in the saturation region when the gate drive signal DRV rises. . Point A in FIG. 4 , that is, the gate terminal voltage of the seventh PMOS transistor MP7 is VA ₌ VDD-V _GS,MP7 , where V _GS,MP7 is the gate-source voltage of the seventh PMOS transistor MP7 . The seventh PMOS transistor MP7 is composed of the fourth PMOS transistor MP4, the lower power transistor HN2, the default pull-down resistors, namely the first resistor R1 and the second resistor R2, the gate capacitance of the external power transistor, the seventh PMOS transistor MP7, and the seventh NMOS transistor. The loop formed by HN6, the third current source I3, the eighth PMOS transistor MP8 and the fifteenth PMOS transistor HP4 is biased in the saturation region, and the drain voltage of the seventh PMOS transistor MP7 can be expressed as:

V _{SD, MP7} = V _{GS, HP4} +V _{GS, HP2} +V _{GS, MP7}

Wherein V _{GS, HP4} and V _{GS, HP2} are the gate-source voltages of the fifteenth PMOS transistor HP4 and the thirteenth PMOS transistor HP2 respectively, and the drain terminal voltage V _{SD, MP7} of the seventh PMOS transistor MP7 is higher than its gate terminal voltage, Therefore, the seventh PMOS transistor MP7 is always in the saturation region. In the above, the fourth PMOS transistor MP4, the lower power transistor HN2, the default pull-down resistors, namely the first resistor R1 and the second resistor R2, the gate capacitance of the external power transistor, the seventh PMOS transistor MP7, the seventh NMOS transistor HN6, the third In the loop formed by the current source I3, the eighth PMOS transistor MP8 and the fifteenth PMOS transistor HP4, the loop stability must be carefully considered. Among them, the current of the thirteenth PMOS tube HP2 is the sum of the currents of the upper power tube MP0 and the sixth PMOS tube MP6. The current of the upper power tube MP0 is different in different stages of driving, and the loop stability conditions also change accordingly. . A compensation capacitor, namely the first capacitor C1, and a compensation resistor, namely the fourth resistor R4, are connected in series between the gate and drain of the seventh PMOS transistor MP7, and Miller compensation is used to improve the loop stability. The middle point A of the loop is the main pole, the drain node of the seventh PMOS transistor MP7 is the secondary pole, the secondary pole remains unchanged, and the main pole increases with the increase of the current of the thirteenth PMOS transistor HP2. Therefore, it is only necessary to ensure that the loop can be stable when the current of the thirteenth PMOS transistor HP2 is the largest, and then the loop can be stable at any other time. In fact, the current flowing through the sixth PMOS transistor MP6 can not only ensure the normal operation of the loop, but also can reduce the default pull-down resistance of the output terminal DRV of the current-mode segmented gate drive circuit (ie, the first resistance) with a small current. R1 and the second resistor R2) and other leakage paths (including the drain terminal of the eighth NMOS transistor HN7 in the active clamp module to the parasitic diode of the substrate) provide current to ensure that the output gate drive signal DRV is charged to the preset value stable at the driving voltage.

The active clamp module is used to clamp the gate drive signal DRV. FIG. 5 is a circuit implementation diagram of the active clamp module, including the eighth NMOS transistor HN7, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, and the tenth PMOS transistor MP10. A PMOS transistor MP11, a twelfth PMOS transistor MP12, a fifth resistor R5, a sixth resistor R6, a fourth current source I4 and a Zener transistor Z, the gate of the tenth PMOS transistor MP10 is connected to the gate of the ninth PMOS transistor MP9 and the drain and grounded after passing through the fourth current source I4, its source is connected to the source of the ninth PMOS transistor MP9 and the output voltage of the low-dropout linear regulator, and its drain is connected to the gate of the twelfth PMOS transistor MP12 and the source of the eleventh PMOS transistor MP11; the gate of the eleventh PMOS transistor MP11 is connected to the second reference voltage REF2, and its drain is connected to the source of the eighth NMOS transistor HN7 and grounded; the gate of the eighth NMOS transistor HN7 On the one hand, it is connected to the drain of the twelfth PMOS transistor MP12 through the fifth resistor R5, and on the other hand, it is connected to the ground through the sixth resistor R6, and its drain is connected to the cathode of the Zener Z and the gate drive signal DRV; the Zener Z The anode is connected to the source of the twelfth PMOS transistor MP12.

When the upper power transistor MP0 exits, only the current of the sixth PMOS transistor MP6 is left to charge the gate driving signal DRV. When the voltage of the gate driving signal DRV rises slowly, the twelfth PMOS transistor MP12 and the eighth NMOS transistor HN7 remain off until When the gate driving signal DRV voltage rises to the preset driving voltage V _DRV =V _REF2 +V _{GS, MP11} +V _{th, MP12} +V _Z , the Zener Z is broken down, the twelfth PMOS transistor MP12 and the eighth NMOS The transistor HN7 starts to conduct, and the eighth NMOS transistor HN7 equalizes the excess current of the sixth PMOS transistor MP6, wherein V _{GS, MP11} , V _{th, MP12} and V _Z are the gate-source voltage of the eleventh PMOS transistor MP11, the The threshold voltage of the twelve PMOS transistors MP12 and the voltage across the Zener transistor Z.

栅驱动信号DRV上升较快；t1～t2时间段为米勒平台，此时栅驱动信号DRV保持不变，外部功率管漏端电压逐渐上升；t2～t3时间段本发明的栅极驱动电路的Source电流能力与0-t1时间段相同；t3-t4时间段内，本发明的栅极驱动电路的驱动电流逐渐下降，栅驱动信号DRV斜率慢慢降低；t4-t5时间段内，栅驱动信号DRV电压保持不变，稳压值为V_y＝V_REF2+V_GS,MP11+V_th,MP12+V_Z；在t5时刻，脉冲宽度调制信号PWM下降沿来临，t5-t6时间段内，本发明的栅极驱动电路下拉栅驱动信号DRV使得外部功率管关断。FIG. 6 is a basic logic timing diagram of the present invention. The timing relationship between the pulse width modulation signal PWM and the gate drive signal DRV can be clearly seen from the logic control diagram, and the transmission delay of the pulse width modulation signal PWM is ignored. When the pulse width modulation signal PWM rises, the Source current capability of the gate drive circuit of the present invention in the time period from 0 to t1 is:

The gate drive signal DRV rises rapidly; the time period from t1 to t2 is the Miller plateau, at this time the gate drive signal DRV remains unchanged, and the drain voltage of the external power tube gradually rises; the time period from t2 to t3 The gate drive circuit of the present invention The source current capability is the same as in the 0-t1 time period; in the t3-t4 time period, the driving current of the gate driving circuit of the present invention gradually decreases, and the gate driving signal DRV slope gradually decreases; in the t4-t5 time period, the gate driving signal The DRV voltage remains unchanged, and the voltage regulation value is V _y =V _REF2 +V _{GS, MP11} +V _{th, MP12} +V _Z ; at t5 time, the falling edge of the pulse width modulation signal PWM comes, and during the t5-t6 time period, the current The inventive gate driving circuit pulls down the gate driving signal DRV to turn off the external power transistor.

The key of the present invention is to control the driving current of the high-side driving module in the present invention by sampling the voltage of the gate driving signal DRV, so that the high-side driving module can generate segmented current driving capability and reduce the dv/dt effect of the gate driving circuit. At the same time, the entire driving circuit of the present invention is powered by the chip power supply voltage, that is, the power supply voltage VDD, and no additional LDO is required to provide the power rail, which simplifies the system circuit, saves the chip layout area, does not require additional voltage-stabilizing capacitors, and reduces peripheral circuits. cost.

Those skilled in the art can make various other specific modifications and combinations without departing from the essence of the present invention according to the technical teaching disclosed in the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

Claims (3)

1. A current type segmented gate drive circuit with active clamp is suitable for a power management chip, the power management chip comprises a low dropout linear regulator, the current type segmented gate drive circuit comprises a power stage and a low-side drive module, the power stage comprises an upper power tube (MP0), a lower power tube (HN2) and a thirteenth PMOS tube (HP2), the low-side drive module enhances the driving capability of a pulse width modulation signal (PWM) generated by the power management chip to be used as a gate control signal (LDRV) of the lower power tube (HN2), the drain electrode of the lower power tube (HN2) is connected with the drain electrode of the thirteenth PMOS tube (HP2) and used as the output end of the current type segmented gate drive circuit to output a gate drive signal (DRV), and the source electrode of the lower power tube is connected with a Power Ground (PGND);

characterized in that the current type segmented gate drive circuit also comprises a high-side logic module, a high-side drive module, a middle-side bias module and an active clamping module,

the high-side logic module is used for converting a power supply rail of the pulse width modulation signal (PWM) to a floating power supply rail to be used as a high-side driving control signal (HDRV _ Ctrl), wherein the floating power supply rail is the power supply Voltage (VDD) minus the output voltage of the low dropout linear regulator to be the power supply Voltage (VDD);

the high-side driving module comprises a first PMOS (P-channel metal oxide semiconductor) tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a fourth PMOS tube (MP4), a fourteenth PMOS tube (HP3), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3), a fourth NMOS tube (HN3), a fifth NMOS tube (HN4), a third resistor (R3), a seventh Resistor (RST) and a first current source (I1), wherein the seventh Resistor (RST) is a large resistor;

the grid electrode of the first NMOS tube (MN1) is connected with a sampling signal (DRV _ Sense) of the gate driving signal (DRV), the drain electrode of the first NMOS tube is connected with the source electrode of the fourth NMOS tube (HN3), and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube (MN2) and is Grounded (GND) after passing through the first current source (I1);

the grid electrode of the fourth NMOS tube (HN3) is connected with the output voltage of the low dropout linear regulator, and the drain electrode of the fourth NMOS tube is connected with the grid electrode and the drain electrode of the first PMOS tube (MP1) and the grid electrode of the second PMOS tube (MP 2);

the grid electrode of the second NMOS tube (MN2) is connected with a first reference voltage (REF1), and the drain electrode of the second NMOS tube (MN3) is connected with the source electrode of the third NMOS tube;

the grid electrode of the third NMOS tube (MN3) is connected with the pulse width modulation signal (PWM), and the drain electrode of the third NMOS tube (HN4) is connected with the source electrode of the fifth NMOS tube;

the grid electrode of the fifth NMOS tube (HN4) is connected with the output voltage of the low dropout linear regulator, and the drain electrode of the fifth NMOS tube (HN4) is connected with the drain electrodes of the second PMOS tube (MP2), the third PMOS tube (MP3) and the fourth PMOS tube (MP4) and the grid electrode of the fourteenth PMOS tube (HP3) and is connected with the power supply Voltage (VDD) after passing through a seventh Resistor (RST);

the grid electrode of the third PMOS tube (MP3) is connected with the inverted signal of the high-side drive control signal (HDRV _ Ctrl), and the source electrode of the third PMOS tube (MP3) is connected with the source electrodes of the first PMOS tube (MP1), the second PMOS tube (MP2) and the fourth PMOS tube (MP4) and is connected with the power supply Voltage (VDD);

the source electrode of the fourteenth PMOS tube (HP3) is connected with the grid electrode of the fourth PMOS tube (MP4) and the grid electrode of the upper power tube (MP0), and is connected with the power supply Voltage (VDD) after passing through the third resistor (R3), and the drain electrode of the fourteenth PMOS tube is Grounded (GND);

the source electrode of the upper power tube (MP0) is connected with a power supply Voltage (VDD), and the drain electrode of the upper power tube is connected with the source electrode of a thirteenth PMOS tube (HP 2);

the middle-side bias module comprises a fifth PMOS (MP5), a sixth PMOS (MP6), a seventh PMOS (MP7), an eighth PMOS (MP8), a fifteenth PMOS (HP4), a sixth NMOS (HN5), a seventh NMOS (HN6), a fourth resistor (R4), a first capacitor (C1), a second current source (I2) and a third current source (I3),

the grid electrode of a sixth NMOS tube (HN5) is connected with the output voltage of the low dropout linear regulator, the source electrode of the sixth NMOS tube is Grounded (GND) after passing through a second current source (I2), and the drain electrode of the sixth NMOS tube is connected with the grid electrode and the drain electrode of a fifth PMOS tube (MP5) and the grid electrodes of a sixth PMOS tube (MP6) and an eighth PMOS tube (MP 8);

the grid electrode of the seventh PMOS tube (MP7) is connected with the drain electrode of the sixth PMOS tube (MP6), the source electrode of the thirteenth PMOS tube (HP2) and one end of the fourth resistor (R4), the source electrodes of the seventh PMOS tube (MP7) are connected with the sources electrodes of the fifth PMOS tube (MP5), the sixth PMOS tube (MP6) and the eighth PMOS tube (MP8) and are connected with the power supply Voltage (VDD), and the drain electrode of the seventh PMOS tube (HN6) is connected with the grid electrode of the fifteenth PMOS tube (HP4) and the drain electrode of the seventh NMOS tube (HN6) and is connected with the other end of the fourth resistor (R4) through the first capacitor (C1);

the grid electrode of a seventh NMOS tube (HN6) is connected with the output voltage of the low dropout linear regulator, and the source electrode of the seventh NMOS tube is Grounded (GND) after passing through a third current source (I3);

the source electrode of the fifteenth PMOS tube (HP4) is connected with the drain electrode of the eighth PMOS tube (MP8) and the grid electrode of the thirteenth PMOS tube (HP2), and the drain electrode of the fifteenth PMOS tube (HP4) is Grounded (GND);

the active clamping module is used for clamping the gate drive signal (DRV).

2. The current-mode segmented gate driver circuit with active clamp of claim 1, wherein the active clamp module comprises an eighth NMOS transistor (HN7), a ninth PMOS transistor (MP9), a tenth PMOS transistor (MP10), an eleventh PMOS transistor (MP11), a twelfth PMOS transistor (MP12), a fifth resistor (R5), a sixth resistor (R6), a fourth current source (I4) and a Zener transistor (Z),

the grid electrode of the tenth PMOS tube (MP10) is connected with the grid electrode and the drain electrode of the ninth PMOS tube (MP9), and is Grounded (GND) after passing through the fourth current source (I4), the source electrode of the tenth PMOS tube is connected with the source electrode of the ninth PMOS tube (MP9) and is connected with the output voltage of the low dropout regulator, and the drain electrode of the tenth PMOS tube is connected with the grid electrode of the twelfth PMOS tube (MP12) and the source electrode of the eleventh PMOS tube (MP 11);

the gate of the eleventh PMOS transistor (MP11) is connected to the second reference voltage (REF2), and the drain thereof is connected to the source of the eighth NMOS transistor (HN7) and Grounded (GND);

the grid electrode of the eighth NMOS tube (HN7) is connected with the drain electrode of the twelfth PMOS tube (MP12) through a fifth resistor (R5), and is Grounded (GND) through a sixth resistor (R6), and the drain electrode of the eighth NMOS tube (HN7) is connected with the cathode of the Zener tube (Z) and the grid driving signal (DRV);

the anode of the Zener tube (Z) is connected with the source electrode of the twelfth PMOS tube (MP 12).

3. The current-mode segmented gate drive circuit with source clamping of claim 1, further comprising a series arrangement of a first resistor (R1) and a second resistor (R2) connected between the output of the current-mode segmented gate drive circuit and Power Ground (PGND), the series point of which outputs the sampled signal (DRV _ Sense).

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