CN109031880B - OPC correction method for SRAM layout - Google Patents
OPC correction method for SRAM layout Download PDFInfo
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- CN109031880B CN109031880B CN201810768912.1A CN201810768912A CN109031880B CN 109031880 B CN109031880 B CN 109031880B CN 201810768912 A CN201810768912 A CN 201810768912A CN 109031880 B CN109031880 B CN 109031880B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000007704 transition Effects 0.000 claims abstract description 34
- 239000004429 Calibre Substances 0.000 claims abstract description 6
- 239000012528 membrane Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 4
- 230000011218 segmentation Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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Abstract
The invention provides an OPC correction method for an SRAM layout, which comprises the steps of dividing the SRAM layout into a middle area, a transition area and a boundary area, correcting a repeated unit screenshot of the SRAM layout by a Calibre pxOPC tool to obtain a mask plate Pattern of a minimum repeated unit of the SRAM, matching and adding the mask plate Pattern of the minimum repeated unit of the SRAM to the middle area of the SRAM layout by using the Calibre Pattern Match tool, and then performing OPC correction on the transition area and the boundary area of the SRAM layout to obtain a final mask plate layer of the SRAM layout. The method can greatly shorten the OPC operation time and ensure the consistency of the mask plate size of the middle repeat unit area of the SRAM layout.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to an OPC (optical proximity correction) correction method for SRAM (static random access memory) layout with a critical dimension of 22nm or below.
Background
With the development of semiconductor technology, the critical dimension of devices is smaller and smaller, and when the process node reaches 16 nm or 14 nm or below, a method of splitting a layer of layout into multiple layers and performing multiple exposures by a photoetching process is generally adopted to solve the limitation that the wavelength of a light source of a DUV photoetching machine reaches the limit. When the process node is at 20 nm or 22nm, the OPC correction of a layout which does not use multi-layer splitting is difficult, and the line width and the space in the layout are limit values which can be born by a machine, so the OPC difficulty is very great.
The pxOPC product of Calibre software is often used to solve the problems encountered by OPC during the correction process, such as pattern disconnection, bridging, inability to correct the target due to mask rule limitations, etc. The main feature of pxOPC is that the segmentation of the pattern in the reticle layer is set small and that reasonable irregularly shaped sub-development assist patterns are added. Therefore, the pxOPC correction process is extremely complex and takes a long time, and is generally only used for calculating a small screenshot of the layout, and is not suitable for performing complete layout calculation. Therefore, when a structure which is difficult to correct is encountered in the conventional OPC method, correction is usually performed by methods of adjusting segmentation and structure of a mask and optimizing a sub-development auxiliary pattern by taking a result of pxOPC as a reference, but an OPC script needs to be modified greatly to enable a result of a mask shape obtained by correction to be close to a shape obtained by pxOPC operation.
Disclosure of Invention
The invention aims to provide an OPC correction method for an SRAM layout, which is suitable for a process with a key size of 22nm or below, can save operation modification time and improve mask plate generation speed.
In order to solve the technical problem, the invention provides an OPC correction method for an SRAM layout, which comprises the following steps:
1) dividing an SRAM layout into a middle area, a transition area and a boundary area;
a middle region, a region of repeating cell layout in the SRAM layout;
a transition region extending from the boundary of the middle region to the center of the middle region by a preset width;
a boundary region, which is a region in the SRAM layout except the middle region and the transition region;
2) carrying out pxOPC correction on the screenshot of the repeat unit in the SRAM layout to obtain a minimum repeat unit mask plate;
3) correspondingly placing the minimum repeat unit mask plates on each SRAM layout minimum repeat unit in the middle area to form middle mask plates;
4) carrying out OPC correction on the transition area to obtain a transition mask plate;
5) carrying out OPC correction on the boundary area to obtain a boundary mask plate;
6) and splicing the middle mask plate, the transition mask plate and the boundary mask plate to form the SRAM layout membrane plate.
Wherein the preset width is larger than 5-10 minimum repeating unit sizes.
And 2) intercepting a part of the SRAM layout to perform pxOPC correction when the step 2) is implemented, and acquiring a minimum repeat unit mask plate of a minimum repeat unit in the SRAM layout. The intercepted SRAM layout part at least comprises 5 × 5 SRAM layout minimum repeating units.
And 2) intercepting a part of the middle area of the SRAM layout to perform pxOPC correction when the step 2) is implemented, and acquiring a minimum repeat unit mask plate of a minimum repeat unit in the SRAM layout. The intercepted SRAM layout part at least comprises 5 × 5 SRAM layout minimum repeating units.
Wherein, the minimal repeating unit is searched and matched by Calibre Pattern Match software.
If the mask shape obtained by the pxOPC operation is directly used for final publishing, a step of modifying the OPC script greatly can be omitted. In another product of Calibre software, the pattern matching software can perform matching search in the whole layout by selecting a certain specific structure or screenshot shape, and further select all positions consistent with or similar to the specific shape or screenshot to perform pattern replacement or other operations. At present, the pattern matching is widely applied to the aspect of searching process hotspots.
The Static Random Access Memory (SRAM) layout is characterized in that structures at other positions except for a boundary area are arranged in a repeated unit pattern, so that for the layout of the small-size SRAM, a result obtained by the pxOPC operation is directly replaced into the layout of the SRAM by a pattern matching method, so that a better mask plate shape calculated by the pxOPC can be used as an OPC result, the consistency of the OPC result in the SRAM area can be ensured, and meanwhile, a large amount of CPU operation time and labor can be saved. The invention combines two tools of Calibre, namely a pxOPC tool and an image matching tool for use, can solve the circuit layout with smaller critical dimension by methods of carrying out additional OPC correction on the SRAM boundary area and the like, solves the common problem encountered by OPC on the basis of not splitting the layout, and can obtain the mask plate shape with uniform dimension in shorter time by utilizing the characteristic of repeated SRAM area structures. The invention can save operation modification time and improve the mask plate generation speed.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is an overall schematic diagram of SRAM layout.
FIG. 2 is a schematic diagram of a minimum repetition unit of an OPC corrected SRAM layout.
FIG. 3 is a schematic diagram of a pxOPC corrected SRAM layout minimal repeat unit.
FIG. 4 is a schematic diagram of an SRAM layout near a boundary, which contains minimal repeating cells as well as non-minimal repeating cells.
Fig. 5 is a schematic diagram of the relationship between the middle region, the transition region and the boundary region.
FIG. 6 is a schematic flow diagram of the present invention.
Description of the reference numerals
1 is a boundary region
2 is the transition region
3 is the middle region
4 is a predetermined width
Detailed Description
The SRAM layout OPC provided by the invention mainly solves the problems of long operation modification time, low mask plate generation speed and low production efficiency caused by the problems of open circuit, bridging, large size change of a mask plate silicon wafer and the like in the OPC modification process of the SRAM layout with the key size of 22nm or less.
The pxOPC method is used for calculating the smaller area screenshot in the SRAM layout, and the pxOPC calculation is characterized in that a mask plate layer is shorter in segmentation, an added sub-development auxiliary graph is irregular in shape, the calculation time is longer, and the calculation of the whole layout is not suitable. The above characteristics between pxOPC are generally only used as guidance for OPC correction and SRAF pattern addition, and it is difficult to correct a result completely consistent with the pxOPC result by a normal OPC method.
The graph matching software developed by Calibre Pattern Match, namely Calibre, is widely used in the aspect of finding process hotspots in OPC correction, and can accurately find graphs which are consistent with target graphs or contain certain rules in a layout. After the target graph is found, the found graph can be replaced by a Standard Validation Rule Format (SVRF) statement.
The patterns of the layout of the SRAM area are generally regularly arranged in an array of a certain repeated unit structure, so that the smallest repeated unit in the layout can be used as a target pattern by a pattern matching method, the target pattern is searched in the whole layout, and the mask pattern of the smallest repeated unit obtained by the operation of pxOPC is replaced. The boundaries of the SRAM area may have a different structure than the minimum repeat unit, which requires OPC to correct these locations individually, but the shape of the surrounding pattern may also affect the shape of the mask layer of the minimum repeat unit in the SRAM area. Therefore, the OPC correction needs to be performed again by selecting a range close to the boundary and a certain distance in the SRAM layout, but the shape of the mask layer image of the minimum repeated unit exceeding the area does not need to be performed again with the OPC correction.
As shown in fig. 5, the first embodiment of the OPC correcting method for SRAM layout according to the present invention includes the following steps:
1) dividing an SRAM layout into a middle area, a transition area and a boundary area;
a middle region, a region of repeating cell layout in the SRAM layout;
the transition region extends from the boundary of the middle region to the center direction of the middle region by a preset width, wherein the preset width is larger than the region with the size of 5-10 minimum repeating units;
that is, the predetermined width is greater than 5, 6, 7, 8, 9, or 10 minimum repeat unit sizes. This embodiment extends a distance of 5 minimum repeat unit dimensions.
A boundary region, which is a region in the SRAM layout except the middle region and the transition region;
2) carrying out pxOPC correction on the screenshot of the repeat unit in the SRAM layout to obtain a minimum repeat unit mask plate;
3) correspondingly placing the minimum repeat unit mask plates on each SRAM layout minimum repeat unit in the middle area to form middle mask plates;
4) carrying out OPC correction on the transition area to obtain a transition mask plate;
5) carrying out OPC correction on the boundary area to obtain a boundary mask plate;
6) and splicing the middle mask plate, the transition mask plate and the boundary mask plate to form the SRAM layout membrane plate.
The invention provides a second embodiment of an OPC correction method for an SRAM layout, which comprises the following steps:
1) dividing an SRAM layout into a middle area, a transition area and a boundary area;
the middle area is an area of minimum repeated unit layout in the SRAM layout;
the transition region extends from the boundary of the middle region to the center direction of the middle region by a preset width, wherein the preset width is larger than the region with the size of 5-10 minimum repeating units;
that is, the predetermined width is greater than 5, 6, 7, 8, 9, or 10 minimum repeat unit sizes. This embodiment extends a distance of 10 minimum repeat unit dimensions.
A boundary region, which is a region in the SRAM layout except the middle region and the transition region;
2) and intercepting a part of screenshots containing the repeating units in the SRAM layout to perform pxOPC correction, and obtaining a mask plate of the minimum repeating unit in the SRAM layout. The intercepted SRAM layout part at least comprises 5 × 5 SRAM layout minimum repeating units.
In the second embodiment, a part of the layout of the SRAM layout including the plurality of repeating units is intercepted, which is helpful to reduce the operation time and improve the working efficiency.
3) Correspondingly placing the minimum repeat unit mask plates on each SRAM layout minimum repeat unit in the middle area to form middle mask plates;
4) carrying out OPC correction on the transition area to obtain a transition mask plate;
5) carrying out OPC correction on the boundary area to obtain a boundary mask plate;
6) and splicing the middle mask plate, the transition mask plate and the boundary mask plate to form the SRAM layout membrane plate.
The invention provides a third embodiment of an OPC correction method for an SRAM layout, which comprises the following steps:
1) dividing an SRAM layout into a middle area, a transition area and a boundary area;
the middle area is an area of minimum repeated unit layout in the SRAM layout;
the transition region extends from the boundary of the middle region to the center direction of the middle region by a preset width, wherein the preset width is larger than the region with the size of 5-10 minimum repeating units;
that is, the predetermined width is greater than 5, 6, 7, 8, 9, or 10 minimum repeat unit sizes. This embodiment extends a distance of 15 minimum repeat unit dimensions.
A boundary region, which is a region in the SRAM layout except the middle region and the transition region;
2) and intercepting a part of screenshots in the middle area of the SRAM layout to perform pxOPC correction, and obtaining a mask plate of the minimum repeat unit in the SRAM layout. The intercepted SRAM layout part at least comprises 5 × 5 SRAM layout minimum repeating units.
The middle area of the SRAM layout necessarily contains the minimum repeating unit, and the interception of the middle area of the SRAM layout is beneficial to reducing the operation time and improving the working efficiency.
3) Correspondingly placing the minimum repeat unit mask plates on each SRAM layout minimum repeat unit in the middle area to form middle mask plates;
4) carrying out OPC correction on the transition area to obtain a transition mask plate;
5) carrying out OPC correction on the boundary area to obtain a boundary mask plate;
6) and splicing the middle mask plate, the transition mask plate and the boundary mask plate to form the SRAM layout membrane plate.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (4)
1. An OPC correction method of SRAM layout is used for OPC correction of SRAM layout with critical dimension of 22nm and below, and is characterized by comprising the following steps:
1) dividing an SRAM layout into a middle area, a transition area and a boundary area;
a middle region, a region of repeating cell layout in the SRAM layout;
a transition region extending from the boundary of the middle region to the center of the middle region by a preset width;
a boundary region, which is a region in the SRAM layout except the middle region and the transition region;
2) carrying out pxOPC correction on the repeated unit screenshot in the SRAM layout, intercepting the SRAM layout part at least comprising 5 × 5 minimum repeated units of the SRAM layout, and obtaining a minimum repeated unit mask plate;
3) correspondingly placing the minimum repeat unit mask plates on each SRAM layout minimum repeat unit in the middle area to form middle mask plates;
4) carrying out OPC correction on the transition area to obtain a transition mask plate;
5) carrying out OPC correction on the boundary area to obtain a boundary mask plate;
6) splicing the middle mask plate, the transition mask plate and the boundary mask plate to form an SRAM layout membrane plate;
wherein the predetermined width is greater than 5 minimum repeat unit sizes.
2. The OPC correction method for an SRAM layout of claim 1, wherein: and 2) intercepting a part of the SRAM layout to perform pxOPC correction when the step 2) is implemented, and acquiring a minimum repeat unit mask plate of a minimum repeat unit in the SRAM layout.
3. The OPC correction method for an SRAM layout of claim 1, wherein: and 2) when the step 2) is implemented, intercepting a part of the middle area of the SRAM layout to perform pxOPC correction, and acquiring a minimum repeat unit mask plate of a minimum repeat unit in the SRAM layout.
4. The method for OPC correction of an SRAM layout of claim 2, characterized in that: the minimal repeating unit search and matching is performed by Calibre Pattern Match software.
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| CN114077159B (en) | 2020-08-21 | 2025-07-25 | 长鑫存储技术有限公司 | Layout correction method |
| CN112506003B (en) * | 2020-11-20 | 2025-09-23 | 深圳晶源信息技术有限公司 | Mask optimization method, mask optimization system and electronic equipment |
| CN115346861A (en) | 2021-05-14 | 2022-11-15 | 联华电子股份有限公司 | Method for correcting semiconductor mask pattern and semiconductor structure thereof |
| CN115293094A (en) * | 2022-08-11 | 2022-11-04 | 华虹半导体(无锡)有限公司 | Special unit general database and its establishment method, graphic correction method |
| CN115220297A (en) * | 2022-08-18 | 2022-10-21 | 上海积塔半导体有限公司 | OPC (optical proximity correction) pattern correction method and system and mask plate |
| CN115453815A (en) * | 2022-08-30 | 2022-12-09 | 上海华力集成电路制造有限公司 | Method for correcting optical proximity effect |
| CN116256939A (en) * | 2022-12-29 | 2023-06-13 | 上海集成电路装备材料产业创新中心有限公司 | Optical proximity correction method, device, equipment and computer readable storage medium |
| CN119200318A (en) * | 2024-09-26 | 2024-12-27 | 上海华虹宏力半导体制造有限公司 | Method for extracting minimum repeating unit, OPC verification method and device |
| CN119717387A (en) * | 2025-02-26 | 2025-03-28 | 中国科学院光电技术研究所 | Mask layout and boundary optimization method for super-resolution lithography |
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| JP2003142584A (en) * | 2001-11-05 | 2003-05-16 | Matsushita Electric Ind Co Ltd | Design method of semiconductor integrated circuit device |
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| CN102445835A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Optical proximity correction modeling method of SRAM source and drain dimension |
| CN105892223A (en) * | 2016-06-14 | 2016-08-24 | 上海华力微电子有限公司 | Method for optimizing optical proximity effect (OPC) verification |
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