CN108962817B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, a gate structure on the substrate, a first interlayer dielectric layer on the substrate exposed by the gate structure, and the first interlayer dielectric layer exposing the top of the gate structure; removing The first interlayer dielectric layer; after removing the first interlayer dielectric layer, a second interlayer dielectric layer is formed on the exposed substrate of the gate structure, the second interlayer dielectric layer exposes the top of the gate structure, and the second interlayer dielectric layer The relative dielectric constant of the first interlayer dielectric layer is smaller than that of the first interlayer dielectric layer; contact hole plugs are formed in the second interlayer dielectric layer, and the contact hole plugs are electrically connected to the substrate. In the present invention, the RC delay can be reduced by adopting the scheme of replacing the first interlayer dielectric layer with a second interlayer dielectric layer with a relatively small relative permittivity, thereby improving the performance of the semiconductor device.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

In a semiconductor device, reducing the RC delay (Resistance capacitance delay) can improve the performance of the semiconductor device. With the development of semiconductor technology and the advancement of technology nodes, the functions of devices are becoming stronger and stronger, the integration of devices is getting higher and higher, and the characteristic size (Critical Dimension, CD) of devices is also getting smaller and smaller. Correspondingly, the RC is further reduced. Delay has become one of the important measures to improve the performance of semiconductor devices.

The interconnect structure of the semiconductor device includes contact hole plugs. At present, in order to reduce the RC delay, the material used for the contact hole plug is usually a material with low resistance, such as cobalt or tungsten, so as to improve the performance of the semiconductor device.

However, even if the contact hole plug is made of a material with a lower resistance value, the performance of the semiconductor device still needs to be improved.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to optimize the electrical performance of the semiconductor device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate with a gate structure on the substrate, a first interlayer dielectric layer on the substrate exposed by the gate structure, and the first interlayer dielectric layer on the substrate. The top of the gate structure is exposed by the interlayer dielectric layer; the first interlayer dielectric layer is removed; after the first interlayer dielectric layer is removed, a second interlayer dielectric is formed on the exposed substrate of the gate structure layer, the second interlayer dielectric layer exposes the top of the gate structure, and the relative dielectric constant of the second interlayer dielectric layer is smaller than the relative dielectric constant of the first interlayer dielectric layer; A contact hole plug is formed in the interlayer dielectric layer, and the contact hole plug is electrically connected to the substrate.

Optionally, the material of the first interlayer dielectric layer is SiO ₂ .

Optionally, the material of the second interlayer dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material.

Optionally, the material of the second interlayer dielectric layer is SiOC or SiOCH.

Optionally, after removing the first interlayer dielectric layer, and before forming a second interlayer dielectric layer on the substrate exposed by the gate structure, the forming method further includes: on the substrate exposed by the gate structure forming a first sacrificial layer on the top of the gate structure; forming a mask layer on part of the first sacrificial layer on both sides of the gate structure; using the mask layer as a mask , etching the first sacrificial layer to expose part of the substrate; the step of forming the second interlayer dielectric layer includes: after etching the first sacrificial layer, forming a second layer on the exposed substrate an interlayer dielectric layer; after forming the second interlayer dielectric layer, the forming method further includes: removing the remaining first sacrificial layer, and forming a contact opening in the second interlayer dielectric layer exposing the substrate; The step of forming a contact hole plug in the second interlayer dielectric layer includes: filling the contact opening with a conductive material to form a contact hole plug.

Optionally, the material of the first sacrificial layer is polysilicon.

Optionally, the material of the mask layer is SiO ₂ , SiN or TiN.

至

Optionally, the thickness of the mask layer is

to

Optionally, the step of forming a second interlayer dielectric layer on the exposed substrate includes: forming an interlayer dielectric film on the exposed substrate, the interlayer dielectric film covering the top of the gate structure; A second sacrificial layer is formed on the interlayer dielectric film; a planarization process is used to remove the second sacrificial layer and the interlayer dielectric film above the top of the gate structure, and the interlayer dielectric film remains as the second interlayer dielectric layer.

至

Optionally, in the step of forming an interlayer dielectric film on the exposed substrate, the thickness of the interlayer dielectric film is

to

Optionally, the second sacrificial layer is a tetraethyl orthosilicate layer or a plasma enhanced oxide layer.

至

Optionally, the thickness of the second sacrificial layer is

to

Optionally, the material of the contact hole plug is Co or W.

Optionally, in the step of providing a substrate, the gate structure has a gate protection layer on top; in the step of forming a second interlayer dielectric layer on the exposed substrate, the second interlayer dielectric layer is exposed on the exposed substrate. on top of the gate protection layer.

Optionally, the material of the gate protection layer is silicon nitride. Correspondingly, the present invention further provides a semiconductor structure, comprising: a substrate; a gate structure on the substrate; an interlayer dielectric layer on the substrate exposed by the gate structure, and the interlayer dielectric layer exposes the On the top of the gate structure, the material of the interlayer dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material; contact hole plugs are located in the interlayer dielectric layer on both sides of the gate structure and electrically connected to the substrate; connect.

Optionally, the material of the interlayer dielectric layer is SiOC or SiOCH.

Optionally, the material of the contact hole plug is Co or W.

Optionally, the semiconductor structure further includes: a gate protection layer located on top of the gate structure; the interlayer dielectric layer exposes the top of the gate protection layer.

Optionally, the material of the gate protection layer is silicon nitride. Compared with the prior art, the technical solution of the present invention has the following advantages:

In the present invention, after the first interlayer dielectric layer is removed, a second interlayer dielectric layer is formed on the exposed substrate of the gate structure, the second interlayer dielectric layer exposes the top of the gate structure, and the second interlayer dielectric layer is exposed to the top of the gate structure. The relative dielectric constant (k value) of the dielectric layer is smaller than the relative dielectric constant of the first interlayer dielectric layer; the first interlayer dielectric layer is replaced by a second interlayer dielectric layer with a smaller relative dielectric constant , so that the RC delay can be reduced, thereby improving the performance of the semiconductor device.

In an optional solution, after removing the first interlayer dielectric layer, before forming a second interlayer dielectric layer on the substrate exposed by the gate structure, the forming method further comprises: exposing the gate structure A first sacrificial layer is formed on the substrate, and the first sacrificial layer exposes the top of the gate structure; the first sacrificial layer occupies the position of the second interlayer dielectric layer and the contact hole plug at the same time. After the second interlayer dielectric layer, the remaining first sacrificial layer is removed, and a contact opening exposing the substrate is formed in the second interlayer dielectric layer, thus eliminating the need for photolithography for forming the contact opening and etching process, which simplifies the process steps and helps to reduce the difficulty of the process.

In an optional solution, the material of the second interlayer dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material. Compared with commonly used interlayer dielectric layer materials (such as SiO ₂ ), the second interlayer dielectric layer is The dielectric constant is smaller, so that the effect of reducing the RC delay can be improved.

The present invention provides a semiconductor structure. The material of the interlayer dielectric layer of the semiconductor structure is a low-k dielectric material or an ultra-low-k dielectric material. Compared with the commonly used interlayer dielectric material (eg SiO ₂ ), the The dielectric constant of the interlayer dielectric layer is small, so that the RC delay can be effectively reduced, thereby improving the performance of the semiconductor device.

Description of drawings

1 to 11 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

FIG. 12 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

Detailed ways

It can be known from the background art that even if the contact hole plug is made of a material with a smaller resistance value, the performance of the semiconductor device still needs to be improved.

In order to solve the technical problem, the present invention can reduce the RC delay by using a second interlayer dielectric layer with a relatively small relative permittivity, thereby improving the performance of the semiconductor device.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

1 to 11 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to FIG. 1, a substrate (not shown) is provided, the substrate has a gate structure 100 thereon, a first interlayer dielectric layer 300 is formed on the substrate exposed by the gate structure 100, and the first interlayer dielectric layer 300 The top of the gate structure 100 is exposed.

The substrate provides a process platform for the formation of subsequent semiconductor structures,

In this embodiment, the substrate is used to form a fin-type field effect transistor, so in the step of providing the substrate, the substrate includes a substrate (not shown in the figure) and discrete fins (not shown in the figure) located on the substrate Show). Accordingly, the gate structure 200 spans the fin and covers part of the sidewall and top surface of the fin.

In other embodiments, the substrate may also be used to form a planar transistor, and the substrate is correspondingly a planar substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or germanium-on-insulator substrate.

The material of the fins is the same as the material of the substrate. In this embodiment, the material of the fins is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

In this embodiment, the gate structure 100 is a metal gate. Specifically, the gate structure 100 includes a work function layer 110 and a metal layer 120 located on the work function layer 110; a high-k gate dielectric layer (not shown in the figure) may also be formed between the work function layer 110 and the substrate. Show).

It should be noted that the step of providing the substrate further includes: forming sidewall spacers 200 on the sidewalls of the gate structure 100 ; Source and drain doped regions (not shown) are formed.

The material of the sidewall 200 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 200 can be a single material. Layer structure or stack structure. In this embodiment, the spacer 200 is a stacked structure, and the spacer 200 includes a silicon oxide layer 210 on the sidewall of the gate structure 100 and a nitrogen layer on the sidewall of the silicon oxide layer 210 Silicide layer 220 .

The source and drain doped regions are used as a source region (Source) or a drain region (Drain) of the semiconductor device. Specifically, the source and drain doped regions are formed in the fins on both sides of the gate structure 100 .

It should also be noted that an etch stop layer (CESL) 250 is also formed on the surface of the substrate and the sidewall of the sidewall 200. During the subsequent etching process for forming the contact hole plug, the top of the etch stop layer 250 is formed. It is used to define the stop position of the etching process, so as to avoid the problem of under-etching or over-etching in each area. In this embodiment, the material of the etch stop layer 250 is silicon nitride.

The first interlayer dielectric layer 300 is used to define the formation position and size of the gate structure 200 . Specifically, the first interlayer dielectric layer 300 is formed on the exposed substrate of the gate structure 100 .

The material of the first interlayer dielectric layer 300 is an insulating dielectric material. In this embodiment, the material of the first interlayer dielectric layer 300 is SiO ₂ (silicon oxide). In other embodiments, the material of the first interlayer dielectric layer may also be SiN (silicon nitride), SiON (silicon oxynitride) or SiCON (silicon oxycarbonitride).

In this embodiment, the top of the first interlayer dielectric layer 300 is flush with the top of the sidewall 200 .

In addition, in this embodiment, a gate protection layer 150 is provided on the top of the gate structure 100 .

The gate protection layer 150 is used to protect the top of the gate structure 100 in subsequent processes. In this embodiment, the material of the gate protection layer 150 is silicon nitride.

Specifically, the step of forming the gate protection layer 150 includes: etching and removing a part of the thickness of the gate structure 100 , forming a groove in the sidewall spacer 200 ; filling the groove with a gate protection material , the gate protection material also covers the top of the first interlayer dielectric layer 300; a planarization process is used to remove the gate protection material higher than the top of the first interlayer dielectric layer 300, and the groove The rest of the gate protection material is used as the gate protection layer 150 .

In this embodiment, the top of the gate protection layer 150 is flush with the top of the spacer 200 . In other embodiments, the top of the gate protection layer may also be lower than the top of the spacer.

Referring to FIG. 2 , the first interlayer dielectric layer 300 (as shown in FIG. 1 ) is removed.

By removing the first interlayer dielectric layer 300 , a space is provided for the subsequent formation of a second interlayer dielectric layer with a relative permittivity (k value) smaller than the first interlayer dielectric layer 300 .

In this embodiment, the first interlayer dielectric layer 300 is removed by a wet etching process. The SiO ₂ of the first interlayer dielectric layer 300, correspondingly, the etching solution used in the wet etching process is a hydrofluoric acid solution. In other embodiments, the process of removing the first interlayer dielectric layer may also be a dry etching process.

The gate protection layer 150 is formed on the top of the gate structure 100 , so in the process of removing the first interlayer dielectric layer 300 , the gate protection layer 150 can lift the top of the gate structure 100 . to protection.

Referring to FIGS. 3 to 9 , after removing the first interlayer dielectric layer 300 (as shown in FIG. 1 ), a second interlayer dielectric layer is formed on the exposed substrate (not shown) of the gate structure 100 500 (as shown in FIG. 9 ), the second interlayer dielectric layer 500 exposes the top of the gate structure 100 , and the relative permittivity of the second interlayer dielectric layer 500 is smaller than that of the first interlayer dielectric layer 300 relative permittivity.

By replacing the first interlayer dielectric layer 300 with the second interlayer dielectric layer 500 having a relatively small relative permittivity, the RC delay can be reduced, thereby improving the performance of the semiconductor device.

The steps of forming the second interlayer dielectric layer 500 will be described in detail below with reference to the accompanying drawings.

Referring to FIGS. 3 and 4 , a first sacrificial layer 400 (as shown in FIG. 4 ) is formed on the exposed substrate of the gate structure 100 , and the first sacrificial layer 400 exposes the top of the gate structure 100 .

The first sacrificial layer 400 occupies a space for the second interlayer dielectric layer formed subsequently, and the first sacrificial layer 400 may also occupy a space for the contact hole plugs formed later.

In this embodiment, the material of the first sacrificial layer 400 is polysilicon. The polysilicon material can better play the role of a stop layer in the subsequent planarization process or etching process, and the polysilicon material has good process compatibility, which can avoid the introduction of the first sacrificial layer 400 to the semiconductor formed subsequently. The performance of the structure is adversely affected; in addition, by using polysilicon as the material of the first sacrificial layer 400 , it is beneficial to reduce the difficulty of the subsequent removal of the first sacrificial layer 400 .

Specifically, the step of forming the first sacrificial layer 400 includes: forming a sacrificial material layer 450 on the exposed substrate of the gate structure 100 (as shown in FIG. 3 ), and the sacrificial material layer 450 covers the gate the top of the protective layer 150 ; the sacrificial material layer 450 is planarized; after the planarization, the remaining sacrificial material layer 450 is etched back to form the first sacrificial layer 400 .

By performing a planarization process on the sacrificial material layer 450 to remove a part of the thickness of the sacrificial material layer 450, a process basis is provided for the subsequent engraving of the remaining sacrificial material layer 450, and the process difficulty of the engraving process is reduced; Through the etch-back process, loading effects caused by dense (Dense) regions and sparse (Iso) regions are avoided. That is to say, the surface flatness of the first sacrificial layer 400 and the thickness uniformity of the first sacrificial layer 400 are improved by the combination of the planarization treatment and the etch-back process.

In this embodiment, the top of the first sacrificial layer 400 is flush with the top of the gate protection layer 150 .

至

为了使所述第一牺牲层400顶部与所述栅极保护层150顶部齐平的同时，降低工艺难度，在所述平坦化处理后，剩余所述牺牲材料层450顶部至所述栅极保护层150顶部的距离为

至

In this embodiment, in the step of forming the sacrificial material layer 450, the thickness of the sacrificial material layer 450 is

to

In order to make the top of the first sacrificial layer 400 flush with the top of the gate protection layer 150 and reduce the difficulty of the process, after the planarization process, the top of the sacrificial material layer 450 remains to the gate protection The distance from the top of layer 150 is

to

Referring to FIG. 5 , a mask layer 450 is formed on a portion of the first sacrificial layer 400 on both sides of the gate structure 100 .

The mask layer 450 is used as an etching mask for the subsequent etching of the first sacrificial layer 400 , and is also used for the first sacrificial layer 400 under the mask layer 450 during the etching process. The top of the sacrificial layer 400 plays a protective role.

The material of the mask layer 450 may be SiO ₂ , SiN or TiN. In this embodiment, the material of the mask layer 450 is SiO ₂ .

The mask layer 450 and the second interlayer dielectric layer formed subsequently are both oxide materials. When the mask layer 450 is retained after the first sacrificial layer 400 is etched, the second interlayer dielectric layer formation is not affected.

至

It should be noted that the thickness of the mask layer 450 should not be too small or too large. If the thickness of the mask layer 450 is too small, in the subsequent process of etching the first sacrificial layer 400, the protective effect of the mask layer 450 on the top of the first sacrificial layer 400 is not obvious. The etching process is likely to cause surface damage to the first sacrificial layer 400 under the mask layer 450; if the thickness of the mask layer 450 is too large, it will cause waste of materials, and the mask layer 450 will be wasted when the mask layer 450 is removed. When the film layer 450 is formed, the difficulty of the removal process is increased. Therefore, in this embodiment, the thickness of the mask layer 450 is

to

Specifically, the step of forming the mask layer 450 includes: forming a mask material layer on the first sacrificial layer 400 , and the mask material layer also covers the top of the etch stop layer 250 and the top of the sidewall spacer 200 and the top of the gate protection layer 150; a photoresist layer (not shown) is formed on part of the mask material layer on both sides of the gate structure 100; using the photoresist layer as a mask, etching For the mask material layer, the mask material layer on the part of the first sacrificial layer 400 on both sides of the gate structure 100 is reserved as the mask layer 450 .

In this embodiment, after the mask layer 450 is formed, the photoresist layer is retained, and the photoresist layer serves as an etching mask in the subsequent process of etching the first sacrificial layer 400 .

Referring to FIG. 6 , using the mask layer 450 as a mask, the first sacrificial layer 400 is etched to expose part of the substrate.

The exposed substrate provides space for the subsequent formation of the second interlayer dielectric layer, and the remaining first sacrificial layer 400 occupies space for the contact hole plugs to be formed subsequently.

Specifically, using the photoresist layer and the mask layer 450 as masks, the first sacrificial layer 400 is etched.

In this embodiment, in order to retain the first sacrificial layer 400 under the mask layer 450, the process used for etching the first sacrificial layer 400 is a dry etching process, which is beneficial to improve the remaining The topography of the first sacrificial layer 400 .

It should be noted that, under the protection of the mask layer 450, surface damage to the first sacrificial layer 400 under the mask layer 450 caused by the etching process can be avoided, which is beneficial to improve the subsequent contact hole insertion The quality of plug formation.

In this embodiment, after the first sacrificial layer 400 is etched, the photoresist layer is removed by an ashing process or a wet stripping method.

Referring to FIG. 7 , in this embodiment, after removing the photoresist layer, the forming method further includes: removing the mask layer 450 (as shown in FIG. 6 ).

In other embodiments, the mask layer may also be retained, and the mask layer may be removed in a subsequent process of forming the second interlayer dielectric layer.

Referring to FIG. 8 and FIG. 9 , after etching the first sacrificial layer 400 , a second interlayer dielectric layer 500 (as shown in FIG. 9 ) is formed on the exposed substrate (not shown).

The relative permittivity of the second interlayer dielectric layer 500 is smaller than the relative permittivity of the first interlayer dielectric layer 300 (as shown in FIG. 1 ).

Specifically, the material of the second interlayer dielectric layer 500 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material). The k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), so that the effect of reducing the RC delay can be improved.

In this embodiment, the material of the second interlayer dielectric layer 500 is SiOC. In other embodiments, the material of the second interlayer dielectric layer may also be SiOCH.

Specifically, the step of forming the second interlayer dielectric layer 500 includes: forming an interlayer dielectric film 510 (as shown in FIG. 8 ) on the exposed substrate, and the interlayer dielectric film 510 covers the gate electrode the top of the structure 100; a second sacrificial layer 520 is formed on the interlayer dielectric film 510; a planarization process is used to remove the second sacrificial layer 520 and the interlayer dielectric film 510 higher than the top of the gate structure 100, and the remaining The interlayer dielectric film 510 serves as the second interlayer dielectric layer 500 .

In this embodiment, a gate protection layer 150 is formed on the top of the gate structure 100 , and correspondingly, the interlayer dielectric film 510 covers the top of the gate protection layer 150 ; in the step of the planarization process, The second sacrificial layer 520 and the interlayer dielectric film 510 above the top of the gate protection layer 150 are removed, and the formed second interlayer dielectric layer 500 exposes the top of the gate protection layer 150 .

In this embodiment, the planarization process is a chemical mechanical polishing process. After the chemical mechanical polishing process, the top of the second interlayer dielectric layer 500 is flush with the top of the gate protection layer 150 .

It should be noted that the material of the second interlayer dielectric layer 500 may be a low-k dielectric material or an ultra-low-k dielectric material, and the grinding process of the second interlayer dielectric layer 500 is relatively difficult. It is easy to form organic residues. Therefore, through the second sacrificial layer 520, the second interlayer dielectric layer 500 is exposed to the top of the gate protection layer 150 while avoiding the occurrence of excessive thickness of the interlayer dielectric film 510. Therefore, the organic residue can be reduced and the difficulty of the grinding process can be reduced.

In this embodiment, the second sacrificial layer 520 is a tetraethylorthosilicate (TetraethylOrthosilicate, TEOS) layer or a plasma enhanced oxide layer (Plasma Enhance Oxide, PEOX).

至

The thickness of the interlayer dielectric film 510 should neither be too small nor too large. If the thickness of the interlayer dielectric film 510 is too small, the problem that the thickness of the formed second interlayer dielectric layer 500 is too small is likely to occur, so the interlayer dielectric film 510 at least covers the top of the gate protection layer 150; if If the thickness of the interlayer dielectric film 510 is too large, it is easy to increase the difficulty of the grinding process and organic residues. Therefore, in this embodiment, in the step of forming the interlayer dielectric film 510 on the exposed substrate, the thickness of the interlayer dielectric film 510 is

to

至

The thickness of the second sacrificial layer 520 should neither be too small nor too large. If the thickness of the second sacrificial layer 520 is too small, the formation quality of the second interlayer dielectric layer 500 is easily reduced; if the thickness of the second sacrificial layer 520 is too large, the process time will be increased accordingly, and the grinding efficiency will be reduced . Therefore, in this embodiment, the thickness of the second sacrificial layer 520 is

to

Referring to FIG. 10 , it can be seen from the foregoing analysis that the remaining first sacrificial layers 400 (as shown in FIG. 9 ) on both sides of the gate structure 100 occupy space for subsequent contact hole plugs, thus forming the second After the interlayer dielectric layer 500 is formed, the forming method further includes: removing the remaining first sacrificial layer 400 , and forming a contact opening 515 in the second interlayer dielectric layer 500 exposing the substrate (not shown).

The contact opening 515 provides a space for the formation of subsequent contact hole plugs.

Specifically, taking the top of the etching stop layer 250 as the stop position, the remaining first sacrificial layer 400 is removed by etching; after the etching stop layer 250 is exposed, the etching stop layer 250 is etched to expose all the The substrate is formed, and a contact opening 515 is formed through the second interlayer dielectric layer 500 and the etch stop layer 250 .

In this embodiment, the contact opening 515 exposes the source and drain doped regions (not shown).

In this embodiment, a dry etching process is used to etch the remaining first sacrificial layer 400 and the etching stop layer 250 , so that the contact opening 515 has a good shape.

Referring to FIG. 11 , a contact hole plug 550 is formed in the second interlayer dielectric layer 500 , and the contact hole plug 550 is electrically connected to the substrate.

The contact hole plug 550 is electrically connected to the source-drain doped region (not shown in the figure), and the contact hole plug 550 is used to realize the electrical connection within the semiconductor device, and is also used to realize the device and the device. electrical connection.

Specifically, the step of forming the contact hole plug 550 in the second interlayer dielectric layer 500 includes: filling the contact opening 515 (as shown in FIG. 10 ) with a conductive material, and the conductive material also covers the The top of the second interlayer dielectric layer 500 ; a planarization process is used to remove the conductive material above the top of the gate protection layer 150 , and the remaining conductive material in the contact opening 515 is used as the contact hole plug 550 .

In this embodiment, the material of the contact hole plug 550 is Co, and the contact hole plug 550 may be formed by a chemical vapor deposition process, a sputtering process or an electroplating process. In other embodiments, the material of the contact hole plug may also be W.

The resistance value of the material of the contact hole plug 550 is small, which is beneficial to reduce the RC delay.

It should be noted that, before filling the contact opening 515 with the conductive material, the forming method further includes: forming a titanium layer (not shown) on the sidewall and bottom of the contact opening 515; and forming a titanium layer on the surface of the titanium layer A titanium nitride layer (not shown) is formed.

The titanium layer not only has good adhesion to the substrate at the bottom of the contact opening 515 and the second interlayer dielectric layer 500 contacting the sidewall of the opening 515, so as to help improve the formation quality of the titanium nitride layer, and can be annealed. The process reacts with silicon in the base material at the location of the source and drain doped regions to form a titanium silicide layer to reduce the contact resistance of the contact hole plug 550 .

The role of the titanium nitride layer is that: on the one hand, the titanium nitride layer can prevent the reactants used in forming the contact hole plug 550 in the contact opening 515 and the source and drain doped regions The reaction of the base material at the position can also prevent the reactant used from reacting with the formed titanium silicide layer; on the other hand, the titanium nitride layer is used when filling the contact opening 515 with conductive material , to improve the adhesion of the conductive material in the contact opening 515 , and the titanium nitride layer can function as a contact hole liner layer.

In this embodiment, by replacing the first interlayer dielectric layer 300 with a second interlayer dielectric layer 500 with a relatively small relative permittivity (as shown in FIG. 1 ), the RC delay can be reduced, thereby improving the semiconductor device. performance.

In addition, the first sacrificial layer 400 (as shown in FIG. 4 ) occupies the positions of the second interlayer dielectric layer 500 and the contact hole plug 550 at the same time. After the second interlayer dielectric layer 500 is formed, By removing the remaining first sacrificial layer 400 , a contact opening 515 (as shown in FIG. 10 ) exposing the substrate is formed in the second interlayer dielectric layer 500 , thus eliminating the need to form the contact opening 515 The photolithography and etching process simplifies the process steps and helps to reduce the difficulty of the process.

Referring to FIG. 12 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown. Correspondingly, the present invention also provides a semiconductor structure. The semiconductor structure includes:

A substrate (not shown); a gate structure 600 is located on the substrate; an interlayer dielectric layer 800 is located on the substrate exposed by the gate structure 600 , and the interlayer dielectric layer 800 exposes the gate structure At the top of 600, the material of the interlayer dielectric layer 800 is a low-k dielectric material or an ultra-low-k dielectric material; The substrate is electrically connected.

In this embodiment, the semiconductor structure is a fin field effect transistor, so the base includes a substrate (not shown) and discrete fins (not shown) on the substrate. Accordingly, the gate structure 600 spans the fin and covers part of the sidewall and top surface of the fin.

In other embodiments, the semiconductor structure may also be a planar transistor, and the substrate is correspondingly a planar substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or germanium-on-insulator substrate.

The material of the fins is the same as the material of the substrate. In this embodiment, the material of the fins is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

In this embodiment, the gate structure 600 is a metal gate. Specifically, the gate structure 600 includes a work function layer 610 and a metal layer 620 located on the work function layer 610; a high-k gate dielectric layer (not shown in the figure) may also be formed between the work function layer 610 and the substrate. Show).

It should be noted that the semiconductor structure further includes: sidewalls 700 located on the sidewalls of the gate structure 600 ; source and drain doped regions (not shown) located on the substrates on both sides of the gate structure 600 Inside; an etch stop layer (CESL) 750 located on part of the substrate surface and the sidewalls of the sidewall spacers 200 .

The material of the spacer 700 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 700 can be a single material. Layer structure or stack structure. In this embodiment, the spacer 700 is a stacked structure, and the spacer 700 includes a silicon oxide layer 710 on the sidewall of the gate structure 600 and a nitrogen layer on the sidewall of the silicon oxide layer 710 Silicon layer 720 .

The source and drain doped regions are used as a source region (Source) or a drain region (Drain) of the semiconductor device. Specifically, the source and drain doped regions are located in the fins on both sides of the gate structure 600 .

During the formation process of the contact hole plug 850, the top of the etching stop layer 750 is used to define the stop position of the etching process, so as to avoid the problem of under-etching or over-etching in each region. In this embodiment, the material of the etch stop layer 750 is silicon nitride.

It should also be noted that the semiconductor structure further includes: a gate protection layer 650 located on the top of the gate structure 600 .

The gate protection layer 650 is used to protect the top of the gate structure 600 during the formation process of the semiconductor structure. In this embodiment, the material of the gate protection layer 650 is silicon nitride.

In this embodiment, the sidewall spacers 700 are located on the sidewalls of the gate structure 600 and the sidewalls of the gate protection layer 650 , and the top of the gate protection layer 650 is flush with the top of the sidewall spacers 700 . In other embodiments, the top of the gate protection layer may also be lower than the top of the spacer.

The interlayer dielectric layer 800 is used to define the formation position and size of the gate structure 600 . In this embodiment, the top of the interlayer dielectric layer 800 is flush with the top of the sidewall 700 .

The material of the interlayer dielectric layer 800 is a low-k dielectric material or an ultra-low-k dielectric material. Compared with common interlayer dielectric layer materials (eg SiO ₂ ), the dielectric constant of the interlayer dielectric layer 800 is smaller, Therefore, the RC delay can be effectively reduced, thereby improving the performance of the semiconductor device.

In this embodiment, the material of the interlayer dielectric layer 800 is SiOC. In other embodiments, the material of the interlayer dielectric layer may also be SiOCH.

The contact hole plug 850 is used to realize electrical connection within the semiconductor device and also to realize the electrical connection between devices.

Specifically, the contact hole plug 850 penetrates the interlayer dielectric layer 800 and the etch stop layer 750 and is electrically connected to the source and drain doped regions (not shown).

In this embodiment, the material of the contact hole plug 850 is Co. In other embodiments, the material of the contact hole plug may also be W.

The resistance value of the material of the contact hole plug 850 is small, which is beneficial to reduce the RC delay.

It should be noted that the semiconductor structure further includes: a titanium layer located between the contact hole plug 850 and the interlayer dielectric layer 800; a titanium silicide layer located between the contact hole plug 850 and the substrate between; a titanium nitride layer, located between the contact hole plug 850 and the titanium layer, and between the contact hole plug 850 and the titanium silicide layer.

The titanium layer has good adhesion to the substrate and the second interlayer dielectric layer 800, which is beneficial to improve the formation quality of the titanium nitride layer; the titanium silicide layer is composed of the titanium layer and the second interlayer dielectric layer. The silicon in the base material at the position of the source and drain doped regions is reacted and generated, and the titanium silicide layer is used to reduce the contact resistance of the contact hole plug 850 .

The role of the titanium nitride layer is: on the one hand, the titanium nitride layer can prevent the reactant used in forming the contact hole plug 850 from reacting with the base material at the position of the source and drain doped regions can also prevent the reactant used from reacting with the titanium silicide layer; on the other hand, the titanium nitride layer is used to improve the material of the contact hole plug 850 when the contact hole plug 850 is formed. To improve the adhesion, the titanium nitride layer can function as a contact hole liner layer.

The material of the interlayer dielectric layer 800 of the semiconductor structure of the present invention is a low-k dielectric material or an ultra-low-k dielectric material. Compared with commonly used interlayer dielectric layer materials (eg SiO ₂ ), the interlayer dielectric layer 800 of the present invention The dielectric constant is small, so that the RC delay can be effectively reduced, thereby improving the performance of the semiconductor device.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. A method for forming a semiconductor structure, comprising: providing a substrate with a gate structure on the substrate, a first interlayer dielectric layer on the substrate exposed by the gate structure, and the top of the gate structure exposed by the first interlayer dielectric layer; removing the first interlayer dielectric layer; After removing the first interlayer dielectric layer, a second interlayer dielectric layer is formed on the exposed substrate of the gate structure, the second interlayer dielectric layer exposes the top of the gate structure, and the second layer The relative permittivity of the interlayer dielectric layer is smaller than the relative permittivity of the first interlayer medium layer; A contact hole plug is formed in the second interlayer dielectric layer, the contact hole plug is electrically connected to the substrate, and the step of forming a contact hole plug in the second interlayer dielectric layer includes: removing the first A sacrificial layer is formed to form a contact opening; a conductive material is filled into the contact opening, wherein the first sacrificial layer is located on the substrate on both sides of the gate structure and penetrates the second interlayer dielectric layer on both sides of the gate structure, The top of the first sacrificial layer is flush with the top of the gate structure. 2 . The method for forming a semiconductor structure according to claim 1 , wherein the material of the first interlayer dielectric layer is SiO ₂ . 3 . 3 . The method for forming a semiconductor structure according to claim 1 , wherein the material of the second interlayer dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material. 4 . 4 . The method for forming a semiconductor structure according to claim 1 , wherein the material of the second interlayer dielectric layer is SiOC or SiOCH. 5 . 5 . The method for forming a semiconductor structure according to claim 1 , wherein after removing the first interlayer dielectric layer, before forming a second interlayer dielectric layer on the exposed substrate of the gate structure, the The forming method further includes: forming a first sacrificial layer on the exposed substrate of the gate structure, the first sacrificial layer exposing the top of the gate structure; part of the first sacrificial layer on both sides of the gate structure forming a mask layer thereon; using the mask layer as a mask, etching the first sacrificial layer to expose part of the substrate; The step of forming the second interlayer dielectric layer includes: after etching the first sacrificial layer, forming a second interlayer dielectric layer on the exposed substrate; After the second interlayer dielectric layer is formed, the forming method further includes: removing the remaining first sacrificial layer, and forming a contact opening in the second interlayer dielectric layer exposing the substrate; The step of forming a contact hole plug in the second interlayer dielectric layer includes: filling the contact opening with a conductive material to form a contact hole plug. 6 . The method for forming a semiconductor structure according to claim 5 , wherein the material of the first sacrificial layer is polysilicon. 7 . 7 . The method for forming a semiconductor structure according to claim 5 , wherein the material of the mask layer is SiO ₂ , SiN or TiN. 8 . 8. The method for forming a semiconductor structure according to claim 5, wherein the thickness of the mask layer is

to

9. The method for forming a semiconductor structure according to claim 5, wherein the step of forming a second interlayer dielectric layer on the exposed substrate comprises: forming an interlayer dielectric film on the exposed substrate, the interlayer dielectric film covers the top of the gate structure; forming a second sacrificial layer on the interlayer dielectric film; Using a planarization process, the second sacrificial layer and the interlayer dielectric film above the top of the gate structure are removed, and the interlayer dielectric film remains as the second interlayer dielectric layer. 10 . The method for forming a semiconductor structure according to claim 9 , wherein in the step of forming an interlayer dielectric film on the exposed substrate, the thickness of the interlayer dielectric film is 10 .

to

11 . The method of claim 9 , wherein the second sacrificial layer is a tetraethyl orthosilicate layer or a plasma enhanced oxide layer. 12 . 12 . The method for forming a semiconductor structure according to claim 9 , wherein the thickness of the second sacrificial layer is 12 .

to

13 . The method for forming a semiconductor structure according to claim 1 , wherein the material of the contact hole plug is Co or W. 14 . 14. The method for forming a semiconductor structure according to claim 1, wherein in the step of providing the substrate, a gate protection layer is provided on the top of the gate structure; In the step of forming a second interlayer dielectric layer on the exposed substrate, the second interlayer dielectric layer exposes the top of the gate protection layer. 15 . The method for forming a semiconductor structure according to claim 14 , wherein the gate protection layer is made of silicon nitride. 16 . 16. A semiconductor structure, characterized in that it comprises: base; a gate structure on the substrate; An interlayer dielectric layer is located on the exposed substrate of the gate structure, and the top of the gate structure is exposed from the interlayer dielectric layer, and the material of the interlayer dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material ; Contact hole plugs, located in the interlayer dielectric layers on both sides of the gate structure and electrically connected to the substrate, the contact hole plugs are formed by removing the first sacrificial layer and then filled with conductive materials, wherein the The first sacrificial layer is located on the substrate on both sides of the gate structure and penetrates the interlayer dielectric layers on both sides of the gate structure, and the top of the first sacrificial layer is flush with the top of the gate structure. 17. The semiconductor structure of claim 16, wherein the material of the interlayer dielectric layer is SiOC or SiOCH. 18. The semiconductor structure of claim 16, wherein the material of the contact hole plug is Co or W. 19. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: a gate protection layer on top of the gate structure; The interlayer dielectric layer exposes the top of the gate protection layer. 20. The semiconductor structure of claim 19, wherein the gate protection layer is made of silicon nitride.

Images