CN108957814B - Liquid crystal display device and circuit compensation method - Google Patents
Liquid crystal display device and circuit compensation method Download PDFInfo
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- CN108957814B CN108957814B CN201810991678.9A CN201810991678A CN108957814B CN 108957814 B CN108957814 B CN 108957814B CN 201810991678 A CN201810991678 A CN 201810991678A CN 108957814 B CN108957814 B CN 108957814B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The invention provides a liquid crystal display device and a circuit compensation method, comprising the following steps: the first metal layer, the semiconductor layer, the second metal layer, and be located common electrode and pixel electrode of second metal layer top, common electrode and pixel electrode are located different layers, wherein, the first metal layer includes first signal line and second signal line, first signal line and second signal line pass through the opening respectively with pixel electrode and one electric connection in the common electrode, the metal level outside signal line and the data line forms compensation capacitor, or the metal level of data line and other non-signal lines forms compensation capacitor, or the signal line passes through the mode of other metal level mutual compensation, the design space of demultiplexing circuit has been reduced, be favorable to reducing the size at lower border, effectively save panel design area, reduce design cost.
Description
Technical Field
The invention belongs to the technical field of liquid crystal display, and particularly relates to a liquid crystal display device and a circuit compensation method.
Background
Currently, the design of the DeMUX (demultiplexing circuit) has a 1:2 (or 1:3, etc.) form, which can transmit the source signal output by the IC terminal to the pixel data line in a 1:2 form, the source line output by the IC terminal is reduced by half, and the number of ICs is also reduced by half, so the design cost of the panel is reduced.
However, when the data line potential reaches a predetermined value, the MUX (Multiplexer, MUX for short) is turned off, the clock signal CK jumps, and the data line potential also fluctuates due to the influence of the potential jump of the clock signal CK, and the data line is compensated by using the reverse signal CK'.
In the prior art, an electrode for outputting a reverse signal CK 'and a data line form an overlapping capacitor, and the electrode for outputting a clock signal CK and the electrode for outputting the reverse signal CK' are made of the same layer of metal, so that the occupied area of the design is twice that of the uncompensated design, and a large amount of panel space is occupied.
As shown in fig. 1, the liquid crystal display device includes a first signal line 01 which outputs a clock signal CK1, a second signal line 02 which outputs a clock signal CK2, a third signal line 03 which outputs an inversion signal CK1 ', and a fourth signal line 04 which outputs an inversion signal CK 2', and the first signal line 01, the second signal line 02, the third signal line 03, and the fourth signal line 04 are formed of the same metal layer, and therefore occupy a large panel space.
Fig. 2(a) and 2(b) show the compensation principle of the circuit, when the clock signal CK1 is at high potential, the TFT1 is turned on, and the potential on the Data line Data1 rises and is finally equal to the potential on the source line; when the clock signal CK1 drops to a negative voltage, the TFT1 is turned off, the Data line Data1 is disconnected from the source line, and the clock signal CK1 pulls the voltage on the Data line Data1 downward through the capacitor Cgs, so that the final voltage on the Data line Data1 is lower than the voltage on the source line. In order to solve the problem that the clock signal CK1 pulls the potential of the Data line Data1, a compensation capacitor Cgs 'and a reverse signal CK 1' are adopted, when the potential of the clock signal CK1 is reduced, the reverse signal CK1 'is increased, the compensation capacitor Cgs' pulls the potential of the Data line Data1 upwards, the effect of the clock signal CK1 is offset, and finally the potential on the Data line Data1 is kept at a desired value. The potential 05 on the Data line Data1 before compensation is obviously different from the potential 06 on the Data line Data1 after compensation.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a liquid crystal display device and a circuit compensation method, which solve the problem that the area occupied by the existing design is twice that of the design without compensation, and a large amount of panel space is occupied.
The technical scheme provided by the invention is as follows:
the invention provides a liquid crystal display device, comprising: a first metal layer (1); a semiconductor layer (3); a second metal layer (5); and a common electrode (8) and a pixel electrode (10) located above the second metal layer (5); an insulating layer between the common electrode (8) and the pixel electrode (10);
the first metal layer (1) comprises a first signal line, a second signal line, a third signal line and a fourth signal line, the third signal line and the fourth signal line are respectively and electrically connected with one of the pixel electrode (10) and the common electrode (8) through openings, and the other of the pixel electrode (10) and the common electrode (8) is electrically connected with the second metal layer (5) through openings;
when the potential of the first signal line is lowered, the potential of the third signal line is raised; when the potential of the second signal line is lowered, the potential of the fourth signal line is raised.
Preferably, a first opening is arranged on the third signal line, a second opening is arranged on the fourth signal line, and a third opening and a fourth opening are arranged on the second metal layer (5);
the third signal line is electrically connected with the pixel electrode (10) through the first opening, the fourth signal line is electrically connected with the pixel electrode (10) through the second opening, and the second metal layer (5) is electrically connected with the common electrode (8) through the third opening and the fourth opening;
or, the third signal line is electrically connected with the common electrode (8) through the first opening, the fourth signal line is electrically connected with the common electrode (8) through the second opening, and the second metal layer (5) is electrically connected with the pixel electrode (10) through the third opening and the fourth opening.
The invention provides a liquid crystal display device, comprising: a first metal layer (1); a semiconductor layer (3); a second metal layer (5); and an electrode (20) located above the second metal layer (5); an insulating layer between the electrode (20) and the second metal layer (5);
the first metal layer (1) comprises a first signal line, a second signal line, a third signal line and a fourth signal line, and the third signal line and the fourth signal line are respectively and electrically connected with the electrode (20) through the opening;
when the potential of the first signal line is lowered, the potential of the third signal line is raised; when the potential of the second signal line is lowered, the potential of the fourth signal line is raised.
Preferably, a first opening is formed in the third signal line, the third signal line is electrically connected with the electrode (20) through the first opening, a second opening is formed in the fourth signal line, and the fourth signal line is electrically connected with the electrode (20) through the second opening.
The invention provides a liquid crystal display device, comprising: a first metal layer (1); a semiconductor layer (3); a second metal layer (5); and a common electrode (8) and a pixel electrode (10) located above the second metal layer (5); an insulating layer between the common electrode (8) and the pixel electrode (10);
the first metal layer (1) comprises a first signal line and a second signal line, the first signal line and the second signal line are respectively and electrically connected with one of the pixel electrode (10) and the common electrode (8) through the openings, and the other of the pixel electrode (10) and the common electrode (8) is electrically connected with the second metal layer (5) through the openings;
when the potential of the first signal line is lowered, the potential of the second signal line is raised; when the second signal line potential is lowered, the first signal line potential is raised.
Preferably, a first opening is formed in the first signal line, the first signal line is electrically connected with the pixel electrode (10) through the first opening, a second opening is formed in the second signal line, the second signal line is electrically connected with the pixel electrode (10) through the second opening, a third opening and a fourth opening are formed in the second metal layer (5), and the second metal layer (5) is electrically connected with the common electrode (8) through the third opening and the fourth opening.
The invention provides a liquid crystal display device, comprising: a first metal layer (1); a semiconductor layer (3); a second metal layer (5); and an electrode (20) located above the second metal layer (5); an insulating layer between the electrode (20) and the second metal layer (5);
the first metal layer (1) comprises a first signal line and a second signal line, and the first signal line and the second signal line are respectively and electrically connected with the electrode (20) through the openings;
when the potential of the first signal line is lowered, the potential of the second signal line is raised; when the second signal line potential is lowered, the first signal line potential is raised.
Preferably, a first opening is arranged on the first signal line, the first signal line is electrically connected with the electrode (20) through the first opening, a second opening is arranged on the second signal line, and the second signal line is electrically connected with the electrode (20) through the second opening.
Preferably, the electrode (20) is a pixel electrode or a common electrode.
The present invention provides a circuit compensation method using any of the above liquid crystal display devices.
Compared with the prior art, the invention has at least one of the following beneficial effects:
1. the invention can compensate the jump influence of the clock signal CK.
2. The invention reduces the panel space required for the design of the compensation circuit.
Drawings
The present invention will be further described in the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a conventional LCD device;
FIG. 2(a) is a schematic diagram of a demultiplexing circuit;
FIG. 2(b) is a schematic diagram of the compensation principle of the demultiplexing circuit;
FIG. 3 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view taken along line A-A' of a liquid crystal display device according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a liquid crystal display device according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a liquid crystal display device according to another embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view taken along line A-A' of a liquid crystal display device according to another embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a liquid crystal display device according to another embodiment of the present invention;
FIG. 9 is a schematic view of a liquid crystal display device according to another embodiment of the present invention;
FIG. 10 is a schematic view of a cross-sectional structure A-A' of a liquid crystal display device according to another embodiment of the present invention;
FIG. 11 is a schematic cross-sectional view of a liquid crystal display device according to another embodiment of the present invention;
FIG. 12 is a schematic view of a liquid crystal display device according to another embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view taken along line A-A' of a liquid crystal display device according to another embodiment of the present invention;
FIG. 14 is a schematic cross-sectional view of a liquid crystal display device according to another embodiment of the present invention;
FIG. 15 is a schematic view of a liquid crystal display device according to another embodiment of the present invention;
FIG. 16 is a schematic cross-sectional view taken along line A-A' of a liquid crystal display device according to another embodiment of the present invention;
fig. 17 is a schematic view of a cross-sectional structure B-B' of a liquid crystal display device according to another embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The technical solution of the present invention is described in detail with specific examples below.
Example one
As shown in fig. 3 to 5, the liquid crystal display device of the present embodiment has a structure in which a substrate, which may be but not limited to a glass substrate, is formed with a first metal layer 1 on the substrate, the first metal layer 1 is made of a single metal or a composite metal, the first metal layer 1 includes a gate electrode (not shown), a first signal line 101 for outputting a first clock signal CK1, a second signal line 102 for outputting a second clock signal CK2, a third signal line 103 for outputting a third clock signal CK1 ', a fourth signal line 104 for outputting a fourth clock signal CK 2', a gate insulating film 2 formed on the layer where the first metal layer 1 is located, and the first insulating film 2 is made of SiO 2xAnd/or SiNxThe semiconductor layer 3 may be an IGZO semiconductor layer, the etch barrier layer 4 formed on the semiconductor layer 3, the second metal layer 5 formed on the etch barrier layer 4, the second metal layer 5 including a source electrode and a drain electrode, the second metal layer 5 having one or more metal layer structures, the second insulating layer 6 formed on the second metal layer 5, the third insulating layer 7 formed on the second insulating layer 6, the common electrode 8 formed on the third insulating layer 7, the fourth insulating layer 9 formed on the common electrode 8, and the pixel electrode 10 formed on the fourth insulating layer 9, wherein the material of the second insulating layer 6 and the fourth insulating layer 9 may be SiOx, SiNx, or a combination thereof, and the third insulating layer 7 may be an organic insulating layer.
As shown in fig. 3, the third signal line 103 and the fourth signal line 104 are electrically connected to the pixel electrode 10 through the opening, and the common electrode 8 is electrically connected to the second metal layer 5 through the opening, so that the common electrode 8 and the pixel electrode 10 overlap to form a compensation capacitor. The third signal line 103 has a first opening 11, the fourth signal line 104 has a second opening 12, and the second metal layer 5 has a third opening 13 and a fourth opening 14.
As shown in fig. 3 and 4, the pixel electrode 10 is partially located in the first opening 11, the third signal line 103 is electrically connected to the pixel electrode 10, the common electrode 8 is partially located in the third opening 13, and part of the fourth insulating layer 9 is also located in the third opening 13, the second metal layer 5 is electrically connected to the common electrode 8, so that the pixel electrode 10 and the common electrode 8 are overlapped to form a compensation capacitor Cgs ', and the third clock signal CK1 ' output by the third signal line 103 and the compensation capacitor Cgs ' pull the potential of the data line, thereby canceling the effect of the first clock signal CK1 output by the first signal line 101, and keeping the potential on the data line at a desired value.
As shown in fig. 3 and 5, the pixel electrode 10 is partially located in the second opening 12, the fourth signal line 104 is electrically connected to the pixel electrode 10, the common electrode 8 is partially located in the fourth opening 14, and part of the fourth insulating layer 9 is also located in the fourth opening 14, the second metal layer 5 is electrically connected to the common electrode 8, so that the pixel electrode 10 and the common electrode 8 are overlapped to form a compensation capacitor Cgs ', and the fourth clock signal CK2 ' output by the fourth signal line 104 and the compensation capacitor Cgs ' pull the potential of the data line, thereby canceling the effect of the second clock signal CK2 output by the second signal line 102, and keeping the potential on the data line at a desired value.
In addition, as an alternative embodiment, as shown in fig. 6 to 8, the third signal line 103 and the fourth signal line 104 are electrically connected to the common electrode 8 through the opening, and the pixel electrode 10 is electrically connected to the second metal layer 5 through the opening, so that the common electrode 8 and the pixel electrode 10 overlap to form a compensation capacitor. The third signal line 103 has a first opening 11, the fourth signal line 104 has a second opening 12, and the second metal layer 5 has a third opening 13 and a fourth opening 14.
As shown in fig. 6 and 7, the common electrode 8 is partially located in the first opening 11, and a portion of the fourth insulating layer 9 is also located in the first opening 11, the third signal line 103 is electrically connected to the common electrode 8, the pixel electrode 10 is partially located in the third opening 13, and the second metal layer 5 is electrically connected to the pixel electrode 10, so that the common electrode 8 and the pixel electrode 10 overlap to form a compensation capacitor Cgs ', and the third clock signal CK1 ' output by the third signal line 103 and the compensation capacitor Cgs ' pull the potential of the data line, thereby canceling the effect of the first clock signal CK1 output by the first signal line 101, and keeping the potential on the data line at a desired value.
As shown in fig. 6 and 8, the common electrode 8 is partially located in the second opening 12, and a portion of the fourth insulating layer 9 is also located in the second opening 12, the fourth signal line 104 is electrically connected to the common electrode 8, the pixel electrode 10 is partially located in the fourth opening 14, and the second metal layer 5 is electrically connected to the pixel electrode 10, so that the common electrode 8 and the pixel electrode 10 are overlapped to form a compensation capacitor Cgs ', and the fourth clock signal CK2 ' output by the fourth signal line 104 and the compensation capacitor Cgs ' pull the data line, thereby canceling the effect of the second clock signal CK2 output by the second signal line 102, and keeping the potential on the data line at a desired value.
In the above embodiment, the third signal line and the fourth signal line are electrically connected to one of the pixel electrode or the common electrode through the via hole, and the other of the pixel electrode or the common electrode is electrically connected to the metal layer through the via hole, so that the pixel electrode and the common electrode are overlapped to form a compensation capacitor, the widths of the third signal line and the fourth signal line are reduced, and the design area of the panel is effectively saved.
Example two
As shown in fig. 9 to 11, the liquid crystal display device of the present embodiment has a structure in which a substrate, which may be but not limited to a glass substrate, is formed with a first metal layer 1 on the substrate, the first metal layer 1 is made of a single metal or a composite metal, the first metal layer 1 includes a gate electrode (not shown), a first signal line 201 for outputting a first clock signal CK1, a second signal line 202 for outputting a second clock signal CK2, a third signal line 203 for outputting a third clock signal CK1 ', a fourth signal line 204 for outputting a fourth clock signal CK 2', and a gate insulating film 2 formed on the layer where the first metal layer 1 is located is formedThe first insulating film 2 is made of SiOxAnd/or SiNxThe semiconductor layer 3 may be an IGZO semiconductor layer, the etch barrier layer 4 formed on the semiconductor layer 3, the second metal layer 5 formed on the etch barrier layer 4, the second metal layer 5 including a source electrode and a drain electrode, the second metal layer 5 having one or more metal layer structures, the second insulating layer 6 formed on the second metal layer 5, and the electrode 20 formed on the second insulating layer 6, wherein the electrode 20 is a pixel electrode, and the material of the second insulating layer 6 may be SiOx, SiNx, or a combination thereof.
As shown in fig. 9, the third signal line 203 and the fourth signal line 204 are electrically connected to the electrode 20 through the opening, and the electrode 20 and the second metal layer 5 overlap to form a compensation capacitor. The third signal line 203 has a first opening 21, and the fourth signal line 204 has a second opening 22.
As shown in fig. 9 and 10, the electrode 20 is partially located in the first opening 21, the third signal line 203 is electrically connected to the electrode 20, and the second insulating layer 6 is located between the electrode 20 and the second metal layer 5, so that the electrode 20 and the second metal layer 5 are overlapped to form a compensation capacitor Cgs ', and the third clock signal CK1 ' output by the third signal line 203 and the compensation capacitor Cgs ' pull the potential of the data line, thereby canceling the effect of the first clock signal CK1 output by the first signal line 201, and keeping the potential of the data line at a desired value.
As shown in fig. 9 and 11, the electrode 20 is partially located in the second opening 22, the fourth signal line 204 is electrically connected to the electrode 20, and the second insulating layer 6 is located between the electrode 20 and the second metal layer 5, so that the overlapping of the electrode 20 and the second metal layer 5 also forms a compensation capacitor Cgs ', and the fourth clock signal CK2 ' output by the fourth signal line 204 and the compensation capacitor Cgs ' pull the potential of the data line, thereby canceling the effect of the second clock signal CK2 output by the second signal line 202, and keeping the potential of the data line at a desired value.
Further, as an alternative embodiment, the electrode 20 is a common electrode.
In the above embodiment, the third signal line and the fourth signal line are electrically connected to the pixel electrode or the common electrode through the via hole, so that the pixel electrode or the common electrode and the metal layer are overlapped to form the compensation capacitor, the widths of the third signal line and the fourth signal line are further reduced, and the design area of the panel is effectively saved.
EXAMPLE III
As shown in fig. 12 to 14, the liquid crystal display device of the present embodiment has a structure in which a substrate, which may be but not limited to a glass substrate, is formed with a first metal layer 1 on the substrate, the first metal layer 1 is made of a single metal or a composite metal, the first metal layer 1 includes a gate electrode (not shown), a first signal line 301 for outputting a first clock signal CK1, a second signal line 302 for outputting a second clock signal CK2, a gate insulating film 2 formed on the first metal layer 1, and the first insulating film 2 is made of SiOxAnd/or SiNxThe semiconductor layer 3 may be an IGZO semiconductor layer, the etch barrier layer 4 formed on the semiconductor layer 3, the second metal layer 5 formed on the etch barrier layer 4, the second metal layer 5 including a source electrode and a drain electrode, the second metal layer 5 having one or more metal layer structures, the second insulating layer 6 formed on the second metal layer 5, the third insulating layer 7 formed on the second insulating layer 6, the common electrode 8 formed on the third insulating layer 7, the fourth insulating layer 9 formed on the common electrode 8, and the pixel electrode 10 formed on the fourth insulating layer 9, wherein the material of the second insulating layer 6 and the fourth insulating layer 9 may be SiOx, SiNx, or a combination thereof, and the third insulating layer 7 may be an organic insulating layer.
As shown in fig. 12, the first signal line 301 is electrically connected to the common electrode 8 through the opening, the second signal line 302 is electrically connected to the pixel electrode 10 through the opening, and the second metal layer 5 is electrically connected to the pixel electrode 10 and the common electrode 8 through the opening, respectively, so that the common electrode 8 and the pixel electrode 10 are overlapped to form a compensation capacitor. The second metal layer 5 is provided with a first opening 31 and a fourth opening 34, the first signal line 302 is provided with a second opening 32, and the second signal line 302 is provided with a third opening 33.
As shown in fig. 12 and 13, the common electrode 8 is partially located in the first opening 31, and a portion of the fourth insulating layer 9 is also located in the first opening 31, the second metal layer 5 is electrically connected to the common electrode 8, the pixel electrode 10 is partially located in the third opening 33, and the second signal line 302 is electrically connected to the pixel electrode 10, so that the common electrode 8 and the pixel electrode 10 are overlapped to form a compensation capacitor Cgs ', and the second clock signal CK2 output from the second signal line 302 and the compensation capacitor Cgs' pull the data line, thereby canceling the effect of the first clock signal CK1 output from the first signal line 301, and keeping the potential on the data line at a desired value.
As shown in fig. 12 and 14, the common electrode 8 is partially located in the second opening 32, and a portion of the fourth insulating layer 9 is also located in the second opening 32, the first signal line 301 is electrically connected to the common electrode 8, the pixel electrode 10 is partially located in the fourth opening 34, and the second metal layer 5 is electrically connected to the pixel electrode 10, so that the common electrode 8 and the pixel electrode 10 overlap to form a compensation capacitor Cgs ', and the first clock signal CK1 output from the first signal line 301 and the compensation capacitor Cgs' pull the data line, thereby canceling the effect of the second clock signal CK2 output from the second signal line 302, and keeping the potential on the data line at a desired value.
In addition, as an alternative embodiment, the first signal line 301 is electrically connected to the pixel electrode 10 through the opening, the second signal line 302 is electrically connected to the common electrode 8 through the opening, and the second metal layer 5 is electrically connected to the pixel electrode 10 and the common electrode 8 through the opening, respectively, so that the common electrode 8 and the pixel electrode 10 are overlapped to form a compensation capacitor.
The second metal layer 5 is electrically connected with the pixel electrode 10 through the opening, and the second signal line 302 is electrically connected with the common electrode 8 through the opening, so that the common electrode 8 and the pixel electrode 10 are overlapped to form a compensation capacitor Cgs ', and the second clock signal CK2 output by the second signal line 302 and the compensation capacitor Cgs' pull the potential of the data line, thereby counteracting the action of the first clock signal CK1 output by the first signal line 301, and keeping the potential on the data line at a desired value.
The second metal layer 5 is electrically connected with the common electrode 8 through the opening, the first signal line 301 is electrically connected with the pixel electrode 10 through the opening, so that the common electrode 8 and the pixel electrode 10 are overlapped to form a compensation capacitor Cgs ', and the first clock signal CK1 output by the first signal line 301 and the compensation capacitor Cgs' pull the potential of the data line, so as to counteract the effect of the second clock signal CK2 output by the second signal line 302, and make the potential on the data line keep the expected value.
In the above embodiment, the first signal line and the second signal line are electrically connected to one of the pixel electrode or the common electrode through the via hole, and the other of the pixel electrode or the common electrode is electrically connected to the metal layer through the via hole, so that the pixel electrode and the common electrode are overlapped to form the compensation capacitor, and the first signal line and the second signal line are mutually compensated, thereby omitting the third signal line and the fourth signal line, and more effectively saving the design area of the panel.
Example four
As shown in fig. 15 to 17, the liquid crystal display device of the present embodiment has a structure in which a substrate, which may be but not limited to a glass substrate, is formed with a first metal layer 1 on the substrate, the first metal layer 1 is made of a single metal or a composite metal, the first metal layer 1 includes a gate electrode (not shown), a first signal line 201 for outputting a first clock signal CK1, a second signal line 202 for outputting a second clock signal CK2, a gate insulating film 2 formed on the first metal layer 1, and the first insulating film 2 is made of SiOxAnd/or SiNxThe semiconductor layer 3 may be an IGZO semiconductor layer, the etch barrier layer 4 formed on the semiconductor layer 3, the second metal layer 5 formed on the etch barrier layer 4, the second metal layer 5 including a source electrode and a drain electrode, the second metal layer 5 having one or more metal layer structures, the second insulating layer 6 formed on the second metal layer 5, and the electrode 20 formed on the second insulating layer 6, wherein the electrode 20 is a pixel electrode or a common electrode, and the material of the second insulating layer 6 may be SiOx, SiNx, or a combination thereof.
As shown in fig. 15, the first signal line 201 and the second signal line 202 are electrically connected to the electrode 20 through the opening, and the electrode 20 and the second metal layer 5 overlap to form a compensation capacitor. The second signal line 202 has a first opening 41, and the first signal line 201 has a second opening 42.
As shown in fig. 15 and 16, the electrode 20 is partially located in the first opening 41, the second signal line 202 is electrically connected to the electrode 20, and the second insulating layer 6 is located between the electrode 20 and the second metal layer 5, so that the electrode 20 and the second metal layer 5 are overlapped to form a compensation capacitor Cgs ', and the second clock signal CK2 output by the second signal line 202 and the compensation capacitor Cgs' pull the potential of the data line, thereby canceling the effect of the first clock signal CK1 output by the first signal line 201, and keeping the potential of the data line at a desired value.
As shown in fig. 15 and 17, the electrode 20 is partially located in the second opening 42, the first signal line 201 is electrically connected to the electrode 20, and the second insulating layer 6 is located between the electrode 20 and the second metal layer 5, so that the overlapping of the electrode 20 and the second metal layer 5 also forms a compensation capacitor Cgs ', and the first clock signal CK1 output from the first signal line 201 and the compensation capacitor Cgs' pull the potential of the data line, thereby canceling the effect of the second clock signal CK2 output from the second signal line 202, and keeping the potential on the data line at a desired value.
Further, as an alternative embodiment, the electrode 20 is a common electrode.
In the above embodiment, the first signal line and the second signal line are electrically connected to the pixel electrode or the common electrode through the via hole, so that the pixel electrode or the common electrode and the metal layer are overlapped to form the compensation capacitor, and the first signal line and the second signal line are compensated with each other, thereby omitting the third signal line and the fourth signal line, and more effectively saving the design area of the panel.
The invention also discloses a circuit compensation method, which adopts the liquid crystal display device.
The invention also discloses an array substrate, a liquid crystal panel and a display device adopting the liquid crystal display device.
The invention also discloses a demultiplexing circuit applying the liquid crystal display device.
According to the liquid crystal display device and the circuit compensation method, the design space of the demultiplexing circuit is reduced by the mode that the metal layers except the signal line and the data line form the compensation capacitor, or the metal layers of the data line and other non-signal lines form the compensation capacitor, and the signal line is mutually compensated through other metal layers, so that the size of the lower boundary is favorably reduced, the design area of a panel is effectively saved, and the design cost is reduced.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A liquid crystal display device comprising:
a first metal layer (1);
a semiconductor layer (3);
a second metal layer (5); and the number of the first and second groups,
a common electrode (8) and a pixel electrode (10) located above the second metal layer (5);
an insulating layer between the common electrode (8) and the pixel electrode (10);
the first metal layer (1) comprises a first signal line, a second signal line, a third signal line and a fourth signal line, the third signal line and the fourth signal line are respectively and electrically connected with one of the pixel electrode (10) and the common electrode (8), and the other of the pixel electrode (10) and the common electrode (8) is electrically connected with the second metal layer (5);
when the potential of the first signal line is lowered, the potential of the third signal line is raised, and when the potential of the second signal line is lowered, the potential of the fourth signal line is raised.
2. The liquid crystal display device according to claim 1, wherein a first opening is provided in the third signal line, a second opening is provided in the fourth signal line, and a third opening and a fourth opening are provided in the second metal layer (5);
the third signal line is electrically connected with the pixel electrode (10) through the first opening, the fourth signal line is electrically connected with the pixel electrode (10) through the second opening, and the second metal layer (5) is electrically connected with the common electrode (8) through the third opening and the fourth opening;
or, the third signal line is electrically connected with the common electrode (8) through the first opening, the fourth signal line is electrically connected with the common electrode (8) through the second opening, and the second metal layer (5) is electrically connected with the pixel electrode (10) through the third opening and the fourth opening.
3. A liquid crystal display device comprising:
a first metal layer (1);
a semiconductor layer (3);
a second metal layer (5); and the number of the first and second groups,
an electrode (20) located above the second metal layer (5);
an insulating layer between the electrode (20) and the second metal layer (5);
the first metal layer (1) comprises a first signal line, a second signal line, a third signal line and a fourth signal line, and the third signal line and the fourth signal line are respectively and electrically connected with the electrode (20);
when the potential of the first signal line is lowered, the potential of the third signal line is raised, and when the potential of the second signal line is lowered, the potential of the fourth signal line is raised.
4. The liquid crystal display device according to claim 3, wherein the third signal line has a first opening, the third signal line is electrically connected to the electrode (20) through the first opening, the fourth signal line has a second opening, and the fourth signal line is electrically connected to the electrode (20) through the second opening.
5. A liquid crystal display device comprising:
a first metal layer (1);
a semiconductor layer (3);
a second metal layer (5); and the number of the first and second groups,
a common electrode (8) and a pixel electrode (10) located above the second metal layer (5);
an insulating layer between the common electrode (8) and the pixel electrode (10);
the first metal layer (1) comprises a first signal line and a second signal line, the first signal line and the second signal line are respectively and electrically connected with one of the pixel electrode (10) and the common electrode (8), and the other of the pixel electrode (10) and the common electrode (8) is electrically connected with the second metal layer (5);
when the potential of the first signal line is lowered, the potential of the second signal line is raised; when the second signal line potential is lowered, the first signal line potential is raised.
6. The lcd device according to claim 5, wherein the second metal layer (5) has a first opening and a fourth opening, the first signal line has a second opening, the second signal line has a third opening, the second metal layer (5) and the first signal line are electrically connected to the common electrode (8) through the first opening and the third opening, respectively, and the second metal layer (5) and the second signal line are electrically connected to the pixel electrode (10) through the fourth opening and the third opening, respectively.
7. A liquid crystal display device comprising:
a first metal layer (1);
a semiconductor layer (3);
a second metal layer (5); and the number of the first and second groups,
an electrode (20) located above the second metal layer (5);
an insulating layer between the electrode (20) and the second metal layer (5);
the first metal layer (1) comprises a first signal line and a second signal line, and the first signal line and the second signal line are respectively and electrically connected with the electrode (20);
when the potential of the first signal line is lowered, the potential of the second signal line is raised; when the second signal line potential is lowered, the first signal line potential is raised.
8. The liquid crystal display device according to claim 7, wherein the second signal line has a first opening, the second signal line is electrically connected to the electrode (20) through the first opening, the first signal line has a second opening, and the first signal line is electrically connected to the electrode (20) through the second opening.
9. A liquid crystal display device according to claim 3 or 7, characterized in that the electrode (20) is a pixel electrode or a common electrode.
10. A circuit compensation method using the liquid crystal display device according to any one of claims 1 to 9.
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