CN108957289B - Circuit board test pin system and test method - Google Patents
Circuit board test pin system and test method Download PDFInfo
- Publication number
- CN108957289B CN108957289B CN201810620320.5A CN201810620320A CN108957289B CN 108957289 B CN108957289 B CN 108957289B CN 201810620320 A CN201810620320 A CN 201810620320A CN 108957289 B CN108957289 B CN 108957289B
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- test
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- tested
- circuit board
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- 238000012360 testing method Methods 0.000 title claims abstract description 106
- 238000010998 test method Methods 0.000 title claims abstract description 7
- 102000007315 Telomeric Repeat Binding Protein 1 Human genes 0.000 claims description 9
- 108010033711 Telomeric Repeat Binding Protein 1 Proteins 0.000 claims description 9
- 101100190527 Arabidopsis thaliana PIN5 gene Proteins 0.000 claims description 6
- 101100190530 Arabidopsis thaliana PIN8 gene Proteins 0.000 claims description 6
- 101150087393 PIN3 gene Proteins 0.000 claims description 6
- 108010037490 Peptidyl-Prolyl Cis-Trans Isomerase NIMA-Interacting 4 Proteins 0.000 claims description 6
- 102100031653 Peptidyl-prolyl cis-trans isomerase NIMA-interacting 4 Human genes 0.000 claims description 6
- 238000011056 performance test Methods 0.000 claims description 6
- 238000002788 crimping Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 108010059419 NIMA-Interacting Peptidylprolyl Isomerase Proteins 0.000 claims description 3
- 102100026114 Peptidyl-prolyl cis-trans isomerase NIMA-interacting 1 Human genes 0.000 claims description 3
- 210000001503 joint Anatomy 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000013011 mating Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
- G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The utility model provides a circuit board test pin system, includes the circuit board, a plurality of the same test pin, the control panel of printing on the circuit board, arbitrary test pin all with the control panel is connected, a plurality of test pin is the multiseriate form and arranges, and the adjacent row the test pin is the cross arrangement, and the interval is listed as the test pin arrangement mode is the same, still discloses a test method of this circuit board test pin system, and the step is: the invention has the advantages that the problems of inconvenient pin butt joint and easy occurrence of poor test in the prior art are solved, the pin sequence can be automatically detected by utilizing a pin system, the pin definition of a program is automatically adjusted, the test efficiency is improved, and the occurrence of poor test is reduced.
Description
Technical Field
The present invention relates to the field of circuit board testing technologies, and in particular, to a circuit board testing pin system and a testing method.
Background
At present, the FPC connection mode on the display module assembly test tool is generally that the approximate position of the FPC PINs is determined by the positioning baffle according to the appearance of the display module assembly, and the other end of the FPC PINs is a PCB (printed circuit board) or an FPC with the same PIN (PIN). Then PIN carries out the crimping to PIN, and this method error ratio is great, and the counterpoint is inaccurate, and FPC must pass through the counterpoint mark, adopts the positioning baffle, and through module appearance cooperation counterpoint mark location, inefficiency, the frequent short circuit causes the unnecessary damage of module.
Disclosure of Invention
The invention aims to solve the defects of the prior art and provides a circuit board test pin system and a test method which have high test efficiency and can effectively protect a module from being damaged.
The invention solves the problems by adopting the following technical scheme: the circuit board test pin system comprises a circuit board, a plurality of identical test pins printed on the circuit board and a control board, wherein any one of the test pins is connected with the control board, the test pins are distributed in a multi-column mode, the test pins in adjacent columns are arranged in a cross mode, and the test pins in interval columns are identical in arrangement mode.
In some embodiments, the number of columns of test pins is greater than three times the number of columns of pins to be tested.
In some embodiments, the test pins have a width less than one-half of the pins to be tested and a length less than one-fifth of the pins to be tested.
In some embodiments, the test pin width is one third of the pin to be tested and the test pin length is one fifth of the pin to be tested.
In some embodiments, the pitch between columns of test pins is one third of the width of the pins to be tested.
A testing method of a circuit board testing pin system comprises the following steps:
(1) Defining each two adjacent columns of test pins as a test group, wherein the number of the test groups is K, K=1, 2,3 … and N, any one of the test groups carries out numbering definition on the test pins from top to bottom, the number is J, J=1, 2,3 … and N, and any one of the test pins is PINJ-K;
(2) Placing the golden finger surface of the pin to be tested in line with the golden finger surface of the test pin in the horizontal direction and crimping;
(3) Controlling PIN1-1 to PIN1-N to output high level, controlling PIN3-1 to PIN3-N, PIN4-1 to PIN4-N as input, detecting corresponding PIN signals, recording high level signals detected by PIN2 and PIN3 rows, and performing performance test;
(4) If the PIN2 and the PIN3 are not successfully detected, the voltage of the PIN1 row is disconnected, the PIN2 row is pressed, the PIN4 row and the PIN5 row are detected, performance test is carried out, and if the PIN4 row and the PIN5 row are not successfully detected, the test is carried out by analogy.
In some embodiments, the test pins are regularly distributed with pins to be tested.
The invention has the beneficial effects that: the pin sequence can be automatically detected by utilizing the pin system, the pin definition of a program can be automatically adjusted, the testing efficiency is improved, and the generation of testing faults is reduced.
Drawings
FIG. 1 is a schematic diagram of a pin system according to the present invention;
FIG. 2 is a diagram of a normal mating system of a test pin and a pin to be tested during testing according to the present invention;
FIG. 3 is a diagram of a system for mating with a test pin when the test pin is placed obliquely in accordance with the present invention;
in the figure, 1, a test pin; 2. a control board; 3. a circuit board.
Detailed Description
The invention is further described below with reference to the drawings and examples.
In fig. 1, a circuit board test pin system includes a circuit board 3, a plurality of identical test pins 1 printed on the circuit board, and a control board 2, wherein any one of the test pins 1 is connected with the control board 2, the test pins 1 are arranged in a plurality of rows, the test pins 1 in adjacent rows are arranged in a cross manner, and the test pins 1 in spaced rows are arranged in the same manner.
The number of columns of the test pin 1 is greater than three times of the number of columns of the pins to be tested, the width of the test pin 1 is smaller than one half of the pins to be tested, the length of the test pin 1 is smaller than one fifth of the pins to be tested, specifically, the width of the test pin 1 is one third of the pins to be tested, the length of the test pin 1 is one fifth of the pins to be tested, and the space between the columns of the test pin 1 is one third of the width of the pins to be tested.
The minimum width of the test pins is 0.1mm, the length is 0.1mm and the pin spacing is 0.2mm according to the FPC etching precision, so the minimum size of the test pins with the test pins is 0.3 mm wide, 0.5mm long and the pin spacing is 0.6mm. And determining the positions of the pins to be tested in an interlaced mode, and secondly, preventing the short circuit problem caused by the fact that the pins to be tested are bridged between two rows of detection pins.
A testing method of a circuit board testing pin system comprises the following steps:
(1) Defining each two adjacent columns of test pins as a test group, wherein the number of the test groups is K, K=1, 2,3 … and N, any one of the test groups carries out numbering definition on the test pins from top to bottom, the number is J, J=1, 2,3 … and N, and any one of the test pins is PINJ-K;
(2) Placing the golden finger surface of the pin to be tested in line with the golden finger surface of the test pin in the horizontal direction and crimping;
(3) Controlling PIN1-1 to PIN1-N to output high level, controlling PIN3-1 to PIN3-N, PIN4-1 to PIN4-N as input, detecting corresponding PIN signals, recording high level signals detected by PIN2 and PIN3 rows, and performing performance test;
(4) If the PIN2 and the PIN3 are not successfully detected, the voltage of the PIN1 row is disconnected, the PIN2 row is pressed, the PIN4 row and the PIN5 row are detected, performance test is carried out, and if the PIN4 row and the PIN5 row are not successfully detected, the test is carried out by analogy.
The test pins 1 and the pins to be tested are distributed regularly.
Specifically, referring to fig. 2, the golden finger surface of fpc pins of the module to be tested is placed in line with the golden finger surface of the test pins in the horizontal direction and is artificially pressed, so that the pins on the two surfaces are in close contact. When the pins of the module to be tested fpc are distributed regularly with the pins to be tested, and the horizontal directions of the pins of the module to be tested fpc are consistent with the horizontal directions of the pins to be tested, 1 column of the pins to be tested fpc does not correspond to every 3 columns of the pins to be tested, and the interval rows of the pins to be tested are affected by short circuits of the pins to be tested.
In fig. 3, if the FPC is placed obliquely, it is found that the rule is that the FPC pins of the module to be tested and the test pins will have a column that does not correspond every n columns, where the size of n is related to the oblique angle of the FPC pins of the module to be tested and the test pins in the horizontal direction. The test pin spacing rows will be shorted by the effect of the pins to be tested. By applying voltage to a row of test pins, the corresponding voltage is detected and judged at intervals, and the pins to be tested are arranged above the pins.
The invention has the advantages that: the pin sequence can be automatically detected by utilizing the pin system, the pin definition of a program can be automatically adjusted, the testing efficiency is improved, and the generation of testing faults is reduced.
The foregoing is illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the claims. The present invention is not limited to the above embodiments, and the specific structure thereof is allowed to vary. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (5)
1. The test method of the circuit board test pin system is characterized in that the circuit board test pin system comprises a circuit board, a plurality of identical test pins printed on the circuit board and a control board, wherein any one of the test pins is connected with the control board, the test pins of a plurality of adjacent columns are distributed in a multi-column manner, the test pins of the adjacent columns are arranged in a cross manner, and the test pins of the interval columns are arranged in the same manner; the test method comprises the following steps:
(1) Defining each two adjacent columns of test pins as a test group, wherein the number of the test groups is K, K=1, 2,3 … and N, any one of the test groups carries out numbering definition on the test pins from top to bottom, the number is J, J=1, 2,3 … and N, and any one of the test pins is PINJ-K;
(2) Placing the golden finger surface of the pin to be tested in line with the golden finger surface of the test pin in the horizontal direction and crimping;
(3) Controlling PIN1-1 to PIN1-N to output high level, controlling PIN3-1 to PIN3-N, PIN4-1 to PIN4-N as input, detecting corresponding PIN signals, recording high level signals detected by PIN2 and PIN3 rows, and performing performance test;
(4) If the PIN2 and the PIN3 are not successfully detected, the voltage of the PIN1 row is disconnected, the PIN2 row is pressed, the PIN4 row and the PIN5 row are detected, performance test is carried out, if the PIN4 row and the PIN5 row are not successfully detected, the test is carried out by analogy;
The test pins and the pins to be tested are distributed regularly; when the pins of the module to be tested fpc are consistent with the horizontal direction of the test pins, 1 column of the pins of the module to be tested fpc are not corresponding to the test pins every 3 columns, and the test pin interval rows are short-circuited under the influence of the pins to be tested; when the FPC is placed obliquely, the rule is that the FPC pins of the to-be-tested module and the test pins are not corresponding to each other in every n columns, the size of n is related to the oblique angle of the FPC pins of the to-be-tested module and the horizontal direction of the test pins, and the interval rows of the test pins are influenced by the short circuit of the to-be-tested pins.
2. The method of claim 1, wherein the number of columns of test pins is greater than three times the number of columns of pins to be tested.
3. The method of claim 1, wherein the test pin has a width less than one half of the pin to be tested and a length less than one fifth of the pin to be tested.
4. A test method according to claim 3, wherein the test pin width is one third of the pin to be tested.
5. The method of claim 4, wherein the pitch between columns of test pins is one third of the width of the pins to be tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810620320.5A CN108957289B (en) | 2018-06-15 | 2018-06-15 | Circuit board test pin system and test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810620320.5A CN108957289B (en) | 2018-06-15 | 2018-06-15 | Circuit board test pin system and test method |
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| Publication Number | Publication Date |
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| CN108957289A CN108957289A (en) | 2018-12-07 |
| CN108957289B true CN108957289B (en) | 2024-08-13 |
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| CN201810620320.5A Active CN108957289B (en) | 2018-06-15 | 2018-06-15 | Circuit board test pin system and test method |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110502382B (en) * | 2019-08-26 | 2023-04-07 | Oppo（重庆）智能科技有限公司 | TYPE-C interface testing method and device, storage medium and electronic equipment |
| CN116184177B (en) * | 2023-04-27 | 2023-12-08 | 合肥中晶新材料有限公司 | Test system for semiconductor integrated circuit package |
| CN118858904A (en) * | 2024-09-25 | 2024-10-29 | 宁德时代新能源科技股份有限公司 | Chip detection method, device, equipment, medium and product |
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| CN208255364U (en) * | 2018-06-15 | 2018-12-18 | 江西兴泰科技有限公司 | A kind of circuit board testing pin system |
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Address after: 343000 in Jizhou Industrial Park, Ji'an City, Jiangxi Province Applicant after: Jiangxi Xingtai Technology Co.,Ltd. Address before: 343000 in Jizhou Industrial Park, Ji'an City, Jiangxi Province Applicant before: JIANGXI XINGTAI TECHNOLOGY Co.,Ltd. |
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