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CN108919874A - A kind of low pressure difference linear voltage regulator - Google Patents

A kind of low pressure difference linear voltage regulator Download PDF

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Publication number
CN108919874A
CN108919874A CN201811005197.2A CN201811005197A CN108919874A CN 108919874 A CN108919874 A CN 108919874A CN 201811005197 A CN201811005197 A CN 201811005197A CN 108919874 A CN108919874 A CN 108919874A
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field effect
type field
pole
effect transistor
signal
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CN108919874B (en
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马寒玉
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Beijing Neural Network Technology Co Ltd
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Beijing Neural Network Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a kind of low pressure difference linear voltage regulators, low pressure difference linear voltage regulator includes amplifier, power switch, bleeder circuit and the second compensating element, and amplifier adjusts the output signal of amplified signal output end according to the input signal of noninverting input, reverse input end and compensation input terminal；Power component adjusts the output signal of second end according to the input signal of control terminal；Bleeder circuit divides the input signal of the first and second voltage division signal input terminals；First power supply signal reduces the variation of the output signal of amplified signal output end caused by the first power supply signal and second source signal intensity by forming access, access between the second compensating element, and second source signal.According to the technical solution of the present invention, while realizing low pressure difference linear voltage regulator voltage stabilizing function and improving supply-voltage rejection ratio at low pressure difference linear voltage regulator intermediate frequency, the problem of improving GBW to improve the increase of power consumption caused by the supply-voltage rejection ratio at intermediate frequency is avoided.

Description

Low dropout regulator
Technical Field
The embodiment of the invention relates to the technical field of integrated circuits, in particular to a low dropout regulator.
Background
With the development of integrated circuit technology, more and more circuits are integrated On a Chip to form an SOC (System On Chip), and especially, wireless transceiver chips, such as analog rf circuits (e.g., LNA (Low Noise Amplifier), PLL (Phase Locked Loop), ADC/DAC (analog-to-digital converter/digital-to-analog converter), and digital circuits (e.g., digital baseband), are integrated On a Chip.
In order to extend the standby time, improve the integration level, and reduce the complexity of the peripheral circuit, the SOC currently adopts a DC (Direct Current)/DC converter combined with a Low Dropout Regulator (LDO) power supply architecture, for example, the DC/DC and the LDO can be directly integrated in the SOC. Because the DC/DC is driven by the clock, the output ripple is large at the working clock frequency, and the PLL, the ADC, the LNA and the like are sensitive to power supply parameters, which puts a high requirement on the power supply voltage rejection ratio index of the LDO.
However, the supply voltage rejection ratio of a common LDO without off-chip capacitance is poor at the intermediate frequency, and the operating clock frequency of DC/DC is substantially at the intermediate frequency of the LDO. The GBW (unit gain bandwidth) of the LDO can be increased to increase its supply voltage rejection ratio at an intermediate frequency, but increasing the GBW of the LDO increases the power consumption of the LDO, resulting in a decrease in the efficiency of the LDO.
Disclosure of Invention
In view of the above, the present invention provides a low dropout regulator, which reduces the influence of the change of the first power signal and the second power signal on the regulated signal output by the low dropout regulator, and avoids the problems of increased power consumption and reduced efficiency of the low dropout regulator caused by increasing the GBW of the low dropout regulator to increase the power supply voltage rejection ratio at the intermediate frequency while achieving the voltage regulation function of the low dropout regulator and increasing the power supply voltage rejection ratio at the intermediate frequency of the low dropout regulator.
The embodiment of the invention provides a low dropout regulator, which comprises:
the amplifier comprises a same-direction input end, an inverse input end, a compensation signal input end and an amplification signal output end, wherein the inverse input end is connected with a reference signal, and the amplifier is used for adjusting an output signal of the amplification signal output end according to input signals of the same-direction input end, the inverse input end and the compensation signal input end;
the power switch comprises a control end, a first end and a second end, the control end is electrically connected with the amplified signal output end, the first end is connected to a first power signal, the second end is used as a voltage-stabilizing signal output end of the low dropout linear regulator, and the power switch is used for adjusting an output signal of the second end according to an input signal of the control end;
the voltage dividing circuit comprises a first voltage dividing signal input end, a second voltage dividing signal input end and a voltage dividing signal output end, the first voltage dividing signal input end is electrically connected with the second end, the second voltage dividing signal input end is connected with a second power signal, the voltage dividing signal output end is electrically connected with the homodromous input end, and the voltage dividing circuit is used for dividing the voltage of input signals of the first voltage dividing signal input end and the second voltage dividing signal input end to form a voltage dividing signal and outputting the voltage dividing signal through the voltage dividing signal output end;
a second compensation element, a first pole of the second compensation element being electrically connected to the compensation signal input terminal, a second pole of the second compensation element being electrically connected to the second divided signal input terminal, the first power signal passing through a path formed between the second compensation element and the second power signal, the path reducing a change in an output signal of the amplified signal output terminal caused by a change in the first power signal and the second power signal.
Specifically, the low dropout regulator further comprises:
the first end of the first impedance element is electrically connected with the control end of the power switch, the second end of the first impedance element is electrically connected with the first pole of the first compensation element, and the second pole of the first compensation element is electrically connected with the second end of the power switch.
In particular, the first compensation element and the second compensation element each comprise a compensation capacitance.
Specifically, the second compensation element includes a plurality of second compensation capacitors, first poles of all the second compensation capacitors are electrically connected as the first poles of the second compensation elements, second poles of all the second compensation capacitors are electrically connected as the second poles of the second compensation elements, and at least a part of the second compensation capacitors are transistor capacitors.
Specifically, the voltage dividing circuit includes:
and a second impedance element and a third impedance element, wherein a first pole of the second impedance element is used as a first voltage division signal input end of the voltage division circuit, a second pole of the second impedance element is electrically connected with a first pole of the third impedance element to be used as a voltage division signal output end of the voltage division circuit, and a second pole of the third impedance element is used as a second voltage division signal input end of the voltage division circuit.
Specifically, the power switch includes a field effect transistor, a gate of the field effect transistor serves as the control terminal of the power switch, a first pole of the field effect transistor serves as a first terminal of the power switch, and a second pole of the field effect transistor serves as a second terminal of the power switch.
Specifically, the amplifier comprises a first P-type field effect transistor and a second P-type field effect transistor;
the first pole of the first P-type field effect transistor and the first pole of the second P-type field effect transistor are both connected with the first power supply signal, and the grid electrode of the first P-type field effect transistor is electrically connected with the grid electrode of the second P-type field effect transistor and serves as a compensation signal input end of the amplifier.
Specifically, the amplifier further includes a first N-type field effect transistor, a second N-type field effect transistor, and a current source, where a first pole of the first N-type field effect transistor is electrically connected to a second pole of the first P-type field effect transistor, a first pole of the second N-type field effect transistor is electrically connected to a second pole of the second P-type field effect transistor, a gate of the first N-type field effect transistor is used as the inverting input terminal of the amplifier, a gate of the second N-type field effect transistor is used as the non-inverting input terminal of the amplifier, both the second pole of the first N-type field effect transistor and the second pole of the second N-type field effect transistor are electrically connected to the first pole of the current source, and the second pole of the current source is connected to the second power signal; or,
the amplifier further comprises m stages of N-type field effect tube groups and a current source, wherein each stage of N-type field effect tube group comprises a first N-type field effect tube and a second N-type field effect tube, the grid electrode of the first N-type field effect tube in the former m-1 stage of N-type field effect tube group is electrically connected with the grid electrode of the second N-type field effect tube in the same N-type field effect tube group, the first pole of the first N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the first P-type field effect tube, the first pole of the second N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the second P-type field effect tube, the second pole of the first N-type field effect tube in the ith stage of N-type field effect tube group is electrically connected with the first pole of the first N-type field effect tube in the ith +1 stage of N-type field effect tube, a second pole of the second N-type field effect transistor in the i-th stage N-type field effect transistor group is electrically connected to a first pole of the second N-type field effect transistor in the i + 1-th stage N-type field effect transistor group, a gate of the first N-type field effect transistor in the m-th stage N-type field effect transistor group serves as the inverting input terminal of the amplifier, a gate of the second N-type field effect transistor in the m-th stage N-type field effect transistor group serves as the non-inverting input terminal of the amplifier, a second pole of the first N-type field effect transistor and a second pole of the second N-type field effect transistor in the m-th stage N-type field effect transistor group are both electrically connected to a first pole of the current source, and the second pole of the current source is connected to the second power signal; wherein i is a positive integer.
Specifically, the amplifier comprises n stages of P-type field effect transistor groups, each stage of P-type field effect transistor group comprises a first P-type field effect transistor and a second P-type field effect transistor, the grid electrode of all the first P-type field effect transistors is electrically connected with the grid electrode of all the second P-type field effect transistors to serve as the compensation signal input end of the amplifier, the first pole of the first P-type field effect transistor and the first pole of the second P-type field effect transistor of the first stage of P-type field effect transistor group are both connected with the first power supply signal, the second pole of the first P-type field effect transistor in the i-th stage of P-type field effect transistor group is electrically connected with the first pole of the first P-type field effect transistor in the i + 1-th stage of P-type field effect transistor group, the second pole of the second P-type field effect transistor in the ith-stage P-type field effect transistor group is electrically connected with the first pole of the second P-type field effect transistor in the (i + 1) th-stage P-type field effect transistor group.
Specifically, the amplifier further includes a first N-type field effect transistor, a second N-type field effect transistor, and a current source, a first pole of the first N-type field effect transistor is electrically connected to a second pole of the first P-type field effect transistor in the nth stage P-type field effect transistor group, a first pole of the second N-type field effect transistor is electrically connected to a second pole of the second P-type field effect transistor in the nth stage P-type field effect transistor group, a gate of the first N-type field effect transistor serves as the inverting input terminal of the amplifier, a gate of the second N-type field effect transistor serves as the non-inverting input terminal of the amplifier, a second pole of the first N-type field effect transistor and a second pole of the second N-type field effect transistor are both electrically connected to a first pole of the current source, and a second pole of the current source is connected to the second power signal; or,
the amplifier further comprises m stages of N-type field effect tube groups and a current source, wherein each stage of N-type field effect tube group comprises a first N-type field effect tube and a second N-type field effect tube, the grid electrode of the first N-type field effect tube in the previous m-1 stage of N-type field effect tube group is electrically connected with the grid electrode of the second N-type field effect tube in the same N-type field effect tube group, the first pole of the first N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the first P-type field effect tube in the N-type field effect tube group, the first pole of the second N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the second P-type field effect tube in the N-type field effect tube group, the second pole of the first N-type field effect tube in the i-stage of N-type field effect tube group is electrically connected with the second pole of the second P-type field effect tube in the i +1 stage of N A first pole of the effect tube is electrically connected, a second pole of the second N-type field effect tube in the i +1 th N-type field effect tube group is electrically connected with a first pole of the second N-type field effect tube in the i +1 th N-type field effect tube group, a gate of the first N-type field effect tube in the m-th N-type field effect tube group is used as the reverse input end of the amplifier, a gate of the second N-type field effect tube in the m-th N-type field effect tube group is used as the same-direction input end of the amplifier, a second pole of the first N-type field effect tube and a second pole of the second N-type field effect tube in the m-th N-type field effect tube group are both electrically connected with a first pole of the current source, and the second pole of the current source is connected to the second power signal; wherein n is an integer greater than 1, and i is a positive integer.
The embodiment of the invention provides a low dropout regulator, which utilizes a second compensation element to form a passage between a first power supply signal and a second power supply signal, wherein the passage can reduce the change of an output signal of an amplified signal output end caused by the change of the first power supply signal and the second power supply signal and reduce the influence of the change of the first power supply signal and the second power supply signal on the control end voltage of a power switch, a power element can adjust the output signal of a second end according to an input signal of the control end, further reduce the influence of the change of the first power supply signal and the second power supply signal on a voltage stabilizing signal output by the second end of the power switch, namely a voltage stabilizing signal output end, and improve the power supply voltage suppression ratio at the intermediate frequency of the low dropout regulator while realizing the voltage stabilizing function of the low dropout regulator, and utilizes the second compensation element to realize the improvement of the power supply voltage suppression ratio at the intermediate frequency of the low dropout regulator, the power supply voltage rejection ratio of the low dropout linear regulator at the intermediate frequency is not improved by improving the GBW, the problems of large power consumption and low efficiency of the low dropout linear regulator caused by improving the GBW are avoided, and the power consumption of the low dropout linear regulator is reduced.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a prior art low dropout linear regulator;
fig. 2 is a schematic structural diagram of a low dropout regulator according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention;
fig. 7 is a diagram illustrating the effect of the power supply voltage rejection ratio of the low dropout regulator according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures. Throughout this specification, the same or similar reference numbers refer to the same or similar structures, elements, or processes. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The embodiment of the invention provides a low dropout regulator, which comprises an amplifier, a power switch, a voltage division circuit, a first compensation element and a second compensation element, wherein the amplifier comprises a homodromous input end, a reverse input end, a compensation signal input end and an amplification signal output end, the power switch comprises a control end, a first end and a second end, and the voltage division circuit comprises a first voltage division signal input end, a second voltage division signal input end and a voltage division signal output end. The reverse input end is connected with a reference signal, the control end is electrically connected with the amplified signal output end, the first end is connected with a first power supply signal, the second end is used as a voltage stabilization signal output end of the low dropout linear voltage regulator, the first voltage division signal input end is electrically connected with the second end, the second voltage division signal input end is connected with a second power supply signal, the voltage division signal output end is electrically connected with the homodromous input end, the first pole of the second compensation element is electrically connected with the compensation signal input end, and the second pole of the second compensation element is electrically connected with the second voltage division signal input end. The amplifier is used for adjusting an output signal of the amplified signal output end according to input signals of the equidirectional input end, the reverse input end and the compensation input end, the power element is used for adjusting an output signal of the second end according to an input signal of the control end, the voltage division circuit is used for dividing the voltage of the input signals of the first voltage division signal input end and the second voltage division signal input end to form a voltage division signal and outputting the voltage division signal through the voltage division signal output end, the first power supply signal passes through a passage formed between the second compensation element and the second power supply signal, and the passage enables the change of the output signal of the amplified signal output end caused by the change of the first power supply signal and the second power supply.
In order to prolong the standby time, improve the integration level and reduce the complexity of peripheral circuits, the SOC currently adopts a power supply architecture combining a DC/DC converter and an LDO, for example, both the DC/DC converter and the LDO can be directly integrated in the SOC. Because the DC/DC is driven by the clock, the output ripple is large at the working clock frequency, and the PLL, the ADC, the LNA and the like are sensitive to power supply parameters, which puts high requirements on the power supply voltage rejection ratio index of the LDO in the chip. However, the supply voltage rejection ratio of a common LDO without off-chip capacitance is poor at the intermediate frequency, and the operating clock frequency of DC/DC is substantially at the intermediate frequency of the LDO.
Fig. 1 is a schematic diagram of a low dropout regulator in the prior art. As shown in fig. 1, when the LDO operates in the middle frequency band, that is, the operating frequency F of the LDO is greater than P0 and less than GBW, the supply voltage rejection ratio PSRR of the LDO satisfies the following formula:
wherein gm1 is transconductance of the first transistor T1, Ro1 is parallel equivalent impedance of the output impedance of the first transistor T1 and the output impedance of the fifth transistor T5, gm3 is output transconductance of the third transistor T3, Ro3 is output impedance of the third transistor T3, β is feedback coefficient and is equal toS is the frequency domain, P0 is the dominant pole of the LDO, i.e., P0 is equal to the-3 dB bandwidth of the open loop gain, and GBW is the unity gain-bandwidth product of the LDO. Referring to the above formula, the GBW of the LDO can be increased to increase the power supply rejection ratio at the intermediate frequency, but increasing the GBW of the LDO increases the transconductance of the LDO, and the increase of the transconductanceIn addition, the current flowing through the LDO is increased, so that the power consumption of the LDO is increased, and the efficiency is reduced.
The low dropout regulator according to the embodiment of the present invention utilizes two compensation components to form a path between a first power signal and a second power signal, the path can reduce the variation of an output signal at an amplified signal output end caused by the variation of the first power signal and the second power signal, and reduce the influence of the variation of the first power signal and the second power signal on the control end voltage of a power switch, the power component can adjust the output signal at a second end according to the input signal at the control end, so as to reduce the influence of the variation of the first power signal and the second power signal on a regulated voltage signal output by a second end of the power switch, i.e. a regulated voltage signal output end, and the low dropout regulator realizes the voltage regulation function and simultaneously improves the power supply voltage rejection ratio at the intermediate frequency of the low dropout regulator, and the embodiment of the present invention utilizes the second compensation component to realize the improvement of the power supply voltage rejection ratio at the intermediate frequency of the low dropout regulator, the power supply voltage rejection ratio of the low dropout linear regulator at the intermediate frequency is not improved by improving the GBW, so that the problems of large power consumption and low efficiency of the low dropout linear regulator caused by improving the GBW are solved, and the power consumption of the low dropout linear regulator is reduced.
Fig. 2 is a schematic structural diagram of a low dropout regulator according to an embodiment of the present invention. As shown in fig. 2, the low dropout linear regulator includes an amplifier 1, a power switch 2, a voltage dividing circuit 3 and a second compensation element 5, wherein the amplifier 1 includes a same-direction input terminal a1, a reverse-direction input terminal a2, a compensation signal input terminal A3 and an amplification signal output terminal a4, the power switch 2 includes a control terminal B1, a first terminal B2 and a second terminal B3, and the voltage dividing circuit 3 includes a first voltage dividing signal input terminal D1, a second voltage dividing signal input terminal D2 and a voltage dividing signal output terminal D3.
The inverting input terminal a2 is connected to a reference signal VREF, the control terminal B1 is electrically connected to the amplified signal output terminal a4, the first terminal B2 is connected to a first power signal VDD, the second terminal B3 is used as a voltage stabilization signal output terminal VOUT of the low dropout linear regulator, the first voltage division signal input terminal D1 is electrically connected to the second terminal B3, the second voltage division signal input terminal D2 is connected to a second power signal GND, the voltage division signal output terminal D3 is electrically connected to the equidirectional input terminal a1, the first pole F1 of the second compensation element 5 is electrically connected to the compensation signal input terminal A3, and the second pole F2 of the second compensation element 5 is electrically connected to the second voltage division signal input terminal D2.
The amplifier 1 is configured to adjust an output signal of the amplified signal output terminal a4 according to input signals of the equidirectional input terminal a1, the inverse input terminal a2 and the compensation signal input terminal A3, the power switch 2 is configured to adjust an output signal of the second terminal B3 according to an input signal of the control terminal B1, and the voltage divider circuit 3 is configured to divide input signals of the first voltage divider signal input terminal D1 and the second voltage divider signal input terminal D2 into a divided voltage signal and output the divided voltage signal through the voltage divider signal output terminal D3. Specifically, as shown in fig. 2, when the voltage of the regulated signal output terminal VOUT of the low dropout linear regulator increases, the voltage of the divided signal fed back to the equidirectional input terminal a1 of the amplifier 1 by the voltage dividing circuit 3 increases, and the voltage of the signal output from the amplified signal output terminal a4 of the amplifier 1 increases. The power switch 2 is exemplarily configured as a P-type transistor, and the increase of the gate voltage of the power switch 2 increases the voltage difference between the source and the drain of the power switch 2, so that the voltage difference between the source and the drain of the power switch 2 increases the voltage of the regulated signal output by the regulated signal output terminal VOUT of the low dropout linear regulator. Similarly, when the voltage of the voltage-stabilizing signal output by the voltage-stabilizing signal output terminal VOUT of the low dropout linear regulator decreases, the feedback of the voltage-dividing circuit 3 and the control of the power switch 2 increase the voltage of the voltage-stabilizing signal output by the voltage-stabilizing signal output terminal VOUT of the low dropout linear regulator, and the low dropout linear regulator accordingly realizes the voltage-stabilizing function.
As shown in fig. 2, the first power signal VDD passes through the second compensation element 5 to form a path between the second power signal GND and the first power signal VDD, the path reduces the variation of the output signal of the amplified signal output terminal a4 caused by the variation of the first power signal VDD and the second power signal GND, and reduces the influence of the variation of the first power signal VDD and the second power signal GND on the voltage of the control terminal B1 of the power switch 2, the power switch 2 can adjust the output signal of the second terminal B3 according to the input signal of the control terminal B1, and further reduces the influence of the variation of the first power signal VDD and the second power signal GND on the second terminal B3 of the power switch 2, that is, the regulated signal output by the regulated signal output terminal VOUT, and increases the power voltage rejection ratio at the intermediate frequency of the low dropout linear regulator, and the embodiment of the present invention uses the second compensation element 5 to achieve the increase of the power voltage rejection ratio at the intermediate frequency of the low dropout linear regulator, the power supply voltage rejection ratio of the low dropout linear regulator at the intermediate frequency is not improved by improving the GBW, so that the problems of large power consumption and low efficiency of the low dropout linear regulator caused by improving the GBW are solved, and the power consumption of the low dropout linear regulator is reduced.
Fig. 3 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention. With reference to fig. 2 and 3, the voltage divider circuit 3 may include a second impedance element 31 and a third impedance element 32, a first pole G1 of the second impedance element 31 serves as a first voltage dividing signal input terminal D1 of the voltage divider circuit 3, a second pole G2 of the second impedance element 31 is electrically connected to a first pole H1 of the third impedance element 32 as a voltage dividing signal output terminal D3 of the voltage divider circuit 3, and a second pole H2 of the third impedance element 32 serves as a second voltage dividing signal input terminal D2 of the voltage divider circuit 3. Specifically, after the second impedance element 31 and the third impedance element 32 in the voltage dividing circuit 3 divide the voltage of the regulated signal output terminal VOUT of the low dropout linear regulator, the divided signal is transmitted to the equidirectional input terminal a1 of the amplifier 1 through the divided signal output terminal D3. Fig. 3 only exemplarily sets the voltage dividing circuit 3 to include two impedance elements, the voltage dividing circuit 3 may also include more impedance elements, the number of the impedance elements in the voltage dividing circuit 3 and the size of the impedance elements may be specifically set according to the voltage dividing requirement, and RL and CL in fig. 3 are both loads.
Fig. 3 is a specific circuit diagram equivalent to fig. 2. With reference to fig. 2 and 3, the power switch 2 may include a fet, a gate d1 of the fet serving as the control terminal B1 of the power switch 2, a first pole d2 of the fet serving as the first terminal B2 of the power switch 2, and a second pole d3 of the fet serving as the second terminal B3 of the power switch 2. Fig. 2 and fig. 3 exemplarily set the power switch 2 as a P-type transistor, and the embodiment of the present invention does not limit the type of the transistor in the power switch 2.
With reference to fig. 2 and fig. 3, the amplifier 1 may include a first P-type fet 11, a second P-type fet 12, a first N-type fet 13, a second N-type fet 14, and a current source 15, wherein a first pole K2 of the first P-type fet 11 and a first pole L2 of the second P-type fet 12 are both connected to the first power signal VDD, and a gate K1 of the first P-type fet 11 and a gate L1 of the second P-type fet 12 are electrically connected to serve as a compensation signal input terminal A3 of the amplifier 1. The first pole M2 of the first N-type fet 13 is electrically connected to the second pole K3 of the first P-type fet 11, the first pole Q2 of the second N-type fet 14 is electrically connected to the second pole L3 of the second P-type fet 12, the gate M1 of the first N-type fet 13 is used as the inverting input a2 of the amplifier 1, the gate Q1 of the second N-type fet 14 is used as the inverting input a1 of the amplifier 1, the second pole M3 of the first N-type fet 13 and the second pole Q3 of the second N-type fet 14 are both electrically connected to the first pole T1 of the current source 15, and the second pole T2 of the current source 15 is connected to the second power signal GND.
Optionally, with reference to fig. 2 and fig. 3, the low dropout linear regulator may further include a first impedance element 61 and a first compensation element 4, a first end W1 of the first impedance element 61 is electrically connected to the control end B1 of the power switch 2, a second end W2 of the first impedance element 61 is electrically connected to the first pole E1 of the first compensation element 4, and the second pole E2 of the first compensation element 4 is electrically connected to the second end B3 of the power switch 2. The first compensation element 4 and the second compensation element 5 may each comprise a compensation capacitance.
With reference to fig. 2 and fig. 3, the first P-type fet 11, the second P-type fet 12, the first N-type fet 13, the second N-type fet 14, and the current source 15 form a cascode amplifier 1, and when the LDO operates in a middle frequency band, that is, when the operating frequency F of the LDO is greater than P0 and less than GBW, the supply voltage rejection ratio PSRR of the LDO satisfies the following formula:
wherein gm1 is the transconductance of the first N-type fet 13, the resistance of the second impedance element 31 is R1, the resistance of the third impedance element 32 is R2, β is the feedback coefficient and is equal toS is the frequency domain, P0 is the dominant pole of LDO, C2 is the capacitance of the second compensation element 5, Ct is the sum of the capacitance of the first compensation element 4 and the parasitic capacitance of the power switch 2.
Referring to fig. 2 and 3, the first power signal VDD may be a positive power voltage signal, the second power signal GND may be a ground signal, the second compensation element 5 is configured to increase a path L1 from the first power signal VDD to the second power signal GND, when the first power signal VDD or the second power signal GND changes, the second compensation element 5 is configured to reduce an influence of the change of the first power signal VDD or the second power signal GND on a voltage of a gate K1 of the first P-type fet 11, the gate K1 of the first P-type fet 11 is shorted with a gate L1 of the second P-type fet 12, so that an influence of the change of the first power signal VDD or the second power signal GND on a voltage of a second pole L3 of the second P-type fet 12 is reduced, and an influence of the change of the first power signal VDD or the second power signal on a control terminal B1, i.e., a gate d1 of the power switch 2 is reduced, and then reduced the influence of the change of first power signal VDD or second power signal GND to the second end B3 of power switch 2, namely the steady voltage signal voltage that steady voltage signal output terminal VOUT output, when having improved the mains voltage rejection ratio of LDO at GBW intermediate frequency department, avoided improving the low dropout linear regulator's GBW in order to improve its power supply voltage rejection ratio at intermediate frequency department and leaded to the problem of the low dropout linear regulator's consumption increase, efficiency reduction.
In addition, a filter circuit consisting of a variable transconductance stage gm, a resistor and a capacitor and a variable current high-gain amplification stage can be introduced at present, and the low-frequency zero is utilized to offset the reduction of the power supply voltage rejection ratio caused by the low-frequency pole so as to enhance the power supply voltage rejection ratio of the LDO in the middle frequency band; the auxiliary amplifier 1 can also be adopted to improve the power supply voltage rejection ratio of the LDO middle frequency band while not changing the pole of the LDO main loop and generating the zero point. However, the two schemes have complicated structures and increase the manufacturing cost of the LDO, and the low dropout regulator provided by the embodiment of the invention utilizes the second compensation element 5, thereby improving the supply voltage rejection ratio of the LDO, simplifying the structure of the LDO and reducing the manufacturing cost of the LDO.
In combination with the above formula, the second compensation element 5 effectively compensates the influence of the parasitic capacitance of the first compensation element 4 and the power switch 2, and the power supply voltage rejection ratio of the LDO can be significantly improved by selecting the appropriate second compensation element 5. Specifically, the supply voltage rejection ratio of the LDO is negative, and the supply voltage rejection ratio of the LDO can be increased by increasing the capacitance value of the second compensation element 5, for example, making the capacitance value of the second compensation element 5 approximately equal to the sum of the capacitance value of the first compensation element 4 and the parasitic capacitance of the power switch 2.
Fig. 4 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention. Unlike the low dropout regulator having the configuration shown in fig. 3, the amplifier 1 in the low dropout regulator having the configuration shown in fig. 4 includes M stages of N-type field effect transistor groups 100, and in conjunction with fig. 2 and 4, each stage of N-type field effect transistor group 100 includes a first N-type field effect transistor 13 and a second N-type field effect transistor 14, a gate M1 of the first N-type field effect transistor 13 in the first M-1 stage of N-type field effect transistor group 100 is electrically connected to a gate Q1 of the second N-type field effect transistor 14 in the same N-type field effect transistor group 100, a first pole M2 of the first N-type field effect transistor 13 in the first stage of N-type field effect transistor group 100 is electrically connected to a second pole K3 of the first P-type field effect transistor 11, a first pole Q2 of the second N-type field effect transistor 14 in the first stage of N-type field effect transistor group 100 is electrically connected to a second pole L3 of the second P-type field effect transistor 12, a first pole M3 of the first N-type field effect transistor 13 in the i-stage of N-type field effect transistor group 100 A first pole M2 of the first N-type fet 13 is electrically connected, a second pole Q3 of the second N-type fet 14 in the i +1 th stage N-type fet group 100 is electrically connected to a first pole Q2 of the second N-type fet 14 in the i +1 th stage N-type fet group 100, a gate M1 of the first N-type fet 13 in the M-th stage N-type fet group 100 is used as a reverse input a2 of the amplifier 1, a gate Q1 of the second N-type fet 14 in the M-th stage N-type fet group 100 is used as a same-direction input a1 of the amplifier 1, a second pole M3 of the first N-type fet 13 in the M-th stage N-type fet group 100 and a second pole Q3 of the second N-type fet 14 are both electrically connected to a first pole T1 of the current source 15, and a second pole T2 of the current source 15 is connected to a second power supply signal GND; wherein i is a positive integer.
Fig. 4 exemplarily sets M equal to 2, that is, the amplifier 1 includes two stages of N-type field effect transistor groups 100, the gate M1 of the first N-type field effect transistor 13 in the first stage of N-type field effect transistor group 100 is electrically connected to the gate Q1 of the second N-type field effect transistor 14 in the first stage of N-type field effect transistor group 100, the second pole M3 of the first N-type field effect transistor 13 in the first stage of N-type field effect transistor group 100 is electrically connected to the first pole M2 of the first N-type field effect transistor 13 in the second stage of N-type field effect transistor group 100, the second pole Q3 of the second N-type field effect transistor 14 in the first stage of N-type field effect transistor group 100 is electrically connected to the first pole Q2 of the second N-type field effect transistor 14 in the second stage of N-type field effect transistor group 100, the gate M5639 of the first N-type field effect transistor 13 in the second stage of N-type field effect transistor group 100 is used as the inverting input terminal 2 of the amplifier 1, and the gate Q1 of the second N-type field effect transistor group 100 is used The second pole M3 of the first N-type fet 13 and the second pole Q3 of the second N-type fet 14 in the second stage N-type fet group 100 are both electrically connected to the first pole T1 of the current source 15, and the second pole T2 of the current source 15 is connected to the second power signal GND.
Fig. 5 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention. Referring to fig. 2 and 5, the amplifier 1 includes N-stage P-type fet groups 200, first N-type fets 13, second N-type fets 14 and a current source 15, each of the P-type fet groups 200 includes first P-type fets 11 and second P-type fets 12, gates K1 of all the first P-type fets 11 and L1 of all the second P-type fets 12 are electrically connected as a compensation signal input A3 of the amplifier 1, a first pole K2 of the first P-type fets 11 and a first pole L2 of the second P-type fets 12 of the first P-type fet group 200 are both connected to a first power signal VDD, a second pole K3 of the first P-type fets 11 of the i-stage P-type fet group 200 and a first pole K2 of the first P-type fets 11 of the i + 1-stage P-type fet group 200 are electrically connected, and a second pole K2 of the second P-type fets 12 of the i-stage P-type fets 200 and L3 of the i + 1-stage P-type fets group 200 are electrically connected to a second pole L3 of the i + 1-stage P-type fets group 200 The first poles L2 of the two PFETs 12 are electrically connected. A first pole M2 of the first N-type fet 13 is electrically connected to a second pole K3 of the first P-type fet 11 in the nth stage P-type fet group 200, a first pole Q2 of the second N-type fet 14 is electrically connected to a second pole L3 of the second P-type fet 12 in the nth stage P-type fet group 200, a gate M1 of the first N-type fet 13 is used as an inverting input a2 of the amplifier 11, a gate Q1 of the second N-type fet 14 is used as a non-inverting input a1 of the amplifier 11, both the second pole M3 of the first N-type fet 13 and the second pole Q3 of the second N-type fet 14 are electrically connected to a first pole T1 of the current source 15, and a second pole T2 of the current source 15 is connected to the second power supply signal GND. Similarly, the second compensation element 5 increases the path L1 from the first power supply signal VDD to the second power supply signal GND, reduces the influence of the variation of the first power supply signal VDD or the second power supply signal GND on the voltage of the regulated signal output from the regulated signal output terminal VOUT, and improves the supply voltage rejection ratio of the LDO at the intermediate frequency of GBW.
Fig. 5 exemplarily sets n equal to 2, that is, the amplifier 11 includes a two-stage P-type fet group 200, the gates K1 of two first P-type fets 11 and the gates L1 of two second P-type fets 12 are electrically connected as the compensation signal input terminal A3 of the amplifier 11, the second pole K3 of the first P-type fet 11 in the first-stage P-type fet group 200 is electrically connected to the first pole K2 of the first P-type fet 11 in the second-stage P-type fet group 200, and the second pole L3 of the second P-type fet 12 in the first-stage P-type fet group 200 is electrically connected to the first pole L2 of the second P-type fet 12 in the second-stage P-type fet group 200. The first pole M2 of the first N fet 13 is electrically connected to the second pole K3 of the first P fet 11 in the second P fet group 200, and the first pole Q2 of the second N fet 14 is electrically connected to the second pole L3 of the second P fet 12 in the second P fet group 200. Similarly, the second compensation element 5 increases the path L1 from the first power supply signal VDD to the second power supply signal GND, reduces the influence of the variation of the first power supply signal VDD or the second power supply signal GND on the voltage of the regulated signal output from the regulated signal output terminal VOUT, and improves the supply voltage rejection ratio of the LDO at the intermediate frequency of GBW.
Fig. 6 is a schematic structural diagram of another low dropout regulator according to an embodiment of the present invention. Unlike the low dropout regulator having the configuration shown in fig. 5, the amplifier 1 in the low dropout regulator having the configuration shown in fig. 6 includes M stages of N-type field effect transistor groups 100, and, in conjunction with fig. 2 and 6, the amplifier 1 includes M stages of N-type field effect transistor groups 100 and a current source 15, each stage of N-type field effect transistor group 100 includes a first N-type field effect transistor 13 and a second N-type field effect transistor 14, the gate M1 of the first N-type field effect transistor 13 in the first M-1 stage of N-type field effect transistor group 100 is electrically connected to the gate Q1 of the second N-type field effect transistor 14 in the same N-type field effect transistor group 100, the first pole M2 of the first N-type field effect transistor 13 in the first stage of N-type field effect transistor group 100 is electrically connected to the second pole K3 of the first P-type field effect transistor 11 in the N-stage of P-type field effect transistor group 200, the first pole Q2 of the second N-type field effect transistor 14 in the first stage of N-type field effect transistor group 100 is electrically connected to the second P-type Pole L3 is electrically connected, second pole M3 of first N-type field effect transistor 13 in i-th stage N-type field effect transistor group 100 is electrically connected to first pole M2 of first N-type field effect transistor 13 in i + 1-th stage N-type field effect transistor group 100, second pole Q3 of second N-type field effect transistor 14 in i-th stage N-type field effect transistor group 100 is electrically connected to first pole Q2 of second N-type field effect transistor 14 in i + 1-th stage N-type field effect transistor group 100, gate M1 of first N-type field effect transistor 13 in M-th stage N-type field effect transistor group 100 is used as inverting input terminal a2 of amplifier 1, gate Q1 of second N-type field effect transistor 14 in M-th stage N-type field effect transistor group 100 is used as inverting input terminal a1 of amplifier 1, second pole M3 of first N-type field effect transistor 13 and second pole Q3 of second N-type field effect transistor 14 in M-th stage N-type field effect transistor group 100 are both electrically connected to first pole T1, a second pole T2 of the current source 15 is connected to the second power supply signal GND; wherein n is an integer greater than 1, and i is a positive integer.
Fig. 6 exemplarily sets M equal to 2, that is, the amplifier 1 includes two stages of N-type fet groups 100, the gate M1 of the first N-type fet 13 in the first stage of N-type fet group 100 is electrically connected to the gate Q1 of the second N-type fet 14 in the same N-type fet group 100, the first pole M2 of the first N-type fet 13 in the first stage of N-type fet group 100 is electrically connected to the second pole K3 of the first P-type fet 11 in the second stage of P-type fet group 200, the first pole Q2 of the second N-type fet 14 in the first stage of N-type fet group 100 is electrically connected to the second pole L3 of the second P-type fet 12 in the second stage of P-type fet group 200, the second pole M3 of the first N-type fet 13 in the first stage of N-type fet group 100 is electrically connected to the first pole M2 of the first N-type fet 13 in the second stage of N-type fet group 100, the second pole Q3 of the second N-type fet 14 in the first stage N-type fet group 100 is electrically connected to the first pole Q2 of the second N-type fet 14 in the second stage N-type fet group 100, the gate M1 of the first N-type fet 13 in the second stage N-type fet group 100 is used as the inverting input terminal a2 of the amplifier 1, the gate Q1 of the second N-type fet 14 in the second stage N-type fet group 100 is used as the inverting input terminal a1 of the amplifier 1, the second pole M3 of the first N-type fet 13 in the second stage N-type fet group 100 and the second pole Q3 of the second N-type fet 14 are both electrically connected to the first pole T1 of the current source 15, and the second pole T2 of the current source 15 is connected to the second power supply signal GND. Similarly, the second compensation element 5 increases the path L1 from the first power supply signal VDD to the second power supply signal GND, reduces the influence of the variation of the first power supply signal VDD or the second power supply signal GND on the voltage of the regulated signal output from the regulated signal output terminal VOUT, and improves the supply voltage rejection ratio of the LDO at the intermediate frequency of GBW.
For example, the amplifiers in the low dropout linear regulator shown in fig. 3 to 6 are all telescopic cascode amplifiers, so that the low dropout linear regulator obtains a larger gain at a low frequency. The amplifier in the low dropout regulator may also be a folded cascode amplifier, which can also make the low dropout regulator obtain a larger gain at a low frequency.
Referring to fig. 2 to 6, the first impedance element 61 may cancel the zero point generated by the first compensation element 4 as a zero point canceling resistance. Specifically, the frequency domain includes a right Half plane RHP (right hall plane) zero point and a left Half plane lhp (left hall plane) zero point, and the first impedance element 61 is arranged such that the RHP zero point z1 satisfies the following calculation formula:
where C1 is the capacitance of the first compensation element 4, R is the resistance of the first impedance element 61, and gm is the equivalent transconductance of the amplifier 1. To eliminate the RHP zero point, R may be set equal toPushing this RHP zero point to infinity, the effect is completely negligible.
When R is greater thanWhen the property of the zero point is changed from the RHP zero point to the LHP zero point, the first impedance element 61 is set so that the LHP zero point z2 satisfies the following calculation formula:
referring to the above equation, another compensation strategy is to increase the resistance R of the first impedance element 61 so that the feedback zero becomes a stable LHP zero and is located at least at 2GBW, and when the LHP zero is close to the pole, the effect of the pole is eliminated.
Referring to fig. 2 to 6, it may be provided that the second compensation element 5 includes a plurality of second compensation capacitors 51, the first poles F11 of all the second compensation capacitors 51 are electrically connected as the first poles F1 of the second compensation element 5, the second poles F21 of all the second compensation capacitors 51 are electrically connected as the second poles F2 of the second compensation element 5, and at least a part of the second compensation capacitors 51 are provided as transistor capacitors. Fig. 2 to 6 exemplarily set the second compensation element 5 to include two second compensation capacitors 51, one second compensation capacitor 51 may be a fixed MOM capacitor, i.e., a capacitor between edges of the same metal layer or an MIM capacitor, i.e., an interlayer capacitor between different metal layers, and the other second compensation capacitor 51 may be a variable transistor capacitor, i.e., a MOS capacitor. Specifically, reference is made to the following formula:
ct is the sum of the capacitance of the first compensation element 4 and the parasitic capacitance of the power switch 2, C2 is the capacitance of the second compensation element 5, the parasitic capacitance of the power switch 2 is the voltage between the gate and the source of the power switch 2, and the gate-source voltage of the fet changes with the temperature. In order to increase the PSRR of the LDO, Ct should be as close as possible to C2, so the second compensation element 5 includes at least one MOS capacitor, that is, the capacitance of the second compensation element 5 also changes with the temperature, which is beneficial to increase the PSRR of the LDO.
Fig. 7 is a diagram illustrating the effect of the power supply voltage rejection ratio of the low dropout regulator according to the embodiment of the present invention. Fig. 7 shows a curve a showing the effect of the power supply rejection ratio of the low dropout regulator in the prior art shown in fig. 1, a curve B showing the effect of the power supply rejection ratio of the low dropout regulator including a second compensation element, wherein an abscissa shows frequency and an ordinate shows the power supply rejection ratio, and as can be seen from fig. 7, the second compensation element is arranged to improve the power supply rejection ratio of the LDO in the middle frequency band by more than 30 dB.
The low dropout regulator provided by the embodiment of the invention utilizes the second compensation element to form a path between the first power signal and the second power signal, the path can reduce the change of the output signal of the amplified signal output end caused by the change of the first power signal and the second power signal, and reduce the influence of the change of the first power signal and the second power signal on the control end voltage of the power switch, the power element can adjust the output signal of the second end according to the input signal of the control end, so as to reduce the influence of the change of the first power signal and the second power signal on the voltage stabilizing signal output by the second end of the power switch, namely the voltage stabilizing signal output end, and the power voltage suppression ratio at the intermediate frequency of the low dropout regulator is improved while the voltage stabilizing function of the low dropout regulator is realized, and the embodiment of the invention utilizes the second compensation element to realize the improvement of the power voltage suppression ratio at the intermediate frequency of the low dropout regulator, the power supply voltage rejection ratio of the low dropout linear regulator at the intermediate frequency is not improved by improving the GBW, the problems of large power consumption and low efficiency of the low dropout linear regulator caused by improving the GBW are avoided, and the power consumption of the low dropout linear regulator is reduced.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A low dropout linear regulator, comprising:
the amplifier comprises a same-direction input end, an inverse input end, a compensation signal input end and an amplification signal output end, wherein the inverse input end is connected with a reference signal, and the amplifier is used for adjusting an output signal of the amplification signal output end according to input signals of the same-direction input end, the inverse input end and the compensation signal input end;
the power switch comprises a control end, a first end and a second end, the control end is electrically connected with the amplified signal output end, the first end is connected to a first power signal, the second end is used as a voltage-stabilizing signal output end of the low dropout linear regulator, and the power switch is used for adjusting an output signal of the second end according to an input signal of the control end;
the voltage dividing circuit comprises a first voltage dividing signal input end, a second voltage dividing signal input end and a voltage dividing signal output end, the first voltage dividing signal input end is electrically connected with the second end, the second voltage dividing signal input end is connected with a second power signal, the voltage dividing signal output end is electrically connected with the homodromous input end, and the voltage dividing circuit is used for dividing the voltage of input signals of the first voltage dividing signal input end and the second voltage dividing signal input end to form a voltage dividing signal and outputting the voltage dividing signal through the voltage dividing signal output end;
a second compensation element, a first pole of the second compensation element being electrically connected to the compensation signal input terminal, a second pole of the second compensation element being electrically connected to the second divided signal input terminal, the first power signal passing through a path formed between the second compensation element and the second power signal, the path reducing a change in an output signal of the amplified signal output terminal caused by a change in the first power signal and the second power signal.
2. The low dropout regulator of claim 1, further comprising:
the first end of the first impedance element is electrically connected with the control end of the power switch, the second end of the first impedance element is electrically connected with the first pole of the first compensation element, and the second pole of the first compensation element is electrically connected with the second end of the power switch.
3. The low dropout regulator of claim 2 wherein the first compensation element and the second compensation element each comprise a compensation capacitor.
4. The low dropout regulator of claim 3 wherein said second compensation element comprises a plurality of second compensation capacitors, a first pole of all of said second compensation capacitors electrically connected as said first pole of said second compensation element, a second pole of all of said second compensation capacitors electrically connected as said second pole of said second compensation element, at least a portion of said second compensation capacitors being transistor capacitors.
5. The low dropout regulator of claim 1 wherein the voltage divider circuit comprises:
and a second impedance element and a third impedance element, wherein a first pole of the second impedance element is used as a first voltage division signal input end of the voltage division circuit, a second pole of the second impedance element is electrically connected with a first pole of the third impedance element to be used as a voltage division signal output end of the voltage division circuit, and a second pole of the third impedance element is used as a second voltage division signal input end of the voltage division circuit.
6. The LDO of claim 1, wherein the power switch comprises a FET, a gate of the FET serving as the control terminal of the power switch, a first pole of the FET serving as the first terminal of the power switch, and a second pole of the FET serving as the second terminal of the power switch.
7. The low dropout regulator of any one of claims 1 to 6 wherein the amplifier comprises a first P-type field effect transistor and a second P-type field effect transistor;
the first pole of the first P-type field effect transistor and the first pole of the second P-type field effect transistor are both connected with the first power supply signal, and the grid electrode of the first P-type field effect transistor is electrically connected with the grid electrode of the second P-type field effect transistor and serves as a compensation signal input end of the amplifier.
8. The low dropout regulator according to claim 7,
the amplifier further comprises a first N-type field effect transistor, a second N-type field effect transistor and a current source, wherein a first pole of the first N-type field effect transistor is electrically connected with a second pole of the first P-type field effect transistor, a first pole of the second N-type field effect transistor is electrically connected with a second pole of the second P-type field effect transistor, a grid electrode of the first N-type field effect transistor is used as the reverse input end of the amplifier, a grid electrode of the second N-type field effect transistor is used as the same-direction input end of the amplifier, a second pole of the first N-type field effect transistor and a second pole of the second N-type field effect transistor are both electrically connected with a first pole of the current source, and a second pole of the current source is connected to the second power signal; or,
the amplifier further comprises m stages of N-type field effect tube groups and a current source, wherein each stage of N-type field effect tube group comprises a first N-type field effect tube and a second N-type field effect tube, the grid electrode of the first N-type field effect tube in the former m-1 stage of N-type field effect tube group is electrically connected with the grid electrode of the second N-type field effect tube in the same N-type field effect tube group, the first pole of the first N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the first P-type field effect tube, the first pole of the second N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the second P-type field effect tube, the second pole of the first N-type field effect tube in the ith stage of N-type field effect tube group is electrically connected with the first pole of the first N-type field effect tube in the ith +1 stage of N-type field effect tube, a second pole of the second N-type field effect transistor in the i-th stage N-type field effect transistor group is electrically connected to a first pole of the second N-type field effect transistor in the i + 1-th stage N-type field effect transistor group, a gate of the first N-type field effect transistor in the m-th stage N-type field effect transistor group serves as the inverting input terminal of the amplifier, a gate of the second N-type field effect transistor in the m-th stage N-type field effect transistor group serves as the non-inverting input terminal of the amplifier, a second pole of the first N-type field effect transistor and a second pole of the second N-type field effect transistor in the m-th stage N-type field effect transistor group are both electrically connected to a first pole of the current source, and the second pole of the current source is connected to the second power signal; wherein i is a positive integer.
9. The LDO of any of claims 1-6, wherein said amplifier comprises n stages of PFET groups, each stage of PFET group comprising a first PFET and a second PFET, the gate of all said first PFET and the gate of all said second PFET being electrically connected as said buck signal input of said amplifier, the first P FET of a first stage PFET group having its first pole and the first P FET of its second stage being connected to said first power signal, the second P FET of an i stage PFET group having its second pole electrically connected to the first P FET of an i +1 stage PFET group, the second P FET of an i stage PFET group having its second pole connected to said first P FET of an i +1 stage PFET group, the second P FET of an i stage PFET group having its second pole and said i +1 stage PFET group The first pole of the second P-type field effect transistor in the field effect transistor group is electrically connected.
10. The low dropout regulator according to claim 9,
the amplifier further comprises a first N-type field effect transistor, a second N-type field effect transistor and a current source, wherein a first pole of the first N-type field effect transistor is electrically connected with a second pole of the first P-type field effect transistor in the nth-stage P-type field effect transistor group, a first pole of the second N-type field effect transistor is electrically connected with a second pole of the second P-type field effect transistor in the nth-stage P-type field effect transistor group, a grid electrode of the first N-type field effect transistor serves as the reverse input end of the amplifier, a grid electrode of the second N-type field effect transistor serves as the same-direction input end of the amplifier, a second pole of the first N-type field effect transistor and a second pole of the second N-type field effect transistor are both electrically connected with a first pole of the current source, and a second pole of the current source is connected to the second power signal; or,
the amplifier further comprises m stages of N-type field effect tube groups and a current source, wherein each stage of N-type field effect tube group comprises a first N-type field effect tube and a second N-type field effect tube, the grid electrode of the first N-type field effect tube in the previous m-1 stage of N-type field effect tube group is electrically connected with the grid electrode of the second N-type field effect tube in the same N-type field effect tube group, the first pole of the first N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the first P-type field effect tube in the N-type field effect tube group, the first pole of the second N-type field effect tube in the first stage of N-type field effect tube group is electrically connected with the second pole of the second P-type field effect tube in the N-type field effect tube group, the second pole of the first N-type field effect tube in the i-stage of N-type field effect tube group is electrically connected with the second pole of the second P-type field effect tube in the i +1 stage of N A first pole of the effect tube is electrically connected, a second pole of the second N-type field effect tube in the i +1 th N-type field effect tube group is electrically connected with a first pole of the second N-type field effect tube in the i +1 th N-type field effect tube group, a gate of the first N-type field effect tube in the m-th N-type field effect tube group is used as the reverse input end of the amplifier, a gate of the second N-type field effect tube in the m-th N-type field effect tube group is used as the same-direction input end of the amplifier, a second pole of the first N-type field effect tube and a second pole of the second N-type field effect tube in the m-th N-type field effect tube group are both electrically connected with a first pole of the current source, and the second pole of the current source is connected to the second power signal; wherein n is an integer greater than 1, and i is a positive integer.
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CN109388171A (en) * 2018-12-10 2019-02-26 上海艾为电子技术股份有限公司 A kind of bandgap voltage reference and electronic equipment
CN110969730A (en) * 2019-11-05 2020-04-07 杭州亿强科技有限公司 Low-power-consumption circuit system applied to intelligent door lock and control method thereof
CN113311898A (en) * 2021-07-30 2021-08-27 唯捷创芯(天津)电子技术股份有限公司 LDO circuit with power supply suppression, chip and communication terminal
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CN109388171A (en) * 2018-12-10 2019-02-26 上海艾为电子技术股份有限公司 A kind of bandgap voltage reference and electronic equipment
CN109388171B (en) * 2018-12-10 2024-02-09 上海艾为电子技术股份有限公司 Band gap reference voltage source and electronic equipment
CN110969730A (en) * 2019-11-05 2020-04-07 杭州亿强科技有限公司 Low-power-consumption circuit system applied to intelligent door lock and control method thereof
CN114375432A (en) * 2019-11-28 2022-04-19 深圳市汇顶科技股份有限公司 Voltage stabilizer, image sensor and method
CN114375432B (en) * 2019-11-28 2024-01-26 深圳市汇顶科技股份有限公司 Voltage regulator, image sensor and method
US20220308609A1 (en) * 2021-03-25 2022-09-29 Qualcomm Incorporated Power supply rejection enhancer
US11687104B2 (en) * 2021-03-25 2023-06-27 Qualcomm Incorporated Power supply rejection enhancer
US12181903B2 (en) 2021-03-25 2024-12-31 Qualcomm Incorporated Power supply rejection enhancer
CN113311898A (en) * 2021-07-30 2021-08-27 唯捷创芯(天津)电子技术股份有限公司 LDO circuit with power supply suppression, chip and communication terminal
WO2023005806A1 (en) * 2021-07-30 2023-02-02 唯捷创芯 （天津）电子技术股份有限公司 Ldo circuit having power supply rejection function, chip and communication terminal

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