CN108897601A - A kind of FPGA application method, system and relevant apparatus based on virtualization - Google Patents

Abstract

This application discloses a method for using FPGA based on virtualization, using SR‑IOV technology to virtualize a single physical FPGA into multiple VFPGAs, and assigning a VFPGA to each created container, and then attaching each After the allocated VFPGA is mounted to the corresponding container, each container can carry out subsequent operations by mounting its own VFPGA, which is different from the traditional way that each container needs to occupy an entire physical FPGA. This application can use SR‑ IOV's hardware virtualization technology realizes that multiple containers correspond to a physical FPGA, which can improve the performance utilization rate of FPGA while reducing the number of FPGAs used. The present application also discloses a virtualization-based FPGA application system, FPGA and computer-readable storage medium, which have the above-mentioned beneficial effects.

Description

A virtualization-based FPGA usage method, system and related devices

technical field

The present application relates to the technical field of containerization, and in particular to a virtualization-based FPGA usage method, system, FPGA, and computer-readable storage medium.

Background technique

With the rise of artificial intelligence, higher requirements are put forward for the amount of data calculation and calculation speed, which also leads to FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) playing an increasingly important role in the field of accelerated computing. Many applications and services can significantly improve computing speed and efficiency with the support provided by FPGA.

Docker, as an open source application container engine, allows developers to package their applications and dependencies into a portable container, and then publish it to any machine running Linux (a popular operating system), compared to traditional In this way, because the Docker-based containerization technology does not need to rely on the external environment, it has higher security and lower system software coupling.

In the PAAS platform (Platform-as-a-Service, platform as a service, that is, a business model in which the server platform is provided as a service), the existing technology adopts a PassThrough-based method to establish the connection between each FPGA and the container, but In this implementation, each container needs to establish a connection with a separate FPGA through PassThrough to achieve subsequent operations, but in reality, each single container cannot fully utilize the full performance of each FPGA, cost-effective (FPGA has been The ratio between performance and implementation cost) is low.

Therefore, it is urgent for those skilled in the art to solve various technical defects in the existing mechanism for using between FPGA and container, and to provide a mechanism for using between FPGA and container with lower implementation cost and higher performance utilization of each FPGA. The problem.

Contents of the invention

The purpose of this application is to provide a virtualization-based FPGA usage method, using SR-IOV technology to virtualize a single physical FPGA into multiple VFPGAs, and assign a VFPGA to each created container, and use the mounting tool to After each allocated VFPGA is mounted to the corresponding container, each container can carry out subsequent operations by mounting its own VFPGA, which is different from the traditional way that each container needs to occupy an entire physical FPGA. This application can use The hardware virtualization technology of SR-IOV realizes that multiple containers correspond to a physical FPGA, which can improve the performance utilization rate of FPGA while reducing the number of FPGAs used.

Another object of the present application is to provide a virtualization-based FPGA application system, FPGA and computer-readable storage medium.

In order to achieve the above object, the application provides a virtualization-based FPGA usage method, including:

Use SR-IOV technology to virtualize a single FPGA into a preset number of VFPGAs;

A VFPGA is allocated to each created container, and each allocated VFPGA is mounted to a corresponding container, so that each container performs subsequent operations through the VFPGA mounted on itself.

Optionally, before assigning a VFPGA to each created container, further include:

Name each VFPGA to obtain each VFPGA ID;

Counting each of the VFPGA IDs, generating a VFGPA pool to be allocated that includes each of the VFPGA IDs;

Correspondingly, assigning one VFPGA to each created container specifically includes;

Select a VFPGA ID from the VFGPA pool to be allocated for each created container;

Allocate the VFPGA corresponding to each selected VFPGA ID to the corresponding container.

Optionally, after allocating the VFPGA corresponding to each selected VFPGA ID to the corresponding container, further include:

Add an allocated mark to the VFPGA allocated to one of the containers, and remove the VFPGA ID of the VFPGA with the allocated mark from the VFGPA pool to be allocated.

Optionally, the method for using FPGA based on virtualization also includes:

When the target container no longer needs to be mounted on its own VFPGA, the mounting relationship between the target VFPGA and the target container is released, and the assigned mark attached to the target VFPGA is removed to obtain the VFPGA to be allocated; wherein, The target VFPGA is the VFPGA that has the mount relationship with the target container before;

The VFPGA ID of the VFPGA to be allocated is supplemented into the VFPGA pool to be allocated.

In order to achieve the above object, the application also provides a virtualization-based FPGA usage system, which includes:

The SR-IOV virtualization unit is used to virtualize a single FPGA into a preset number of VFPGAs using SR-IOV technology;

The VFPGA allocation and mounting unit is used to allocate one VFPGA to each created container, and mount each allocated VFPGA to the corresponding container, so that each container can be mounted by Perform subsequent operations on its own VFPGA.

Optionally, the virtualization-based FPGA usage system also includes:

The VFPGA naming unit is used to name each VFPGA to obtain each VFPGA ID;

The VFGPA pool to be allocated generating unit is used to count each of the VFPGA IDs, and generate a VFGPA pool to be allocated that includes each of the VFPGA IDs;

Correspondingly, the VFPGA allocation and mounting unit specifically includes;

Any selection subunit is used to select a VFPGA ID from the VFGPA pool to be allocated for each created container;

The allocation subunit is configured to allocate the VFPGA corresponding to each selected VFPGA ID to the corresponding container.

Optionally, the virtualization-based FPGA usage system also includes:

Assigned tag addition and assigned VFPGA removal unit, used to add assigned tags to the VFPGA assigned to one of the containers, and add the VFPGA ID of the assigned tag's VFPGA from the VFGPA pool to be allocated remove.

Optionally, the virtualization-based FPGA usage system also includes:

The mounting relationship release and assigned mark removal unit is used to release the mounting relationship between the target VFPGA and the target container when the target container no longer needs to be mounted on its own VFPGA, and remove the attachment attached to the target VFPGA. The assigned mark on the above, to obtain the VFPGA to be allocated; wherein, the target VFPGA is the VFPGA that has the mount relationship with the target container before;

The VFPGA pool to be allocated supplementary unit is used to supplement the VFPGA ID of the VFPGA to be allocated into the VFPGA pool to be allocated.

In order to achieve the above object, the application also provides a kind of FPGA, and this FPGA comprises:

memory for storing computer programs;

The processor is configured to implement the steps of the method for using the FPGA as described above when executing the computer program.

To achieve the above object, the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method for using FPGA as described above is realized A step of.

Obviously, this application provides a virtualization-based FPGA usage method, which uses SR-IOV technology to virtualize a single physical FPGA into multiple VFPGAs, and assigns a VFPGA to each created container. After the loading tool mounts each allocated VFPGA to the corresponding container, each container can carry out subsequent operations by mounting its own VFPGA, which is different from the traditional way that each container needs to occupy an entire physical FPGA. This application The hardware virtualization technology of SR-IOV can be used to realize that multiple containers correspond to a physical FPGA, which can improve the performance utilization rate of FPGA while reducing the number of FGPA used. At the same time, the present application also provides a virtualization-based FPGA application system, FPGA and computer-readable storage medium, which have the above-mentioned beneficial effects and will not be repeated here.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present application, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is the flow chart of a kind of FPGA using method based on virtualization that the embodiment of the present application provides;

Fig. 2 is a flow chart of another virtualization-based FPGA usage method provided by the embodiment of the present application;

FIG. 3 is a schematic diagram of a connection relationship between an existing FPGA and a container;

Fig. 4 is a schematic diagram of a connection relationship between an FPGA and a container provided by the embodiment of the present application;

FIG. 5 is a structural block diagram of a virtualization-based FPGA utilization system provided by an embodiment of the present application.

Detailed ways

The core of this application is to provide a virtualization-based FPGA usage method, which uses SR-IOV technology to virtualize a single physical FPGA into multiple VFPGAs, and assigns a VFPGA to each created container. After the tool mounts each allocated VFPGA to the corresponding container, each container can carry out subsequent operations by mounting its own VFPGA, which is different from the traditional way that each container needs to occupy an entire physical FPGA. This application can With the hardware virtualization technology of SR-IOV, multiple containers correspond to a physical FPGA, which can improve the performance utilization of FPGA while reducing the number of FPGAs used. Another core of the present application is to provide a virtualization-based FPGA application system, FPGA and computer-readable storage medium, which have the above-mentioned beneficial effects.

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Below in conjunction with Fig. 1, Fig. 1 is a flow chart of a virtualization-based FPGA usage method provided by the embodiment of the present application, specifically comprising the following steps:

S101: Using SR-IOV technology to virtualize a single FPGA into a preset number of VFPGAs;

This step aims to use hardware virtualization technology to virtualize a single physical FPGA into logically identifiable multiple VFPGAs (Virtual-FPGA, virtual FPGA), so as to make the one-to-one correspondence between FPGA and container in the prior art The relationship is changed to a one-to-many relationship, thereby greatly improving the performance utilization of the FPGA and reducing the implementation cost.

Among them, SR-IOV technology is a hardware-based virtualization solution that can improve performance and scalability, and the SR-IOV standard allows efficient sharing of PCIe (Peripheral Component InterconnectExpress, fast peripheral component interconnection) between virtual machines device, and it is implemented in hardware to achieve I/O performance comparable to native performance. The SR-IOV specification defines a new standard by which new devices are created that allow virtual machines to connect directly to I/O devices.

Using SR-IOV technology, one FPGA can be virtualized into logically identifiable multiple VFPGAs. Although these VFPGAs are actually the same FPGA, each different VFPGA is actually just a part of a complete FPGA. Part of it is as if an 8-core processor was monopolized by a task, but in fact this task cannot use the full performance of the 8-core processor, and a large part of the performance is unused and wasted, but there is no way, this is It is fixed based on the upper-layer protocol, and the present application uses virtualization technology to virtualize the 8-core processor into 8 virtual processors by using different upper-layer protocols. Of course, each virtual processor in the 8 virtual processors The performance is not as good as that of the original 8-core processors. One way of performance distribution is equal sharing, that is, the 8 virtual processors all have 1/8 of the total performance of the original 8-core processors. Use means to make each virtual processor have a performance greater than 1/8 of the total performance of the original 8-core processor.

The VFPGA virtualized by SR-IOV will also have its own identification mark like the original FPGA, so it can be recognized by the operating system normally, as if there are multiple FPGAs, but in fact no matter which VFPGA is executed The operation is actually performed by the original FPGA.

S102: Allocating a VFPGA to each created container, and mounting each allocated VFPGA to a corresponding container, so that each container performs subsequent operations through the VFPGA mounted on itself.

On the basis of S101, this step aims to assign multiple VFPGAs virtualized by SR-IOV technology to each created container, that is, assign a VFPGA to each created container, and after the allocation, It is also necessary to mount each assigned VFPGA to the corresponding container to enable each container to perform subsequent operations through the VFPGA mounted on itself, that is, to enable the services or applications corresponding to each container to enjoy the benefits brought by the FPGA. operation acceleration effect.

The container here refers to a form of expression of the service or application obtained by using the containerization technology to containerize the service or application. For a more detailed explanation of the containerization technology, please refer to the background technology section, and will not repeat it here.

Furthermore, how to allocate VFPGA to each container has a variety of methods. In the serial processing allocation mode, multiple containers that are simultaneously in the VFPGA to be allocated can be sorted in a certain order, and the first is determined according to the sorting result. Which containers are assigned VFPGAs? Further, multiple VFPGAs virtualized at the same time can also be sorted in a certain order, so as to determine which VFPGA is allocated to the container first according to the sorting results. VFPGA is named, and then each VFPGA can be sorted according to the size of the number, etc., and there is no specific limitation here. Those skilled in the art can obtain multiple specific implementation methods under the guidance of this step thought, as long as it can be realized for each The purpose of allocating one VFPGA per container is sufficient, and the most appropriate allocation method can be flexibly selected according to the actual situation.

In the mounting step, the purpose of mounting a VFPGA to a container can be achieved with the help of a general mounting tool. In fact, it is to establish a binding relationship between the two, so that the corresponding service or application of the container The purpose of computing acceleration can be finally realized through the VFPGA bound to itself.

Furthermore, depending on the operating status of the operating system and changes in real-time functions, some applications or services may no longer be used. At this time, the mounting relationship with the VFPGA that has been mounted on itself can be released, that is, the VFPGA can be released. , so that the released VFPGA can be redistributed and mounted to another required service or application container.

In the specific implementation process, in order to distinguish the different states of each VFPGA (allocated, not allocated), it can also be distinguished by adding corresponding identification marks in different states.

Based on the above technical solution, the embodiment of the present application provides a virtualization-based FPGA usage method, using SR-IOV technology to virtualize a single physical FPGA into multiple VFPGAs, and assigning a VFPGA to each created container. After mounting each allocated VFPGA to the corresponding container with the help of the mounting tool, each container can carry out subsequent operations by mounting its own VFPGA, which is different from the traditional way that each container needs to occupy an entire physical FPGA. This application can use the hardware virtualization technology of SR-IOV to realize that multiple containers correspond to one physical FPGA, which can improve the performance utilization rate of FPGA while reducing the number of FGPA used.

Below in conjunction with Fig. 2, Fig. 2 is a flow chart of another FPGA usage method based on virtualization provided by the embodiment of the present application. On the basis of Embodiment 1, this embodiment, by naming each VFPGA and generating ID’s VFGPA pool to be allocated, select a VFPGA from the VFGPA pool to be allocated each time to the required container, and distinguish VFPGAs in different states by attaching allocated marks to the allocated VFPGAs, and then assign the marked VFPGAs The VFPGA ID corresponding to the VFPGA is removed from the pool to be allocated to make the actual effect better. The specific implementation steps are as follows:

S201: Using SR-IOV technology to virtualize a single FPGA into a preset number of VFPGAs;

S202: Naming each VFPGA to obtain each VFPGA ID;

S203: Count each VFPGA ID, and generate a VFGPA pool to be allocated including each VFPGA ID;

S204: Select a VFPGA ID from the VFGPA pool to be allocated for each created container;

S205: Allocate the VFPGA corresponding to each selected VFPGA ID to the corresponding container;

S206: Add an allocated mark to the VFPGA allocated to a container, and remove the VFPGA ID of the VFPGA with the allocated mark from the VFGPA pool to be allocated;

S207: Mount each allocated VFPGA on a corresponding container, so that each container performs subsequent operations through the VFPGA mounted on itself.

Further, when the target container no longer needs to be mounted on its own VFPGA, release the mounting relationship between the target VFPGA and the target container, and remove the assigned mark attached to the target VFPGA to obtain the VFPGA to be allocated;

Add the VFPGA ID of the VFPGA to be allocated to the VFPGA pool to be allocated, so as to re-allocate and mount the VFPGA to the required container. Among them, the target VFPGA is the VFPGA that has a mounting relationship with the target container before.

Embodiment three

On the basis of the above-mentioned embodiments, this embodiment combines the actual scene and respectively combines the prior art shown in FIG. 3 and the present application shown in FIG. 4 to illustrate the invention points of the present application:

As shown in Figure 3, each container in the prior art needs to establish a connection with the corresponding FPGA through an MMU (Memory Management Unit, memory management unit), that is, a container corresponds to a physical FPGA;

As shown in Figure 4, only one physical FPGA device is used, and multiple VFPGA devices are virtualized by using SR-IOV technology, and the corresponding mounting tools can be used to dynamically establish and cancel the mounting relationship between each VFPGA and the container. Significantly improve the use efficiency of FPGA in cloud environment and greatly reduce the cost of using FPGA.

The specific implementation is as follows:

First, rewrite the FPGA driver so that the FPGA supports SRIOV technology:

(1) PF driver: PF driver can directly access all resources of PF, and is responsible for managing and configuring all VFs;

(2) VF driver: It runs on the client computer like a normal PCIE driver, and directly accesses a specific VF device to complete the data transfer without the participation of VMM;

(3) IOVM: IOVM allocates a complete virtual configuration space for each VF, so clients can emulate and configure VFs like ordinary devices.

Among them, PF is a PCI (Peripheral Component Interconnect, peripheral component interconnection standard, which is currently the most widely used interface in personal computers, and almost all motherboard products have this slot) supported by the physical network card. Function, PF can expand several VFs;

VF is a "network card" virtualized by a physical network card that supports SR-IOV or a virtual instance. It will be presented as an independent network card. Each VF has its own exclusive PCI configuration area, and It may share the same physical resource (share the same physical network port) with other VFs;

The PF driver works in the parent area of the virtualization platform and is loaded first before the VF;

The VF driver works in the virtualization platform sub-area;

It should be noted that VF and PF are isolated, and any results driven or executed by VF will not affect other VF or PF.

Next, create N VFPGAs through the upper interface, and mount these VFPGAs to different created containers through the mounting tool. At this time, you will see the device descriptor of the VFPGA in the corresponding directory in the container. Through this description We can operate VFPGA like a physical FPGA, and all operations on VFPGA will be driven to operate the real physical FPGA calmly:

(1) Create a container that needs to use a virtual FPGA, and the container contains corresponding applications or services;

(2) Use the mounting tool to dynamically mount VFPGA into the container, and you can see the corresponding device descriptor in the container;

(3) When the container no longer needs to use VFPGA for heterogeneous acceleration, it can also be unbound at any time through the mounting tool, and the VFPGA can be dynamically allocated to other containers for use.

This embodiment uses the VFPGA virtualized from the physical FPGA through the SR-IOV foundation as the external device of the container, which can make full use of the performance of the FPGA device, improve the performance utilization rate of the physical FPGA, and effectively accelerate the application or service in the container , to improve the PAAS platform's support for heterogeneous computing.

Because of the complexity of the situation, it is impossible to list and explain them one by one. Those skilled in the art should be able to realize that there may be many examples based on the basic method principles provided by this application combined with actual situations. within the scope of protection.

Please refer to FIG. 5 below. FIG. 5 is a structural block diagram of a virtualization-based FPGA usage system provided by an embodiment of the present application. The virtualization-based FPGA usage system may include:

SR-IOV virtualization unit 100, for utilizing SR-IOV technology to virtualize a single FPGA into a preset number of VFPGAs;

The VFPGA allocation and mounting unit 200 is configured to allocate one VFPGA to each created container, and mount each allocated VFPGA to the corresponding container, so that each container can The subsequent operations are carried out on the VFPGA itself.

Further, the virtualization-based FPGA usage system may also include:

The VFPGA naming unit is used to name each VFPGA to obtain each VFPGA ID;

The VFGPA pool to be allocated generating unit is used to count each of the VFPGA IDs, and generate a VFGPA pool to be allocated that includes each of the VFPGA IDs;

Correspondingly, the VFPGA allocation and mounting unit 200 specifically includes;

Any selection subunit is used to select a VFPGA ID from the VFGPA pool to be allocated for each created container;

The allocation subunit is configured to allocate the VFPGA corresponding to each selected VFPGA ID to the corresponding container.

Further, the virtualization-based FPGA usage system may also include:

Assigned tag addition and assigned VFPGA removal unit, used to add assigned tags to the VFPGA assigned to one of the containers, and add the VFPGA ID of the assigned tag's VFPGA from the VFGPA pool to be allocated remove.

Further, the virtualization-based FPGA usage system may also include:

The mounting relationship release and assigned mark removal unit is used to release the mounting relationship between the target VFPGA and the target container when the target container no longer needs to be mounted on its own VFPGA, and remove the attachment attached to the target VFPGA. The assigned mark on the above, to obtain the VFPGA to be allocated; wherein, the target VFPGA is the VFPGA that has the mount relationship with the target container before;

The VFPGA pool to be allocated supplementary unit is used to supplement the VFPGA ID of the VFPGA to be allocated into the VFPGA pool to be allocated.

Based on the above embodiments, the present application also provides an FPGA, which may include a memory and a processor, wherein a computer program is stored in the memory, and when the processor invokes the computer program in the memory, the above embodiments can be realized provided steps. Of course, the FPGA may also include various necessary network interfaces, power supplies and other components.

The present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by an execution terminal or a processor, the steps provided in the above-mentioned embodiments can be realized. The storage medium may include various media capable of storing program codes such as a U disk, a removable hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk.

Each embodiment in the description is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related part, please refer to the description of the method part.

Professionals can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the possible For interchangeability, in the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

In this paper, specific examples are used to illustrate the principles and implementation methods of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. For those of ordinary skill in the art, without departing from the principle of the application, some improvements and modifications can be made to the application, and these improvements and modifications also fall within the protection scope of the claims of the application.

It should also be noted that in this specification, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is no such actual relationship or order between the operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

Claims (10)

1. A method for using FPGA based on virtualization, characterized in that, comprising: Use SR-IOV technology to virtualize a single FPGA into a preset number of VFPGAs; A VFPGA is allocated to each created container, and each allocated VFPGA is mounted to a corresponding container, so that each container performs subsequent operations through the VFPGA mounted on itself. 2. FPGA using method according to claim 1, is characterized in that, before allocating a described VFPGA respectively for each created container, also comprises: Name each VFPGA to obtain each VFPGA ID; Counting each of the VFPGA IDs, generating a VFGPA pool to be allocated that includes each of the VFPGA IDs; Correspondingly, assigning one VFPGA to each created container specifically includes; Select a VFPGA ID from the VFGPA pool to be allocated for each created container; Allocate the VFPGA corresponding to each selected VFPGA ID to the corresponding container. 3. FPGA using method according to claim 2, is characterized in that, after the VFPGA corresponding to the VFPGA ID that each picks out is assigned to corresponding container, also comprise: Add an allocated mark to the VFPGA that has been allocated to one of the containers, and remove the VFPGA ID of the VFPGA with the allocated mark from the VFGPA pool to be allocated. 4. FPGA using method according to claim 3, is characterized in that, also comprises: When the target container no longer needs to be mounted on its own VFPGA, the mounting relationship between the target VFPGA and the target container is released, and the assigned mark attached to the target VFPGA is removed to obtain the VFPGA to be allocated; wherein, The target VFPGA is the VFPGA that has the mount relationship with the target container before; The VFPGA ID of the VFPGA to be allocated is supplemented into the VFPGA pool to be allocated. 5. A virtualization-based FPGA application system, characterized in that, comprising: The SR-IOV virtualization unit is used to virtualize a single FPGA into a preset number of VFPGAs using SR-IOV technology; The VFPGA allocation and mounting unit is used to allocate one VFPGA to each created container, and mount each allocated VFPGA to the corresponding container, so that each container can be mounted by Perform subsequent operations on its own VFPGA. 6. FPGA using system according to claim 5, is characterized in that, also comprises: The VFPGA naming unit is used to name each VFPGA to obtain each VFPGA ID; The VFGPA pool to be allocated generating unit is used to count each of the VFPGA IDs, and generate a VFGPA pool to be allocated that includes each of the VFPGA IDs; Correspondingly, the VFPGA allocation and mounting unit specifically includes; Any selection subunit is used to select a VFPGA ID from the VFGPA pool to be allocated for each created container; The allocation subunit is configured to allocate the VFPGA corresponding to each selected VFPGA ID to the corresponding container. 7. FPGA using system according to claim 6, is characterized in that, also comprises: Assigned tag addition and assigned VFPGA removal unit, used to add assigned tag to the VFPGA assigned to a container, and add the VFPGA ID of the assigned tag's VFPGA from the VFGPA pool to be allocated remove. 8. FPGA using system according to claim 7, is characterized in that, also comprises: The mounting relationship release and assigned mark removal unit is used to release the mounting relationship between the target VFPGA and the target container when the target container no longer needs to be mounted on its own VFPGA, and remove the attachment attached to the target VFPGA. The assigned mark on the above, to obtain the VFPGA to be allocated; wherein, the target VFPGA is the VFPGA that has the mount relationship with the target container before; The VFPGA pool to be allocated supplementary unit is used to supplement the VFPGA ID of the VFPGA to be allocated into the VFPGA pool to be allocated. 9. A kind of FPGA, is characterized in that, comprises: memory for storing computer programs; A processor, configured to implement the steps of the method for using FPGA according to any one of claims 1 to 4 when executing the computer program. 10. A computer-readable storage medium, characterized in that, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the FPGA according to any one of claims 1 to 4 is realized Steps to use the method.