CN108832809A - A DC-DC circuit for generating negative pressure - Google Patents

Abstract

It is a kind of for generating the DC-DC circuit of negative pressure, belong to electronic circuit technology field.Clock signal is generated under the control of enable signal including oscillator module, drive module, non-overlapping clock generation module and switching capacity module, oscillator module；Drive module generates inverting clock signal according to clock signal, and clock signal and inverting clock signal by the just non-overlapping clock generating unit in non-overlapping clock generation module and bear the switching tube in non-overlapping clock generating unit control switch capacitance module respectively；Switching capacity module generates negative voltage using the electric charge transfer of capacitor, and negative voltage feeds back to drive module adjustment inverting clock signal, the negative voltage that a successive step of going forward side by side generates；Can also guarantee negative voltage in some embodiments using clamper module and output module stablizes output.The present invention has the characteristics that output is reliable and stable, the response time is short and low in energy consumption, solves the problems, such as that the moment of electrifying startup is easy to cause circuit malfunction locked.

Description

A DC-DC circuit for generating negative pressure

technical field

The invention belongs to the technical field of electronic circuits and relates to a DC-DC circuit for generating negative pressure.

Background technique

In the application process of integrated circuits, different voltages are usually required, and the input voltage of the circuit is usually single or limited. Therefore, it is necessary to convert the positive input voltage into different positive or negative voltages in circuit design. to the voltage circuit. For example, in the design of the power supply in portable equipment, it is also necessary to provide a negative power supply.

At present, there are many ways to generate negative voltage, but most of the traditional DC-DC circuits that generate negative voltage are more complicated, and the power consumption is high, and the output voltage is unstable, especially at the moment when the circuit is powered on and started, it is easy to cause negative voltage generation circuit Failed lockout.

Contents of the invention

Aiming at the problems of complex structure, unstable output voltage, high power consumption and easy circuit failure and lockup at the moment of electric start-up in the above-mentioned traditional DC-DC circuit that generates negative pressure, the present invention proposes a DC-DC circuit , used to generate a negative voltage, using the switched capacitor module 50 to generate a negative voltage and feeding it back to the drive module 30 to ensure the reliability of the negative voltage output while speeding up the response time of the circuit. In some embodiments, the clamping module 10 and the The output module 60 ensures the stable output of the negative voltage VDDN.

Technical scheme of the present invention is:

A DC-DC circuit for generating negative voltage, comprising an oscillator module 20, a drive module 30, a non-overlapping clock generation module 40 and a switched capacitor module 50,

The enable end of the oscillator module 20 is connected to the enable signal EN, its power end is connected to the power supply voltage VDD, its ground end is connected to the ground voltage VSS, and its output end outputs the clock signal CLK;

The input terminal of the driving module 30 is connected to the clock signal CLK, and its output terminal outputs an inverted clock signal CLK_N;

The non-overlapping clock generation module 40 includes a positive non-overlapping clock generation unit and a negative non-overlapping clock generation unit, the input end of the positive non-overlapping clock generation unit is connected to the clock signal CLK, and its output end outputs a mutual Inverted and non-overlapping first positive non-overlapping clock signal CLK_P1 and second positive non-overlapping clock signal CLK_P2; the input terminal of the negative non-overlapping clock generation unit is connected to the inverted clock signal CLK_N, which The output terminal outputs a first negative non-overlapping clock signal CLK_N1 and a second negative non-overlapping clock signal CLK_N2 which are mutually inverse and non-overlapping;

The switched capacitor module 50 includes a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4,

One end of the first switching tube S1 is connected to the power supply voltage VDD, and the other end is connected to one end of the second switching tube S2 and one end of the first capacitor C1, and its control signal is the first positive non-overlapping clock signal CLK_P1;

The other end of the second switching tube S2 is connected to one end of the second capacitor C2 and to the ground voltage VSS, and its control signal is the second positive non-overlapping clock signal CLK_P2;

One end of the third switching tube S3 is connected to the ground voltage VSS, and the other end is connected to one end of the fourth switching tube S4 and the other end of the first capacitor C1, and its control signal is the first negative non-overlapping clock signal CLK_N1;

The other end of the fourth switching tube S4 is connected to the other end of the second capacitor C2 and outputs a negative voltage VDDN as the output signal of the DC-DC circuit, and its control signal is the second negative non-overlapping clock signal CLK_N2;

The negative voltage VDDN is used as a feedback signal of the driving module 30 to adjust the negative voltage VDDN.

Specifically, the driving module 30 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a first PMOS transistor MP1,

The gate of the fifth NMOS transistor MN5 is connected to the gates of the first PMOS transistor MP1 and the third NMOS transistor MN3 and serves as the input terminal of the driving module 30, and its drain is connected to the drain of the first PMOS transistor MP1 and the fourth NMOS transistor MN5. The gate of the tube MN4, the source of which is connected to the ground voltage VSS;

The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD;

The gate of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 as the output terminal of the driving module 30, and its drain is connected to the gate of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3. The source of the fourth NMOS transistor MN4 is connected to the source of the second NMOS transistor MN2 and connected to the negative voltage VDDN;

The drains of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the ground voltage VSS.

Specifically, the negative voltage VDDN is used as the output signal of the DC-DC circuit after passing through the clamping module 10 and the output module 60;

The clamping module 10 includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6 and a seventh NMOS transistor MN7,

The gate of the third PMOS transistor MP3 is connected to the enable signal EN, the drain thereof is connected to the gates of the fourth PMOS transistor MP4 and the sixth NMOS transistor MN6 and the drains of the fifth PMOS transistor MP5 and the seventh NMOS transistor MN7, and As the output terminal of the clamping module 10, its source is connected to the source of the second PMOS transistor MP2, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 and connected to the power supply voltage VDD;

The gate of the second PMOS transistor MP2 is connected to the inversion signal EN_N of the enable signal EN, and its drain is connected to the drains of the fourth PMOS transistor MP4 and the sixth NMOS transistor MN6 and the fifth PMOS transistor MP5 and the seventh NMOS transistor. Gate of MN7;

The sources of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are connected to the negative voltage VDDN;

The output module 60 includes a sixth PMOS transistor MP6 and an eighth NMOS transistor MN8,

The gate of the sixth PMOS transistor MP6 is connected to the gate of the eighth NMOS transistor MN8 and connected to the output terminal of the clamping module 10, its source is connected to the ground voltage VSS, and its drain is connected to the drain of the eighth NMOS transistor MN8. outputting an output signal of the DC-DC circuit;

The source of the eighth NMOS transistor MN8 is connected to the negative voltage VDDN.

Specifically, the first switch S1 includes a seventh PMOS transistor MP7, the second switch S2 includes an eighth PMOS transistor MP8, the third switch S3 includes a ninth PMOS transistor MP9, and the fourth switch The tube S4 includes a tenth PMOS tube MP10;

The gate of the seventh PMOS transistor MP7 is connected to the first positive non-overlapping clock signal CLK_P1, its source is connected to the power supply voltage VDD, and its drain is connected to the source of the eighth PMOS transistor MP8;

The gate of the eighth PMOS transistor MP8 is connected to the second positive non-overlapping clock signal CLK_P2, and its drain is connected to the ground voltage VSS;

The gate of the ninth PMOS transistor MP9 is connected to the first negative non-overlapping clock signal CLK_N1, its source is connected to the ground voltage VSS, and its drain is connected to the source of the tenth PMOS transistor MP10;

The gate of the tenth PMOS transistor MP10 is connected to the second negative non-overlapping clock signal CLK_N2, and its drain outputs the negative voltage VDDN;

The first capacitor C1 is connected between the sources of the eighth PMOS transistor MP8 and the tenth PMOS transistor MP10, and the second capacitor C2 is connected between the drains of the eighth PMOS transistor MP8 and the tenth PMOS transistor MP10.

The beneficial effects of the present invention are: the present invention utilizes the negative voltage VDDN generated by the switched capacitor module 50 to pass positive feedback to the drive module 30 to ensure the reliability of the output negative voltage VDDN, and at the same time speed up the response time of the circuit. In some embodiments The stable output of the negative voltage VDDN is guaranteed by the clamping module 10 and the output module 60, which solves the problem of the complexity of the traditional negative voltage DC-DC conversion circuit, unstable output voltage, high power consumption and easy circuit failure at the moment of power-on. The problem of invalid lock.

Description of drawings

FIG. 1 is a schematic diagram of a circuit realization structure of a DC-DC circuit for generating negative voltage proposed by the present invention.

FIG. 2 is a schematic diagram of the operation sequence of a DC-DC circuit for generating negative voltage proposed by the present invention.

Detailed ways

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

A DC-DC circuit for generating negative voltage proposed by the present invention includes an oscillator module 20, a drive module 30, a non-overlapping clock generation module 40 and a switched capacitor module 50, and the enabling terminal of the oscillator module 20 is connected to enable The enable signal EN, its power supply terminal is connected to the power supply voltage VDD, its ground terminal is connected to the ground voltage VSS, and its output terminal outputs the clock signal CLK; the enable signal EN is an externally given enable signal, when the enable signal EN is 0, When the oscillator is turned on, the output is valid; when the enable signal EN is 1, the oscillator is turned off, and the output circuit is reset. When the circuit starts to work, first enable the use of the enable signal EN, so that the oscillator module 20 generates the clock signal CLK, the clock signal CLK is a square wave signal whose amplitude is from the ground voltage VSS to the power supply voltage VDD, and is used as a positive non-overlapping The input signal of the clock generation unit is also used as the input signal of the drive module 30 to generate the inverted clock signal CLK_N, the inverted clock signal CLK_N is the inverted signal of the clock signal CLK, and the clock signal CLK and the inverted clock signal CLK_N are respectively passed through The positive non-overlapping clock generating unit and the negative non-overlapping clock generating unit in the non-overlapping clock generating module 40 control the switches in the switched capacitor module 50 .

The input terminal of the driving module 30 is connected to the clock signal CLK, and its output terminal outputs the inverted clock signal CLK_N; the negative voltage VDDN generated by the switched capacitor module 50 is used as the feedback signal feedback of the driving module 30 to drive the module 30 to adjust the negative voltage VDDN to ensure This improves the reliability of the negative voltage VDDN output while speeding up the response time of the circuit. As shown in FIG. 1, a circuit implementation structure of the driving module 30 is given, including a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a fifth NMOS transistor MN5. A PMOS transistor MP1, the gate of the fifth NMOS transistor MN5 is connected to the gates of the first PMOS transistor MP1 and the third NMOS transistor MN3 and serves as the input terminal of the drive module 30, and its drain is connected to the drain of the first PMOS transistor MP1 and The gate of the fourth NMOS transistor MN4 has its source connected to the ground voltage VSS; the source of the first PMOS transistor MP1 is connected to the power supply voltage VDD; the gate of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2 and the third The source of the NMOS transistor MN3 serves as the output end of the drive module 30, its drain is connected to the gate of the second NMOS transistor MN2 and the source of the fourth NMOS transistor MN4, its source is connected to the source of the second NMOS transistor MN2 and connected to the negative voltage VDDN; the drains of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the ground voltage VSS. The negative voltage VDDN is connected to the sources of the first NMOS transistor MN1 and the second NMSO transistor MN2 through a feedback loop to ensure that the output amplitude of the inverted clock signal CLK_N is further adjusted to a square wave from -VDD to VSS.

The non-overlapping clock generation module 40 includes a positive non-overlapping clock generation unit and a negative non-overlapping clock generation unit, and the input end of the positive non-overlapping clock generation unit is connected to the clock signal CLK for generating mutually anti-phase and non-overlapping The first positive non-overlapping clock signal CLK_P1 and the second positive non-overlapping clock signal CLK_P2; the input end of the negative non-overlapping clock generation unit is connected to the inverted clock signal CLK_N, which is used to generate mutually inverted and non-overlapping The first negative non-overlapping clock signal CLK_N1 and the second negative non-overlapping clock signal CLK_N2.

As shown in FIG. 1 , the switched capacitor module 50 includes a first capacitor C1, a second capacitor C2, a first switch tube S1, a second switch tube S2, a third switch tube S3, and a fourth switch tube S4. The first switch tube S1 One end of one end is connected to the power supply voltage VDD, the other end is connected to one end of the second switching tube S2 and one end of the first capacitor C1, and its control signal is the first positive non-overlapping clock signal CLK_P1; the other end of the second switching tube S2 is connected to the second One end of the capacitor C2 is connected to the ground voltage VSS, and its control signal is the second positive non-overlapping clock signal CLK_P2; one end of the third switching tube S3 is connected to the ground voltage VSS, and the other end is connected to one end of the fourth switching tube S4 and the first capacitor The other end of C1, whose control signal is the first negative non-overlapping clock signal CLK_N1; the other end of the fourth switching tube S4 is connected to the other end of the second capacitor C2 and outputs a negative voltage VDDN as the output signal of the DC-DC circuit, which The control signal is the second negative non-overlapping clock signal CLK_N2.

The clock signal CLK generates the first positive non-overlapping clock signal CLK_P1 and the second positive non-overlapping clock signal CLK_P2 through the positive non-overlapping clock generation unit to control the first switching tube S1 and the second switching tube S2 respectively, and the inverting clock The signal CLK_N generates the first negative non-overlapping clock signal CLK_N1 and the second negative non-overlapping clock signal CLK_N2 through the negative non-overlapping clock generation unit to control the third switching tube S3 and the fourth switching tube S4 respectively, and the first switching tube When S1 and the third switch tube S3 are turned on, the first capacitor C1 is charged, and when the second switch tube S2 and the fourth switch tube S4 are turned on, the charge in the first capacitor C1 is transferred to the second capacitor C2, The negative voltage VDDN is generated by the charge transfer of the first capacitor C1, and the negative voltage VDDN output by the second capacitor C2 supplies power to the driving module 30, which is a positive feedback loop.

Wherein the first switch tube S1, the second switch tube S2, the third switch tube S3 and the fourth switch tube S4 may be PMOS switch tubes or NMOS switch tubes, taking the PMOS switch tube as an example, the first switch tube S1 includes a seventh PMOS switch tube The second switch tube S2 includes the eighth PMOS tube MP8, the third switch tube S3 includes the ninth PMOS tube MP9, and the fourth switch tube S4 includes the tenth PMOS tube MP10; the gate of the seventh PMOS tube MP7 is connected to the first The source of the positive non-overlapping clock signal CLK_P1 is connected to the power supply voltage VDD, and the drain is connected to the source of the eighth PMOS transistor MP8; the gate of the eighth PMOS transistor MP8 is connected to the second positive non-overlapping clock signal CLK_P2, and its drain The pole is connected to the ground voltage VSS; the gate of the ninth PMOS transistor MP9 is connected to the first negative non-overlapping clock signal CLK_N1, its source is connected to the ground voltage VSS, and its drain is connected to the source of the tenth PMOS transistor MP10; the tenth PMOS transistor MP9 The gate of MP10 is connected to the second negative non-overlapping clock signal CLK_N2, and its drain outputs a negative voltage VDDN; the first capacitor C1 is connected between the sources of the eighth PMOS transistor MP8 and the tenth PMOS transistor MP10, and the second capacitor C2 Connected between the drains of the eighth PMOS transistor MP8 and the tenth PMOS transistor MP10.

In some embodiments, in order to ensure that the output of the negative voltage VDDN is more stable, the negative voltage VDDN can be output as the output signal of the DC-DC circuit after passing through the clamping module 10 and the output module 60, as shown in FIG. 1 , the clamping module 1 includes the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7, and the gate of the third PMOS transistor MP3 is connected to the enabling signal EN, whose drain is connected to the gates of the fourth PMOS transistor MP4 and the sixth NMOS transistor MN6 and the drains of the fifth PMOS transistor MP5 and the seventh NMOS transistor MN7 as the output terminal of the clamping module 10, and its source is connected to the first The sources of the second PMOS transistor MP2, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are connected to the power supply voltage VDD; the gate of the second PMOS transistor MP2 is connected to the inverted signal EN_N of the enable signal EN, and its drain is connected to the fourth The drains of the PMOS transistor MP4 and the sixth NMOS transistor MN6 and the gates of the fifth PMOS transistor MP5 and the seventh NMOS transistor MN7; the sources of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are connected to the negative voltage VDDN. The output module 60 includes a sixth PMOS transistor MP6 and an eighth NMOS transistor MN8, the gate of the sixth PMOS transistor MP6 is connected to the gate of the eighth NMOS transistor MN8 and connected to the output terminal of the clamping module 10, and its source is connected to the ground voltage VSS , the drain of which is connected to the drain of the eighth NMOS transistor MN8 and outputs the output signal of the DC-DC circuit; the source of the eighth NMOS transistor MN8 is connected to the negative voltage VDDN.

At this time, when the enable signal EN is 0, the output signal VOUT=VSS-V _OP -VDD+2V _OP -V _OP =-VDD, where V _OP is the voltage drop between the drain and the source of the switch.

FIG. 2 is a schematic diagram of the operation sequence of a DC-DC circuit for generating negative voltage proposed by the present invention, where Δt is the dead time, and all the switch tubes are in the cut-off state during this time period.

To sum up, the present invention proposes a DC-DC circuit for generating negative voltage, which solves the problem that the traditional negative voltage DC-DC conversion circuit is complex, the output voltage is unstable, and the circuit is easily caused by the moment of power-up on the circuit. For the problem of failure lock-up, the negative voltage VDDN generated by the switched capacitor module 50 is positively fed back to the drive module 30 to ensure the reliability of the output negative voltage VDDN, and at the same time speed up the response time of the circuit. In some embodiments, the clamping The module 10 and the output module 60 ensure the stable output of the negative voltage VDDN, and after being converted into the obtained negative voltage VDDN, the clamping module 10 and the output module 60 will clamp the output, and at this time other modules can be turned off, Save circuit power consumption.

It is to be understood that the invention is not limited to the precise configuration and components shown above. Various modifications and optimizations may be made to the step sequence, details and operations of the methods and structures described above without departing from the scope of protection of the claims.

Claims (4)

1. a kind of for generating the DC-DC circuit of negative pressure, which is characterized in that including oscillator module (20), drive module (30), Non-overlapping clock generation module (40) and switching capacity module (50),

The enable end of the oscillator module (20) connects enable signal (EN), and power end connects supply voltage (VDD), connects Ground terminal connects ground voltage (VSS), and output end exports clock signal (CLK)；

The input terminal of the drive module (30) connects the clock signal (CLK), and output end exports inverting clock signal (CLK_N)；

The non-overlapping clock generation module (40) includes just non-overlapping clock generating unit and bears non-overlapping clock generating unit, The input terminal of the just non-overlapping clock generating unit connects the clock signal (CLK), output end output each other reverse phase and The just non-overlapping clock signal (CLK_P1) of non-overlapping first and the second just non-overlapping clock signal (CLK_P2)；It is described to bear non-friendship The input terminal of folded clock generating unit connects the inverting clock signal (CLK_N), and output end exports reverse phase and non-friendship each other The negative non-overlapping clock signal (CLK_N1) of folded first and the second negative non-overlapping clock signal (CLK_N2)；

The switching capacity module (50) includes first capacitor (C1), the second capacitor (C2), first switch tube (S1), second switch (S2), third switching tube (S3) and the 4th switching tube (S4) are managed,

One end of first switch tube (S1) connects supply voltage (VDD), and the other end connects the one end and the of second switch (S2) One end of one capacitor (C1), control signal are the described first just non-overlapping clock signal (CLK_P1)；

One end of the other end connection the second capacitor (C2) of second switch (S2) simultaneously connects ground voltage (VSS), controls signal For the described second just non-overlapping clock signal (CLK_P2)；

One end of third switching tube (S3) connects ground voltage (VSS), and the other end connects one end and first of the 4th switching tube (S4) The other end of capacitor (C1), control signal are the described first negative non-overlapping clock signal (CLK_N1)；

The other end of the other end connection the second capacitor (C2) of 4th switching tube (S4) simultaneously exports described in negative voltage (VDDN) conduct The output signal of DC-DC circuit, control signal are the described second negative non-overlapping clock signal (CLK_N2)；

The negative voltage (VDDN) is used to adjust the negative voltage (VDDN) as the feedback signal of the drive module (30).

2. according to claim 1 for generating the DC-DC circuit of negative pressure, which is characterized in that the drive module (30) Including the first NMOS tube (MN1), the second NMOS tube (MN2), third NMOS tube (MN3), the 4th NMOS tube (MN4), the 5th NMOS (MN5) and the first PMOS tube (MP1) are managed,

The grid of 5th NMOS tube (MN5) connects the grid of the first PMOS tube (MP1) and third NMOS tube (MN3) and as described The input terminal of drive module (30), the drain electrode of drain electrode connection the first PMOS tube (MP1) and the grid of the 4th NMOS tube (MN4), Its source electrode connects ground voltage (VSS)；

The source electrode of first PMOS tube (MP1) connects supply voltage (VDD)；

The drain electrode of the grid connection the second NMOS tube (MN2) of first NMOS tube (MN1) and the source electrode and work of third NMOS tube (MN3) For the output end of the drive module (30), the grid of drain electrode connection the second NMOS tube (MN2) and the 4th NMOS tube (MN4) Source electrode, the source electrode of source electrode connection the second NMOS tube (MN2) simultaneously connect the negative voltage (VDDN)；

Third NMOS tube (MN3) connects ground voltage (VSS) with the drain electrode of the 4th NMOS tube (MN4).

3. according to claim 1 or 2 for generating the DC-DC circuit of negative pressure, which is characterized in that the negative voltage (VDDN) will also after clamper module (10) and output module (60) the just output signal as the DC-DC circuit；

The clamper module (10) includes the second PMOS tube (MP2), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th NMOS tube (MN6) and the 7th NMOS tube (MN7),

The grid of third PMOS tube (MP3) connects the enable signal (EN), drain electrode connection the 4th PMOS tube (MP4) and the 6th The drain electrode of the grid of NMOS tube (MN6) and the 5th PMOS tube (MP5) and the 7th NMOS tube (MN7) and as the clamper module (10) output end, source electrode connect the source electrode of the second PMOS tube (MP2), the 4th PMOS tube (MP4) and the 5th PMOS tube (MP5) And connect supply voltage (VDD)；

The grid of second PMOS tube (MP2) connects the inversion signal (EN_N) of the enable signal (EN), drain electrode connection the 4th The drain electrode of PMOS tube (MP4) and the 6th NMOS tube (MN6) and the grid of the 5th PMOS tube (MP5) and the 7th NMOS tube (MN7)；

6th NMOS tube (MN6) connects the negative voltage (VDDN) with the source electrode of the 7th NMOS tube (MN7)；

The output module (60) includes the 6th PMOS tube (MP6) and the 8th NMOS tube (MN8),

The grid of 6th PMOS tube (MP6) connects the grid of the 8th NMOS tube (MN8) and connects the defeated of the clamper module (10) Outlet, source electrode connect ground voltage (VSS), and the drain electrode of drain electrode the 8th NMOS tube (MN8) of connection simultaneously exports the DC-DC circuit Output signal；

The source electrode of 8th NMOS tube (MN8) connects the negative voltage (VDDN).

4. according to claim 1 for generating the DC-DC circuit of negative pressure, which is characterized in that the first switch tube It (S1) include the 7th PMOS tube (MP7), the second switch (S2) includes the 8th PMOS tube (MP8), the third switching tube It (S3) include the 9th PMOS tube (MP9), the 4th switching tube (S4) includes the tenth PMOS tube (MP10)；

The grid of 7th PMOS tube (MP7) connects the described first just non-overlapping clock signal (CLK_P1), and source electrode connects power supply Voltage (VDD), the source electrode of drain electrode the 8th PMOS tube (MP8) of connection；

The grid of 8th PMOS tube (MP8) connects the described second just non-overlapping clock signal (CLK_P2), drain electrode connection ground electricity It presses (VSS)；

The grid of 9th PMOS tube (MP9) connects the first negative non-overlapping clock signal (CLK_N1), source electrode connection ground electricity It presses (VSS), the source electrode of drain electrode the tenth PMOS tube (MP10) of connection；

The grid of tenth PMOS tube (MP10) connects the second negative non-overlapping clock signal (CLK_N2), drains described in output Negative voltage (VDDN)；

First capacitor (C1) connects between the 8th PMOS tube (MP8) and the source electrode of the tenth PMOS tube (MP10), the second capacitor (C2) It connects between the 8th PMOS tube (MP8) and the drain electrode of the tenth PMOS tube (MP10).