CN108803418A - A kind of AD automated collection systems that FPGA is realized - Google Patents

Abstract

The invention discloses an AD automatic acquisition system realized by FPGA, which includes CPU, FPGA, SRAM and several A/D conversion circuits; several A/D conversion circuits, CPU and SRAM are respectively connected with FPGA; SRAM is used to store the acquisition configuration table and the collection data storage table, the CPU stores the sampling configuration information in the SRAM, the FPGA reads the configuration information to control the collection process, and writes the results collected by several A/D conversion circuits into the SRAM, and the CPU reads the collected data from the SRAM result. The invention adopts software dynamic configuration realization and AD automatic acquisition, and realizes an efficient and flexible AD acquisition system.

Description

An FPGA Realized AD Automatic Acquisition System

technical field

The invention relates to the field of aerospace vehicle electronics, in particular to an FPGA-realized AD automatic acquisition system.

Background technique

In on-board electronic products, analog sampling is an essential function, and the demand for analog sampling channels is increasing. At present, the "single chip + AD" and "FPGA + AD" schemes are mostly used to realize. In the "single chip + AD" scheme, the AD channel switching and AD sampling control are all controlled by the single chip microcomputer. Since the single chip microcomputer runs sequentially and the software controls the AD sampling timing, it is impossible to realize multiple At the same time, the amount of channel data collected by AD is limited by the operating speed of the single-chip microcomputer. The "FPGA+AD" solution can realize multi-channel simultaneous acquisition, but the current FPGA design is relatively fixed, lacks application flexibility, and has a certain dependence on the CPU.

Contents of the invention

In order to meet the large-scale analog quantity acquisition requirements of the on-board computer, reduce the occupation of software running time, and improve the utilization efficiency of the CPU, the present invention proposes an AD automatic acquisition system implemented by FPGA.

The technical scheme adopted in the present invention is:

A kind of AD automatic acquisition system that FPGA realizes, comprises CPU, FPGA, SRAM and some A/D conversion circuits; Some described A/D conversion circuits, described CPU and described SRAM are respectively connected with described FPGA; Described SRAM Used to store the acquisition configuration table and the acquisition data storage table, the CPU stores the sampling configuration information in the SRAM, the FPGA reads the configuration information to control the acquisition process, and stores the results collected by several of the A/D conversion circuits written into the SRAM, and the CPU reads the collected results from the SRAM.

Preferably, the A/D conversion circuit includes an A/D conversion chip and several analog switches; several of the analog switches, the A/D conversion chip, the CPU and the SRAM are respectively connected to the FPGA, Some of the analog switches are respectively connected to the A/D conversion chip; some of the analog switches are used to gate under the control of the FPGA to receive an externally input analog quantity, and then the A/D conversion chip is in the Under the control of the FPGA, the analog quantity is converted into a digital quantity, and the converted data is stored in the SRAM.

Preferably, the FPGA includes CPU access control logic, registers, SRAM access arbitration logic, SRAM access control logic, timer, A/D conversion chip control logic, analog switch switching control logic and main control logic; the CPU access The control logic is in order to realize the mapping of the CPU address to the SRAM and the FPGA internal register storage space, and realize the timing matching of the SRAM access arbitration logic and the CPU access control logic; the SRAM access control logic is used for The timing control of the SRAM read and write access; the timer is used to maintain the large cycle of the automatic acquisition system and the small cycle of the single-channel analog acquisition according to the setting of the register, which is provided to the main control logic; the A/ The D conversion chip control logic is used to control the sampling conversion process of the A/D conversion chip and the acquisition of collection results; the analog switch switching control logic is used for multi-channel analog quantity selection.

Preferably, the registers include a control register and a status register; the control register is used to set a large sampling period, a single-channel sampling period and an interrupt mode; the status register is used to represent the current operating status of the system.

Preferably, the SRAM includes two partitions, respectively storing the collection configuration table and the collection data storage table; there is a reserved space between the storage areas of the collection configuration table and the collection data storage table for subsequent expansion .

Preferably, each acquisition channel in the acquisition configuration table corresponds to an SRAM address, and the order of the acquisition channels corresponds to the order of the SRAM addresses; each acquisition data in the acquisition data storage table corresponds to an SRAM address, and the acquisition channel The order of corresponds to the order of the SRAM address.

The beneficial effects that the present invention realizes are:

The present invention starts from improving the automation degree of AD collection function, adopts FPGA realization technology, realizes the automatic collection function of multi-channel AD, reduces the dependence of the AD collection process on the CPU, and at the same time samples the tabular control logic, endows the application of the AD collection system flexibility.

Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

Fig. 1 is the logic block diagram of the hardware composition of the AD automatic acquisition system that a kind of FPGA realizes of an embodiment of the present invention;

Fig. 2 is the FPGA internal logic block diagram of an embodiment of the present invention;

FIG. 3 is a logical relationship diagram between the collection configuration table, the collection data storage table and the SRAM according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, various embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 1 is a logical diagram of the hardware composition of the system of the present invention, and the logical block diagram takes three groups of ADs as an example. The externally input analog quantity is input to the analog switch, and the analog switch is selected under the control of the FPGA (multiple choice 1, such as 8 choice 1, 16 choice 1), the analog quantity is input to the AD conversion chip, and the AD conversion chip is controlled by the FPGA. Analog-to-digital conversion of the analog quantity, and store the converted data in the SRAM. Each AD conversion chip is used in conjunction with multiple analog switches, making full use of the AD conversion chip and increasing the number of channels that can be collected. SRAM is the cache of this system, which is used to store the acquisition configuration table and the acquisition data storage table. The CPU stores the sampling configuration information in the SRAM, the FPGA reads the configuration information to control the acquisition process, and writes the acquired results into the SRAM, and the CPU then Read the collected results from SRAM.

Figure 2 is the internal logic block diagram of the FPGA. The FPGA is mainly composed of CPU access control logic, registers (control registers, status registers), SRAM access arbitration logic, SRAM access control logic, timers, AD conversion chip control logic, and analog switch switching control logic. And the main control logic composition. The CPU access control logic realizes the mapping of the CPU address to the storage space such as SRAM and FPGA internal registers, and realizes the timing matching between the SRAM access arbitration logic and the CPU access logic. When the SRAM is not idle, the CPU access is delayed. Registers are the control registers and status registers maintained by the FPGA. The control registers are used to set the sampling period and single-channel sampling period, as well as the interrupt mode; the status registers are used to represent the current operating status of the system, such as busy/idle status. The SRAM access arbitration logic implements priority control and access selection for SRAM access, assigns access rights to SRAM access from multiple sources at the same time according to the priority order, and realizes orderly control of SRAM access. The SRAM access control logic mainly realizes the timing control of SRAM read and write access. The timer maintains the large cycle of the automatic acquisition system and the small cycle of single-channel analog acquisition according to the setting of the control register, and provides it to the main control logic to realize the periodic operation of the entire system. The control logic of the AD conversion chip controls the sampling conversion process of the AD conversion chip and the acquisition of the collection results. Analog switch switching control logic realizes multi-channel analog selection. The main control logic realizes the periodical operation of the whole system according to the timer.

Figure 3 shows the logical relationship between the acquisition configuration table and the acquisition data storage table and the SRAM, which describes the storage of the configuration table and the acquisition data storage table in the SRAM. There is a certain amount of reserved space between the table storage area and the collection data storage table storage area, and the user can expand it later. Each acquisition channel in the acquisition configuration table corresponds to a SRAM address, the order of acquisition channels corresponds to the order of SRAM addresses, each acquisition data in the acquisition data storage table corresponds to an SRAM address, and the order of acquisition channels corresponds to the order of SRAM addresses , the end of the collection data storage table is represented by specific characters. Each item in the collection data storage table is the data collected for a single time, and each item in the collection configuration table is the single collection channel and the collection times of the collection channel, so the collection data storage table items are larger than the collection configuration table, only when each collection When the number of acquisitions of the channel is set to 1, the items of the two are the same.

The core of this system lies in the realization of software dynamic configuration and AD automatic acquisition. The system design implements two tables, which are the collection configuration table and the collection data storage table. The acquisition configuration table stores the channel number of analog acquisition in a single cycle and the number of single-channel analog acquisition, and the channel number of analog acquisition is stored in the table in order of the sampling position of the channel in the cycle. Both the collection configuration table and the collection data storage table are stored in the system cache SRAM. Before system acquisition, the software designs the acquisition configuration table, writes the channel numbers that need to collect analog quantities into the acquisition configuration table in order, and can set the number of single-cycle acquisitions as required. The first channel to be collected is placed in the first line of the configuration table, the last channel to be collected is placed in the penultimate line of the configuration table, and the last line stores a special end line, which is used to mark the end of the configuration table. The collected data storage table is a table composed of collected data stored in the order of collection, including collected data and collection update status. The collection update status indicates whether the current data is the latest data collected in this cycle at the current moment. The collection update status is passed through a single bit To define, when the data is updated, the last flag is reversed, that is, when the last flag is 1, the collection update status flag of the updated data in this cycle is set to 0. After the software starts the acquisition, the FPGA reads the information in the acquisition configuration table line by line, controls the analog channel switching and AD sampling, and writes the acquired data into the acquisition data storage table. The data storage order is consistent with the order in the configuration table.

The implementation of AD automatic acquisition includes analog switch switching timing control, AD acquisition timing control, and SRAM timing control to ensure that each device can work normally. FPGA reads the information sampling channel number and sampling times of the acquisition configuration table, controls channel switching, controls the AD chip to complete the analog-to-digital conversion according to the timing requirements, FPGA reads the conversion result and writes the result into the SRAM memory. The sampling sequence is carried out according to the channel storage order in the acquisition configuration table. After all channel acquisitions are completed, an interrupt is sent to inform the CPU. AD automatic acquisition adopts period management. Period management mainly realizes system period management and single-channel acquisition period management. The acquisition of all channels in the acquisition configuration table is completed within the system period. The single-channel acquisition period is the time for a single acquisition of a single channel. SRAM access includes CPU configuration table write access, CPU acquisition data read access, CPU acquisition data status access, FPGA configuration table read access, FPGA acquisition data write access, etc. The arbitration logic is designed with priority control to ensure that each Such access can be successfully responded to. The interrupt logic completes the output of the interrupt, and sends an interrupt to inform the CPU when the data collection in the system cycle is completed. The implementation of AD automatic acquisition is mainly completed by logic control such as period management, timing control, arbitration management, and interrupt logic. Periodic work is performed according to the configuration register, and the work status is fed back in the status register.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (6)

1. the AD automated collection systems that a kind of FPGA is realized, which is characterized in that converted including CPU, FPGA, SRAM and several A/D Circuit；Several A/D conversion circuits, the CPU and the SRAM are connect with the FPGA respectively；The SRAM is for storing Acquisition configuration table and acquired data storage table, the CPU are stored in configuration information is sampled in the SRAM, and the FPGA is read Configuration information controls gatherer process, and the result of several A/D conversion circuits acquisitions is written in the SRAM, the CPU The result of acquisition is read from the SRAM again.

2. the AD automated collection systems that a kind of FPGA according to claim 1 is realized, which is characterized in that the A/D conversions Circuit includes A/D conversion chips and several analog switches；Several analog switches, the A/D conversion chips, the CPU and The SRAM is connect with the FPGA respectively, and several analog switches are connect with the A/D conversion chips respectively；It is several described Analog switch under the FPGA controls gating receive externally input analog quantity, and then the A/D conversion chips exist Analog quantity is converted into digital quantity under the FPGA controls, and transformed data are stored in the SRAM.

3. the AD automated collection systems that a kind of FPGA according to claim 2 is realized, which is characterized in that the FPGA includes CPU access control logics, register, SRAM access arbitrations logic, SRAM access control logics, timer, A/D conversion chip controls Logic, analog switch switch control logic and main control logic processed；The CPU access control logics are realizing to cpu address To the mapping of the SRAM and the FPGA internal registers memory space, and realize described in the SRAM access arbitrations logical AND The sequential coupling of CPU access control logics；The SRAM access control logics are for the sequential control to the SRAM read and write access System；The timer is used to safeguard what the large period of automated collection systems and single analog acquired according to the setting of the register Minor cycle is supplied to the master control logic；The A/D conversion chips control logic is for controlling adopting for the A/D conversion chips The acquisition of sample transfer process and collection result；The analog switch switch control logic is selected for multi-analog.

4. the AD automated collection systems that a kind of FPGA according to claim 3 is realized, which is characterized in that the register packet Include control register and status register；The control register for be arranged sampling large period, the single-channel sampling period and in Disconnected mode；The status register is used to characterize the operating status of current system.

5. the AD automated collection systems that a kind of FPGA according to claim 1 is realized, which is characterized in that the SRAM includes Two subregions store acquisition configuration table and acquired data storage table respectively；The acquisition configuration table and the acquired data storage There is reserved space between the memory block of table, be used for subsequent extension.

6. the AD automated collection systems that a kind of FPGA according to claim 5 is realized, which is characterized in that the acquisition configuration An address SRAM is corresponded to per acquisition channel all the way in table, the sequence of acquisition channel is corresponding with the sequence of the addresses SRAM；It is described Gathered data each time in acquired data storage table corresponds to an address SRAM, and the sequence of acquisition channel is suitable with the addresses SRAM Ordered pair is answered.