CN108763760B - System-level chip based on two-stage BOOT structure - Google Patents
System-level chip based on two-stage BOOT structure Download PDFInfo
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- CN108763760B CN108763760B CN201810533154.5A CN201810533154A CN108763760B CN 108763760 B CN108763760 B CN 108763760B CN 201810533154 A CN201810533154 A CN 201810533154A CN 108763760 B CN108763760 B CN 108763760B
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Abstract
The invention discloses a system-level chip based on a two-stage BOOT structure, which comprises a memory controller, wherein the memory controller is connected with a processor through an on-chip bus, and the on-chip bus is connected with an on-chip ROM; the memory controller is connected with a first memory area and a second memory area; the memory area one comprises a serial PROM and a parallel MRAM, and the memory controller accesses the serial PROM or the parallel MRAM at the same time; the second storage area is a parallel SRAM; wherein, the on-chip ROM stores a first BOOT instruction, and the processor accesses the content stored by the on-chip ROM; the first storage area stores a second BOOT instruction and a user program; wherein the processor is accessed to a BOOTSEL control pin; the memory controller accesses the ROMSEL control pin. A hardware control mode is adopted to select a power-on reset starting address and an accessed off-chip memory type, and three power-on starting modes of a system-on-chip are realized based on a two-stage BOOT structure.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design; in particular to a system-on-chip based on a two-stage BOOT structure.
Background
The conventional SoC power-on starting mainly adopts two methods: firstly, a random-readable nonvolatile device is externally connected to the SoC to serve as a program memory, and the SoC directly reads an instruction execution program from the program memory after power-on reset; secondly, the SoC divides the memory including the on-chip memory and the off-chip memory into three areas, namely a BOOT area, a program memory area and a program execution area, the SoC executes instructions in the BOOT area after power-on reset to transfer the contents of the memory area to the execution area, and then jumps to the program execution area to execute the user program.
Among the two methods, the first method is suitable for the situation that the SoC is externally connected with a FLASH or MRAM and other random-readable memories as a program area, the random-readable memories support the SoC to control random reading through addresses, and the SoC can directly read instruction execution programs from the memory banks. The second method is mostly used for the situation that a non-random readable memory such as an SoC external serial PROM is used as a program storage area, the memory has no address input, only can serially output data according to an input clock, and a processor cannot randomly fetch a finger to access the memory, so that a program in the program storage area can be carried to other program execution areas which can randomly fetch the finger only through a BOOT guiding mechanism in a chip, and loading and starting are realized. In order to meet various application requirements, designers often set a program in the BOOT region to transfer a program with a fixed size in an external program storage region (generally, the amount of data to be transferred is set according to the size of the largest program of an application in order to cover various application requirements) to a program execution region, which is inefficient and inflexible.
The two methods can solve the application requirements of the chip under certain conditions, but both methods have certain limitations and disadvantages. In some cases, a user needs the SoC to support multiple power-on starting modes, for example, in the case of a space application SoC, the user stores programs and data in a serial or parallel nonvolatile memory bank when the SoC is used in a space environment, the power-on starting is completed by BOOT loading after the SoC is reset, and based on reliability of space use and consideration of program backup, a chip is generally required to support multiple BOOT modes and store chip programs in different memory banks. When the chip is subjected to ground debugging, a more direct and efficient NOBOOT direct execution mode is generally used. Under different application scenarios, a user needs the SoC to support multiple BOOT loading modes and power-on starting modes, and needs a more efficient and flexible BOOT loading mode to facilitate use.
At present, a plurality of patents for researching the BOOT method exist, however, no design structure compatible with serial memory BOOT loading, parallel memory BOOT loading and NOBOOT direct execution mode exists at present.
Disclosure of Invention
The invention provides a system-level chip based on a two-stage BOOT structure; a hardware control mode is adopted to select a power-on reset starting address and an accessed off-chip memory type, and three power-on starting modes of a system-on-chip are realized based on a two-stage BOOT structure.
The technical scheme of the invention is as follows: a system-level chip based on a two-level BOOT structure comprises a memory controller, wherein the memory controller is connected with a processor through an on-chip bus, and the on-chip bus is connected with an on-chip ROM; the memory controller is connected with a first memory area and a second memory area; the memory area one comprises a serial PROM and a parallel MRAM, and the memory controller accesses the serial PROM or the parallel MRAM at the same time; the second storage area is a parallel SRAM; wherein, the on-chip ROM stores a first BOOT instruction, and the processor accesses the content stored by the on-chip ROM; the first storage area stores a second BOOT instruction and a user program; wherein the processor is accessed to a BOOTSEL control pin; the memory controller accesses the ROMSEL control pin.
Furthermore, the invention is characterized in that:
the system chip realizes the power-on starting mode as follows: the power-on starting is realized by the parallel MRAM, the on starting is realized by the on-chip ROM and the parallel MRAM, or the on starting is realized by the on-chip ROM and the serial PROM.
A first-level BOOT controller is arranged between the on-chip bus and the on-chip ROM, and the processor accesses the content stored in the on-chip ROM through the first-level BOOT controller.
Wherein the processor is connected to the on-chip bus through the cache memory.
The memory controller comprises an address decoding unit connected with an on-chip bus; the address decoding unit is connected with a second storage area through a second storage area controller; the address decoding unit is connected with a first storage area controller through a selection switch, and the first storage area controller is connected with a first storage area.
The first storage area controller comprises a serial PROM controller and a parallel memory controller which are respectively connected with the serial PROM and the parallel MRAM.
The system chip is a DSP chip, an MCU chip or an SoC chip.
Compared with the prior art, the invention has the beneficial effects that: the system-level chip has on-chip storage and off-chip storage, and can realize three power-on starting modes through two-stage BOOT instruction setting, thereby meeting the requirements of various applications.
Furthermore, the on-chip ROM solidifies the first BOOT instruction and the off-chip storage area I realizes that the off-chip storage and the on-chip storage together complete the program loading of the system level chip, and the size of the program carried by the off-chip storage area I can be adjusted flexibly according to the practical application, so that the method is more efficient and flexible. The off-chip storage direct execution starting mode saves the process of program carrying, saves time for simulation verification and chip testing links, and improves the verifiability and testability of the chip.
Furthermore, the technical scheme has better portability and universality, and can be applied to various chips with architectures such as DSP chips, MCU chips, SoC chips and the like.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a diagram illustrating a processor selecting a boot address according to the present invention;
FIG. 3 is a diagram illustrating a memory controller according to the present invention.
Detailed Description
The technical solution of the present invention is further explained with reference to the accompanying drawings and specific embodiments.
The invention provides a system-level chip based on a two-level BOOT structure, which comprises a memory controller, wherein the memory controller is connected with an on-chip bus, a cache memory (cache) is arranged between the on-chip bus and a processor, and a first-level BOOT controller is arranged between the on-chip bus and an on-chip ROM; the memory controller is connected with a first external memory area and a second external memory area, wherein the first memory area comprises a serial PROM and a parallel MRAM, and the memory controller can only access one of the first and second external memory areas at the same time; and the second storage area is a parallel SRAM. The processor is connected to a BOOTSEL control pin, and the memory controller is connected to a ROMSEL control pin.
As shown in fig. 3, the memory controller includes an address decoding unit connected to the on-chip bus, and the address decoding unit is connected to the parallel SRAM memory (memory area two) through the memory area two controller; the address decoding unit is connected with a selection switch, the selection switch is connected with the serial PROM through the serial PROM, and the selection switch is also connected with the parallel MRAM through the parallel memory controller. Wherein the ROMSEL control pin is connected to the selection switch.
The working principle of the invention is as follows: as shown in fig. 2, the processor determines the first address of the fetch after power-on reset according to the input of the external pin BOOTSEL. When the BOOTSEL is 0, the starting address is the first address of the first storage area after the processor is reset, and when the BOOTSEL is 1, the starting address after the processor is reset is the first address of the ROM in the chip.
As shown in fig. 3, the memory controller access space is divided into two parts, a first memory area and a second memory area, the first memory area supports access control of two types of memory banks, the type of the currently accessed memory bank is selected by the ROMSEL, the ROMSEL of 0 indicates that the parallel MRAM is currently selected to be accessed, and the ROMSEL of 1 indicates that the serial PROM is currently selected to be accessed. In the serial mode, a serial PROM externally connected with the memory area stores a secondary BOOT instruction and a user program. In the parallel mode, a parallel MRAM externally connected to the storage area can only store a user program, and the parallel mode corresponds to the parallel execution mode; the parallel MRAM can also store a secondary BOOT instruction and a user program, in this case corresponding to a parallel load mode. The second BOOT instruction as data stored in the off-chip memory bank can be programmed by a user, and the user determines the content of the second BOOT instruction according to actual application. And the second storage area is externally connected with a parallel storage body and used as a program execution area in serial and parallel loading modes.
Because the serial RROM can not be used as a program area, the system-on-chip of the invention has three power-on starting modes: the storage areas are parallel MRAM (namely, program direct execution), on-chip ROM and parallel MRAM (BOOT parallel loading) and on-chip ROM and serial PROM (BOOT serial loading).
The on-chip ROM is used as an internal curing storage area of the system chip and stores a first-level BOOT instruction, the first-level BOOT instruction is on-chip curing content, and the processor accesses the content of the on-chip ROM through a first-level BOOT controller. The first-level BOOT instruction has the following functions: and the processor executes the first-level BOOT instruction, carries the data (second-level BOOT instruction) with fixed size in the first storage area to the second storage area, and jumps to the first address of the second storage area to start executing the second-level BOOT instruction.
The secondary BOOT instruction is programmed by a user, and the user can program according to actual application requirements. And the processor executes a second BOOT instruction written by a user, carries the user program from the configuration address in the first storage area to the second parallel storage area, jumps to execute the user program, and the system-level chip finishes program BOOT and starts to work.
In the first power-on starting mode, after power-on reset, the processor directly reads the instruction from the external parallel MRAM in the storage area, and executes the user program.
In the second power-on starting mode, after the system-level chip is powered on and reset, the first-level BOOT program is executed by starting to fetch the instruction from the first address of the ROM in the chip, and as a result, the second-level BOOT instruction is transferred from the parallel MRAM externally connected to the first storage area of the chip to the second storage area, then the second-level BOOT program is executed to finish the transfer of the user program from the parallel memory externally connected to the first storage area to the second storage area, and finally the user program is executed in the second storage area
In the third power-on starting mode, after the processor is powered on and reset, the processor starts to point out from the first address of the ROM in the chip to execute the first-level BOOT program, the execution result is that the second-level BOOT instruction is transported from the serial PROM of the first memory area of the chip to the second memory area, then the second-level BOOT program is executed to finish the transportation of the user program from the serial PROM of the first memory area to the second memory area, and then the user program is executed in the second memory area.
The first-level BOOT controller receives an access request of the processor through the on-chip bus, reads corresponding content from the on-chip ROM and returns the corresponding content to the processor. Based on the structure of the invention, in the chip design stage, a designer determines the content of the first-level BOOT instruction according to the evaluation of the system-level chip application condition. According to the two-stage BOOT mechanism adopted by the invention, the first-stage BOOT only needs to carry data which can cover the address range of the second-stage BOOT instruction, and the size and the storage address of the user program are determined by the second-stage BOOT. After the chip is realized, the first-level BOOT instruction is solidified, and as long as the loading mode is selected for starting, the chip executes the first-level BOOT instruction from the ROM area in the chip after each power-on reset, so that the power-on starting is completed.
The system-level chip can be applied to various types and architectures of chips such as a DSP chip, an MCU chip, an SoC chip and the like, and has better portability and universality.
The invention is applied to the SoC chip compatible with the SPARC V8 framework processor, the SoC chip uses the on-chip BOOT control structure provided by the invention, not only can meet various application requirements and the reliability requirements of the chip, but also improves the starting efficiency and flexibility of the chip under the BOOT serial loading mode, and in addition, the verification efficiency is greatly improved by adopting an NOBOOT direct execution mode in the simulation verification stage of the chip. The SoC chip finishes the stream chip, the BOOT control structure has normal functions, and the three power-on starting modes run normally. The design structure provided by the invention has higher portability and reusability.
Claims (6)
1. A system-level chip based on a two-level BOOT structure is characterized by comprising a memory controller, wherein the memory controller is connected with a processor through an on-chip bus, and the on-chip bus is connected with an on-chip ROM; the memory controller is connected with a first memory area and a second memory area; the storage area one comprises a serial PROM and a parallel MRAM, and the memory controller can only access the serial PROM or the parallel MRAM at the same time; the second storage area is a parallel SRAM;
wherein, the on-chip ROM stores a first BOOT instruction, and the processor accesses the content stored by the on-chip ROM;
the first storage area stores a second BOOT instruction and a user program;
wherein the processor is accessed to a BOOTSEL control pin; the memory controller is connected to a ROMSEL control pin;
the system-level chip realizes the power-on starting mode as follows: the power-on starting is realized by the parallel MRAM, the on starting is realized by the on-chip ROM and the parallel MRAM, or the on starting is realized by the on-chip ROM and the serial PROM.
2. The system-on-chip based on two-level BOOT structure according to claim 1, wherein a one-level BOOT controller is disposed between the on-chip bus and the on-chip ROM, and the processor accesses the content stored in the on-chip ROM through the one-level BOOT controller.
3. The two-level BOOT structure based system-on-chip of claim 1, wherein the processor is connected to an on-chip bus through a cache memory.
4. The two-level BOOT structure based system-on-chip of claim 1, wherein the memory controller comprises an address decoding unit connected with an on-chip bus; the address decoding unit is connected with a second storage area through a second storage area controller; the address decoding unit is connected with a first storage area controller through a selection switch, and the first storage area controller is connected with a first storage area.
5. The two-level BOOT architecture based system-on-chip of claim 4, wherein the memory area-controller comprises a serial PROM controller and a parallel memory controller, and connects the serial PROM and the parallel MRAM, respectively.
6. The two-stage BOOT structure-based system-on-chip of claim 1, wherein the system-on-chip is a DSP chip, an MCU chip or an SoC chip.
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| CN110633223B (en) * | 2019-09-18 | 2021-07-13 | 北京机电工程研究所 | Multi-level memory management method for high-speed signal platform |
| CN112256338B (en) * | 2020-10-27 | 2023-12-05 | 记忆科技(深圳)有限公司 | SOC starting method and device, computer equipment and storage medium |
| CN113535248B (en) * | 2021-06-24 | 2024-05-28 | 合肥松豪电子科技有限公司 | TP chip power-on starting method for reducing SRAM space |
| CN117193887B (en) * | 2023-11-06 | 2024-03-15 | 深圳市优特杰科技有限公司 | Mixer distributed control method, device and readable storage medium |
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