CN108573677A - Control signal drive circuit and driving method and pixel circuit drive method - Google Patents
Control signal drive circuit and driving method and pixel circuit drive method Download PDFInfo
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- CN108573677A CN108573677A CN201710132445.9A CN201710132445A CN108573677A CN 108573677 A CN108573677 A CN 108573677A CN 201710132445 A CN201710132445 A CN 201710132445A CN 108573677 A CN108573677 A CN 108573677A
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- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 7
- 101100003180 Colletotrichum lindemuthianum ATG1 gene Proteins 0.000 description 6
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 3
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 3
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 3
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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Abstract
A kind of control signal drive circuit of present invention offer and driving method and pixel circuit drive method, the control signal drive circuit includes the first transistor to the 9th transistor, the first capacitance and the second capacitance, wherein, external circuit provides the first clock signal, second clock signal, high power supply voltage, low supply voltage and input signal to the control signal drive circuit, control signal of the final output with high level and with low level output signal；The structure of the control signal drive circuit is simple, the output that control signal is realized using a small amount of transistor and capacitance, is convenient for integrated realization, is conducive to the yield for improving screen body, and the operation is stable of the driving circuit improves the output stability of control signal.
Description
Technical field
The present invention relates to plane display fields, and in particular to a kind of control signal drive circuit and driving method and pixel
Circuit drive method.
Background technology
Organic light emitting display (Organic Light Emitting Display, OLED) can be divided into nothing in a driving manner
Source (Passive Matrix, PMOLED) and active (Active Matrix, AMOLED).And active organic electroluminescent display device part
(AMOLED), that is, thin film transistor (TFT) (Thin Film Transistor, TFT) collocation capacitance (Capacitor) is utilized to store letter
Number, to control the intensity gray scale performance of OLED.Compared to present mainstream flat panel display Thin Film Transistor-LCD
(TFT-LCD), displayer has many advantages, such as high contrast, wide viewing angle, low-power consumption, thinner.
Different pixel circuits needs different driver' s timing signals, such as 2T1C (2 in conventional organic light emitting display
1 capacitance of thin film transistor (TFT)) pixel circuit, it is only necessary to scanning (Scan) drive signal, and general pixel compensation circuit claim
Make mTnC (containing m thin film transistor (TFT), n capacitance) pixel circuit, then needs several scanning drive signals and several controls
Signal processed is worked in coordination by certain sequential, to make up the defect of technique, improves the consistency that screen body is shown.
The existing driving circuit structure for generating control signal is all more complicated, as shown in Figure 1, it is in the prior art
Control the structural schematic diagram of signal drive circuit, including 15 thin film transistor (TFT)s (M1 to M11 and M44, M55, M88 and M99)
With 5 capacitances (C1 to C5), and it also requires multiple signals, such as input signal IN, high power supply voltage signal VGH, low power supply
Voltage signal VGL, three clock signals CK1, CK2 and CK3, reset signal Reset, final output controls signal and output is believed
Number OUT1, input signals of the OUT1 as next stage drive circuit.
The driving circuit it is complicated, the thin film transistor (TFT) of use and the quantity of capacitance are relatively more, and need
Input signal also compares more, it is easy to cause the unstable of output signal.And if the driving circuit is integrated in organic hair
In the screen body of optical display unit, the area of occupancy screen body that can be excessive influences the yield for shielding body output, and be unfavorable for the section of cost
About.
Therefore, it is this field that a kind of control signal drive circuit simple in structure of design provides control signal to pixel circuit
The technical issues of technical staff's urgent need to resolve.
Invention content
The purpose of the present invention is to provide a kind of control signal drive circuits and driving method and pixel circuit driving side
Method, simplify control signal drive circuit provide stable control signal.
To achieve the above object, the present invention provides a kind of control signal drive circuit, including the first transistor is to the 9th crystalline substance
Body pipe, the first capacitance and the second capacitance, wherein
The grid of the grid of the first transistor and the 4th transistor is connected to one first clock signal terminal, and described first
The first electrode of transistor is connected to an input signal end, the second electrode of the first transistor and the grid of second transistor
It is connected to a first node；
The second electrode of the second transistor is connected to a second clock signal end；First electricity of the second transistor
Pole, the grid of third transistor, the first electrode of the 5th transistor, the grid of the 6th transistor, the 7th transistor grid with
The grid of 8th transistor is connected to a second node；
The grid of the first electrode of the third transistor, the second electrode and the 5th transistor of the 4th transistor
Pole is connected, the second electrode of the third transistor, the second electrode of the 5th transistor, the 6th transistor
The second electrode of two electrodes and the 8th transistor is connected to one first power supply voltage signal end；
First electricity of the first electrode of the 4th transistor, the first electrode of the 7th transistor and the 9th transistor
Pole is connected to a second source voltage signal end；The first electrode of 6th transistor, the second electricity of the 7th transistor
Pole, the 9th transistor grid be connected with one end of second capacitance, the first electrode of the 8th transistor, institute
The second electrode for stating the 9th transistor and the other end of second capacitance are connected to a control signal end；
First capacitance connection is between the second node and first node.
Optionally, further include the tenth transistor and the 11st transistor, the grid of the tenth transistor is connected to first
The first electrode of clock signal terminal, the tenth transistor is connected to input signal end, the second electrode of the tenth transistor
It is connected with the first electrode of the 11st transistor, the grid of the 11st transistor is connected to second clock signal
End, the second electrode of the 11st transistor are connected to first node.
Optionally, further include third capacitance and the 4th capacitance, one end of the third capacitance and the one of the 4th capacitance
End is connected to first power supply voltage signal end, and the other end of the third capacitance is connected to second node, the 4th electricity
The other end of appearance is connected to the second electrode of the tenth transistor.
Optionally, the second node is connected to output signal end.
Optionally, the first electrode is source electrode, and the second electrode is drain electrode；Alternatively, the first electrode is drain electrode,
The second electrode is source electrode.
Optionally, the driver' s timing of the driving circuit includes first stage, second stage and phase III；In the first rank
Section, input signal are low level with the first clock signal, and second clock signal is high level；In second stage, the input letter
Number with first clock signal be high level, the second clock signal be low level, export a high level control signal
An and low level output signal；In the phase III, first clock signal be low level, the input signal with it is described
Second clock signal is the output signal of high level, one low level control signal of output and a high level.
Optionally, in second stage, the output signal controls the input signal of signal drive circuit as next stage.
Correspondingly, the present invention also provides a kind of driving methods of control signal drive circuit, using control as described above
Signal drive circuit generates control signal, including：
First stage：Input signal end provides input signal, and the voltage of the first node is low level；
Second stage：The second clock signal is low level, and the voltage of the first node is less than 2 times of second source
Voltage, output signal end export low level output signal, while the control signal of control signal end output high level；
Phase III：First clock signal is low level, and the input signal is height with the second clock signal
Level, output signal end export the output signal of high level, while the control signal of control signal end output high level.
Optionally, the output signal of second stage controls the input signal of signal drive circuit as next stage
Correspondingly, the present invention also provides a kind of driving method of pixel circuit, using control signal driving as described above
Circuit provides control signal.
Compared with prior art, control signal drive circuit provided by the invention drives with driving method and pixel circuit
Method simplifies the structure of control signal drive circuit, and the defeated of control signal is realized using a small amount of transistor and capacitance
Go out, be convenient for the realization of circuit integration, is conducive to the yield for improving screen body, and the operation is stable of the driving circuit, improves
Control the output stability of signal.
Description of the drawings
Fig. 1 is the structural schematic diagram of control signal drive circuit in the prior art；
The structural schematic diagram for the control signal drive circuit that Fig. 2 is provided by one embodiment of the invention；
Fig. 3 is the signal timing diagram of control signal drive circuit shown in Fig. 2.
Specific implementation mode
To keep present disclosure more clear and easy to understand, below in conjunction with Figure of description, present disclosure is done into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replacement well known to the skilled artisan in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when present example is described in detail, for the ease of saying
Bright, schematic diagram is not partially enlarged in proportion to the general scale, should not be in this, as the restriction of the present invention.
The structural schematic diagram for the control signal drive circuit that Fig. 2 is provided by one embodiment of the invention, as shown in Fig. 2, this
Invention proposes a control signal drive circuit, including the first transistor M1 to the 9th transistor M9, the first capacitance C1 and the second electricity
Hold C2, wherein the grid of the first transistor M1 and the grid of the 4th transistor M4 are connected to one first clock signal terminal
The first electrode of CLK1, the first transistor M1 are connected to an input signal end IN, the second electricity of the first transistor M1
Pole and the grid of second transistor M2 are connected to a first node N；The second electrode of the second transistor M2 is connected to one
Two clock signal terminal CLK2；The first electrode of the second transistor M2, the grid of third transistor M3, the 5th transistor M5
First electrode, the grid of the 6th transistor M6, the grid of the 7th transistor M7 and the 8th transistor M8 grid be connected to one
Two node Ms；The first electrode of the third transistor M3, the second electrode of the 4th transistor M4 and the 5th transistor
The grid of M5 is connected, the second electrode of the third transistor M3, the second electrode of the 5th transistor M5, the described 6th
The second electrode of transistor M6 and the second electrode of the 8th transistor M8 are connected to one first power supply voltage signal end VGH；
The first electrode of the first electrode of the 4th transistor M4, the first electrode and the 9th transistor M9 of the 7th transistor M7
It is connected to a second source voltage signal end VGL；The of the first electrode of the 6th transistor M6, the 7th transistor M7
Two electrodes, the 9th transistor M9 grid be connected with one end of the second capacitance C2, the 8th transistor M8's
First electrode, the second electrode of the 9th transistor M9 and the other end of the second capacitance C2 are connected to control signal end
EM；The first capacitance C1 is connected between the second node M and first node N.
The control signal drive circuit further includes the tenth transistor M10 and the 11st transistor M11, the tenth crystal
The grid of pipe M10 is connected to the first clock signal terminal CLK1, and the first electrode of the tenth transistor M10 is connected to input signal
IN is held, the second electrode of the tenth transistor M10 is connected with the first electrode of the 11st transistor M11, and described the
The grid of 11 transistor M11 is connected to the second electrode connection of second clock signal end CLK2, the 11st transistor M11
To first node N.
The control signal drive circuit further includes third capacitance C3 and the 4th capacitance C4, one end of the third capacitance C3
It is connected to first power supply voltage signal end VGH, the other end of the third capacitance C3 is connected to second node M.Described
One end of four capacitance C4 is connected to first power supply voltage signal end VGH, and the other end of the 4th capacitance C4 is connected to institute
State the second electrode of the tenth transistor M10.
The input signal end IN provides input signal in, the first clock signal terminal CLK1 and provides the first clock signal
Clk1, the second clock signal end CLK2 provide second clock signal clk2, and first power supply voltage signal end VGH is provided
High power supply voltage Vgh, the second source voltage signal end VGL provide low supply voltage Vgl.The one of the first capacitance C1
End, the first electrode of the second transistor M2, the grid of the third transistor M3, the 5th transistor M5 first electricity
Pole, the grid of the 6th transistor M6, the 7th transistor M7 grid connect with the grid of the 8th transistor M8
To second node M, the second node M is connected to output signal end OUT, provides output signal out.The second capacitance C2's
One end, the first electrode of the 8th transistor M8, the second electrode of the 9th transistor M9 are connected with each other, and are connected to control
Signal end EM processed, for exporting control signal em.
In the present embodiment, the first electrode is source electrode, and the second electrode is drain electrode；Alternatively, the first electrode
For drain electrode, the second electrode is source electrode.
The driver' s timing of the control signal drive circuit includes first stage T1, second stage T2 and phase III T3；
T1 in the first stage, input signal in and the first clock signal clk1 are low level, and second clock signal clk2 is high level；
Second stage T2, the input signal in are high level, the second clock signal clk2 with the first clock signal clk1
For low level, the low level output signal out of control signal em and one of a high level are exported；It is described in phase III T3
First clock signal clk1 is low level, and the input signal in and second clock signal clk2 is high level, output one
The output signal out1 of low level control signal em1 and a high level.When the signal of control signal drive circuit shown in Fig. 2
Sequence figure is as shown in figure 3, can be seen that the control signal em1 from first stage T1 to phase III T3 as one in second stage
Signal with high level, to be supplied to pixel circuit.The low level output signal out1 exported in second stage T2 makees
The input signal of signal drive circuit is controlled for next stage, then in phase III T3, the control signal drive circuit of next stage is defeated
Go out the low level output signal out2 (not shown)s of control signal em2 and one of a high level, the output signal
Input signals of the out2 as the control signal drive circuit of next stage again, and so on, multiple control signal is generated, and more
The high level of a control signal translates successively, is supplied to pixel circuit different in display.
Correspondingly, the present invention also provides a kind of driving methods of control signal drive circuit, using above-mentioned control signal
Driving circuit generates control signal.Please refer to signal timing diagram shown in Fig. 3, the driving method of the control signal drive circuit
Including：
First stage T1：The voltage of input signal end IN input voltages, the first node N-terminal is low level；
Second stage T2：The second clock signal clk2 is low level, and the voltage of the first node N-terminal is less than 2 times
Low supply voltage, output signal end exports low level output signal, while the control letter of control signal end output high level
Number；
Phase III T3：First clock signal is low level, and the input signal is with the second clock signal
High level, output signal end export the output signal of high level, while the control signal of control signal end output high level.
Specifically, T1, the input signal in and the first clock signal clk1 are low level, second clock in the first stage
Signal clk2 is high level, and the voltage of the first node N-terminal is low level VGL+ | Vth | (wherein, Vth is the first transistor
The threshold voltage of M1).
It is high level in second stage T2, the input signal in and the first clock signal clk1, when described second
Clock signal clk2 is low level, and the voltage of the first node N-terminal is less than 2Vgl, and output signal end OUT outputs are low level defeated
Go out signal out, while the control signal em1 of control signal end EM output high level.
It should be noted that in organic light emitting display, multiple data lines and scan line, X-shape are set on substrate
At the rectangular pixel unit of multiple arrangements, the waveform that often capable scan line provides sequentially will be in the pixel unit of every a line
Switching transistor is opened, and is allowed the data line of entire row simultaneously by the pixel unit of a full line well, is charged to respective required voltage, shows
Show different grayscale.When every a line is charged, scan line just closes voltage, and then the scan line of next line beats voltage
It opens, then charge and discharge is carried out to the pixel unit of next line by the data line of an identical row, so sequentially go down, when having substituted the bad for the good most
The pixel unit of a line afterwards is then a frame, is then started to charge up again from the first row again.It is both provided with pixel in each pixel unit
Circuit is used for the charge and discharge of pixel unit, needs to provide control signal when completing charge and discharge, therefore, the pixel electricity per a line
Road is required to control signal drive circuit and provides control signal, and therefore, the setting for controlling signal drive circuit should be with scan line
It is corresponding, Multistage Control signal drive circuit is provided on substrate, the control signal drive circuit per level-one corresponds to one
Scan line.Low level output signal will be exported per level-one in second stage T2 output signal ends OUT by control signal drive circuit
Out as next stage control signal drive circuit input signal, the first order control signal drive circuit input signal by
Input signal end IN provides input signal in.
It is low level in phase III T3, the first clock signal clk1, when the input signal in is with described second
Clock signal clk2 is high level, the output signal out of output signal end OUT output high level, while control signal end EM outputs
Low level control signal em1.
In phase III T3, for the control signal drive circuit of next stage, output signal end OUT outputs are low level defeated
Go out signal out, while control the signal em2, the control signal em2 of control signal end EM output high level are supplied to phase therewith
Corresponding pixel circuit, input signals of the output signal out as the control signal drive circuit of next stage again.
Control signal drive circuit per level-one sequentially provides control signal to corresponding pixel circuit, until a frame knot
Beam, each control signal has been provided in control signal drive circuit at this time, then again from the control signal drive circuit of the first order
Start, the job order of the control signal drive circuit is consistent with the pixel unit.
Correspondingly, the present invention also provides a kind of driving method of pixel circuit, using above-mentioned control signal drive circuit
Control signal is provided.The structure of control signal drive circuit provided by the invention is simple, which is integrated
When in the screen body of organic light emitting display, the area of occupancy screen body that will not be excessive is conducive to the reduction of cost.Also, by
In simple in structure, then the Comparision of circuit is stablized, and is capable of providing the stability of control signal.
In conclusion control signal drive circuit provided by the invention and driving method and pixel circuit drive method,
The structure for simplifying control signal drive circuit is realized the output of control signal using a small amount of transistor and capacitance, is convenient for
Integrated realization is conducive to the yield for improving screen body, and the operation is stable of the driving circuit, improves the defeated of control signal
Go out stability.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of control signal drive circuit, which is characterized in that including the first transistor to the 9th transistor, the first capacitance and
Two capacitances, wherein
The grid of the grid of the first transistor and the 4th transistor is connected to one first clock signal terminal, the first crystal
The first electrode of pipe is connected to an input signal end, and the second electrode of the first transistor and the grid of second transistor connect
In a first node；
The second electrode of the second transistor is connected to a second clock signal end, the first electrode of the second transistor,
The grid and the 8th of the grid of third transistor, the first electrode of the 5th transistor, the grid of the 6th transistor, the 7th transistor
The grid of transistor is connected to a second node；
The grid phase of the first electrode of the third transistor, the second electrode and the 5th transistor of the 4th transistor
Connection, the second electrode of the third transistor, the second electrode of the 5th transistor, the 6th transistor second electricity
Pole and the second electrode of the 8th transistor are connected to one first power supply voltage signal end；
The first electrode of 4th transistor, the first electrode of the 7th transistor and the first electrode of the 9th transistor connect
It is connected to a second source voltage signal end；
The first electrode of 6th transistor, the second electrode of the 7th transistor, the 9th transistor grid with
One end of second capacitance is connected, the first electrode of the 8th transistor, the second electrode of the 9th transistor with
The other end of second capacitance is connected to a control signal end；
First capacitance connection is between the second node and first node.
2. control signal drive circuit as described in claim 1, which is characterized in that further include that the tenth transistor and the 11st are brilliant
The grid of body pipe, the tenth transistor is connected to the first clock signal terminal, and the first electrode of the tenth transistor is connected to
The second electrode at input signal end, the tenth transistor is connected with the first electrode of the 11st transistor, and described
The grid of 11 transistors is connected to second clock signal end, and the second electrode of the 11st transistor is connected to first segment
Point.
3. control signal drive circuit as claimed in claim 2, which is characterized in that further include third capacitance and the 4th capacitance,
One end of the third capacitance and one end of the 4th capacitance are connected to first power supply voltage signal end, the third electricity
The other end of appearance is connected to second node, and the other end of the 4th capacitance is connected to the second electrode of the tenth transistor.
4. control signal drive circuit as claimed in claim 3, which is characterized in that the second node is connected to output signal
End.
5. control signal drive circuit as claimed in claim 4, which is characterized in that the first electrode is source electrode, described the
Two electrodes are drain electrode；Alternatively, the first electrode is drain electrode, the second electrode is source electrode.
6. such as control signal drive circuit according to any one of claims 1 to 5, which is characterized in that the driving circuit
Driver' s timing includes first stage, second stage and phase III；In the first stage, input signal is low with the first clock signal
Level, second clock signal are high level；In second stage, the input signal is high level with first clock signal,
The second clock signal is low level, exports the control signal and a low level output signal of a high level；In third
Stage, first clock signal are low level, and the input signal is high level with the second clock signal, and output one is low
The control signal of level and the output signal of a high level.
7. control signal drive circuit as claimed in claim 6, which is characterized in that in second stage, the output signal is made
The input signal of signal drive circuit is controlled for next stage.
8. a kind of driving method of control signal drive circuit, which is characterized in that using as described in any one of claim 1~7
Control signal drive circuit generate control signal, including：
First stage：Input signal end provides input signal, and the voltage of the first node is low level；
Second stage：The second clock signal is low level, second source electricity of the voltage less than 2 times of the first node
Pressure, output signal end export low level output signal, while the control signal of control signal end output high level；
Phase III：First clock signal is low level, and the input signal is high level with the second clock signal,
Output signal end exports the output signal of high level, while the control signal of control signal end output high level.
9. the driving method of control signal drive circuit as claimed in claim 8, which is characterized in that the output of second stage is believed
Number as next stage control signal drive circuit input signal.
10. a kind of driving method of pixel circuit, which is characterized in that using such as control according to any one of claims 1 to 7
Signal drive circuit provides control signal.
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| CN201710132445.9A CN108573677B (en) | 2017-03-07 | 2017-03-07 | Control signal driving circuit and driving method and pixel circuit driving method |
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| CN201710132445.9A CN108573677B (en) | 2017-03-07 | 2017-03-07 | Control signal driving circuit and driving method and pixel circuit driving method |
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| CN108573677B CN108573677B (en) | 2019-12-24 |
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| CN108573677B (en) | 2019-12-24 |
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