CN108566167A - Low noise amplifier circuit - Google Patents

Abstract

The present invention relates to a kind of low noise amplifier circuits.Above-mentioned low noise amplifier circuit, the first bias unit or the second bias unit being biased including cascade multi-stage Low Noise Amplifier, to low-noise amplifier described in every level-one, wherein, it is first bias unit to be biased to prime low-noise amplifier in the multistage low-noise amplifier, it is second bias unit to be biased to rear class low-noise amplifier in the multistage low-noise amplifier, and second bias unit is additionally operable to provide bias voltage to first bias unit；Or in the multistage low-noise amplifier per level-one described in low-noise amplifier is biased is first bias unit.Multi-stage Low Noise Amplifier in the low noise amplifier circuit only needs one or two kinds of bias units to be biased for it, low-noise amplifiers at different levels can be made to be in best working condition, its is simple in structure, at low cost, while also saving the usable floor area of pcb board.

Description

LNA

This application is a divisional application of an invention patent application with an application date of September 26, 2016 and an application number of 2016108539300 with the name of invention and creation of a low-noise amplifier circuit.

technical field

The invention relates to the technical field of electronic circuits, in particular to a low-noise amplifier circuit.

Background technique

The use of Ka-band broadband satellites will become the industry trend of satellite broadband communications in the future. The Ka band is mainly 26.5-40GHz, which greatly improves the communication bandwidth. A series of supporting equipment and components play a vital role in the construction of the entire communication network. Among them, for the ground small station, the transceiver is a key component for constructing the ground small station. In the application for satellite broadcasting, the down conversion module (low noise block, LNB) of the transceiver is the most critical module for receiving signals. The down-conversion module receives the weak signal transmitted from the satellite, the down-conversion module amplifies it and down-converts it into an intermediate frequency signal, and then performs subsequent processing through the modem.

Since the noise figure of the receiver system is mainly determined by the low-noise amplifier, it is particularly important to design an amplifier with reasonable gain, low noise, reliable and stable performance, and a large dynamic range in the design of the receiving front end. Traditional low-noise amplifier circuits are composed of multiple complex electronic components, which are expensive and occupy a large area of the PCB board.

Contents of the invention

Based on this, it is necessary to provide a low-noise amplifier circuit for the problems of complex circuit structure, high cost, and large area occupied by the PCB board.

A low-noise amplifying circuit, comprising cascaded multi-stage low-noise amplifiers, a first bias unit or a second bias unit for biasing each stage of the low-noise amplifier, wherein,

The one that biases the front-stage low-noise amplifier in the multi-stage low-noise amplifier is the first bias unit, and the one that biases the rear-stage low-noise amplifier in the multi-stage low-noise amplifier is the second bias unit. A bias unit, wherein the front-stage low-noise amplifier includes at least a first-stage low-noise amplifier, and the rear-stage low-noise amplifier includes at least a last-stage low-noise amplifier, and the second bias unit is also used for The first bias unit provides a bias voltage; or

It is the first bias unit that biases each stage of the low-noise amplifier in the multi-stage low-noise amplifier.

In one of the embodiments, the first bias unit includes a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

The base of the first triode is connected to the first resistor and the second resistor respectively, the other end of the first resistor is grounded, and the other end of the second resistor is connected to the positive voltage supply terminal; the The collector of the first triode is connected to the negative voltage supply terminal through the third resistor and the fourth resistor; the emitter of the first triode is connected to the positive voltage supply terminal through the fifth resistor;

The low noise amplifier is a transistor amplifier, the source of the transistor amplifier is grounded; the gate of the transistor amplifier is connected to the common point of the third resistor and the fourth resistor; the drain of the transistor amplifier is connected to the first resistor. A transistor emitter connection.

In one of the embodiments, the first bias unit has a second triode; the emitter of the second triode is connected to the positive voltage supply terminal through the second resistor, and the second triode The collector of the transistor is connected to the base of the second triode; the base of the second triode is respectively connected to the first resistor and the base of the first triode.

In one of the embodiments, the second bias unit is a DC bias chip;

The DC bias chip includes multiple sets of correspondingly arranged gate bias pins and drain bias pins; wherein, the gate bias pins provide a positive voltage for the gate of the transistor amplifier, the a drain bias pin provides a negative voltage to the drain of the transistor amplifier; and

It also includes a positive voltage output terminal and a negative voltage output terminal for supplying voltage to the first bias unit.

In one of the embodiments, the low-noise amplifying circuit includes three cascaded first-stage transistor amplifiers, second-stage transistor amplifiers, and third-stage transistor amplifiers.

In one of the embodiments, it is the first bias unit that biases the first-stage transistor amplifier and the second-stage transistor amplifier respectively; it is the first bias unit that biases the third-stage transistor amplifier. Two bias units;

Wherein, the positive voltage output terminals of the second bias unit are respectively connected to the fifth resistor in the first bias unit; the negative voltage output terminals of the second bias unit are respectively connected to the first bias the fourth resistor connection in the cell;

The gate bias pins and drain bias pins in any group of the second bias unit are correspondingly connected to the gate and drain of the third-stage transistor amplifier.

In one of the embodiments, the low-noise amplifying circuit includes a PNP type general-purpose double transistor that simultaneously biases the first-stage transistor amplifier and the second-stage transistor amplifier; and biases the third-stage transistor amplifier. Set as the second bias unit;

Wherein, the gates of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively connected to the collectors of the PNP-type general-purpose double transistor; the drains of the first-stage transistor amplifier and the second-stage transistor amplifier are respectively connected to the The emitter connection of the PNP type universal double transistor; the source of the first-stage transistor amplifier and the second-stage transistor amplifier are grounded;

The positive voltage output terminal of the second bias unit is connected to the emitter of the PNP-type general-purpose double transistor; the negative voltage output terminal of the second bias unit is connected to the collector of the PNP-type general-purpose double-transistor;

The gate bias pins and drain bias pins in any group of the second bias unit are correspondingly connected to the gate and drain of the third transistor amplifier.

In one of the embodiments, it is the first bias unit that biases each of the three low-noise amplifiers;

The emitters of the first triodes in the first bias unit are all loaded with a positive voltage, and the collectors of the first triodes are all loaded with a negative voltage.

In one of the embodiments, it is the first bias unit that biases the first-stage transistor amplifier; it is the second bias unit that simultaneously biases the second-stage transistor amplifier and the third-stage transistor amplifier. bias unit;

The positive voltage output terminal of the second bias unit is connected to the fifth resistor in the first bias unit; the negative voltage output terminal of the second bias unit is connected to the fifth resistor in the first bias unit. Four resistance connections;

The first group of gate bias pins and drain bias pins in the second bias unit are respectively connected to the gate and drain of the second-stage transistor amplifier; The second group of gate bias pins and drain bias pins in the bias unit are respectively connected to the gate and drain of the third-stage transistor amplifier.

In one of the embodiments, a plurality of DC blocking capacitors are further included, and the DC blocking capacitors are connected in series between two adjacent stages of the low noise amplifiers.

The above-mentioned low-noise amplifying circuit includes cascaded multi-stage low-noise amplifiers, a first bias unit or a second bias unit for biasing each stage of the low-noise amplifier, wherein the multi-stage low-noise The first bias unit is used to bias the front-stage low-noise amplifier in the amplifier, and the second bias unit is used to bias the rear-stage low-noise amplifier in the multi-stage low-noise amplifier. The second bias unit is also used to provide a bias voltage to the first bias unit; or to bias each stage of the low noise amplifier in the multi-stage low noise amplifier is the first bias unit. The multi-stage low-noise amplifier in the low-noise amplifier circuit only needs one or two kinds of bias units to bias it, so that the low-noise amplifiers of all levels can be in the best working state, and the structure is simple and the cost is low. At the same time, it also saves the use area of the PCB board.

Description of drawings

Fig. 1 is a structural framework diagram of the low noise amplifying circuit of an embodiment;

2 is a circuit diagram of a first bias unit in an embodiment;

3 is a circuit diagram of a first bias unit in another embodiment;

Fig. 4 is an arrangement diagram of the pins of the DC bias chip in an embodiment;

Fig. 5 is a drain current-drain voltage characteristic curve diagram of a transistor amplifier in an embodiment;

Fig. 6 is one of the circuit diagrams of the low noise amplifying circuit in an embodiment;

Fig. 7 is the second circuit diagram of the low noise amplifying circuit in an embodiment;

Fig. 8 is the third circuit diagram of the low noise amplifying circuit in an embodiment;

FIG. 9 is the fourth circuit diagram of the low noise amplifier circuit in an embodiment.

Detailed ways

In order to facilitate the understanding of the present invention, the invention will be described more fully below with reference to the associated drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terminology used herein in the description of the invention is for the purpose of describing specific embodiments only, and is not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

A low-noise amplifier circuit, which amplifies the signal received or to be transmitted, so that the total noise figure in the circuit is small and the power gain is high. The low-noise amplifier circuit can be used in Ka-band, Ku-band, and X-band The transceiver system is medium.

As shown in Figure 1 is a structural frame diagram of the low noise amplifier circuit, wherein the low noise amplifier circuit includes cascaded multi-stage low noise amplifiers (M1, M2, ..., Mn) and each stage of the low noise amplifier is biased set the first bias unit 110 or the second bias unit 120.

The first bias unit 110 is used to bias the front-stage low-noise amplifiers in the multi-stage low-noise amplifiers (M1, M2, ..., Mn), and the rear The second bias unit 120 performs biasing for the stage low noise amplifiers, wherein the front stage low noise amplifier includes at least the first stage low noise amplifier M1, and the rear stage low noise amplifier includes at least the last stage low noise amplifier Mn. The second bias unit 120 is also used for providing a bias voltage to the first bias unit 110 . Or it is the first bias unit 110 that biases each stage of the low noise amplifier in the multistage low noise amplifier ( M1 , M2 , . . . , Mn).

In this embodiment, the low-noise amplifier circuit is applied in the down-conversion module (Low Noise Block, LNB) of the transceiver, and the Ka-band high-frequency signal received by the multi-stage low-noise amplifier (M1, M2, ..., Mn) enlarge. Wherein, the low noise amplifier is a transistor amplifier, and the transistor amplifier adopts a high electron mobility transistor (High Electron Mobility Transistor, HEMT) to amplify the high frequency signal. In other embodiments, the transistor amplifier can also be a heterojunction bipolar transistor (Heterojunction Bipolar Transistor, HBT), a pseudomorphic high electron mobility transistor (Pseudomorphic High Electron Mobility Transistor, pHEMT), a metal-semiconductor field effect transistor (Metal-Semiconductor FET) or Junction Field-Effect Transistor (JFET).

High-frequency signals are amplified by multi-stage transistor amplifiers (M1, M2, ..., Mn), and each stage of transistor amplifiers is equipped with a corresponding first bias unit 110 or a second bias unit 120, and the transistor amplifier is amplified. The bias makes the transistor amplifier in the best working state, that is, the drain voltage and drain current work in the best state. At the same time, the second bias unit 120 can also provide the bias voltage for the first bias unit 110 , the circuit design is simple, the design cost and material cost are saved, and the PCB area is also saved.

Among them, the noise figure is the most important parameter of the low noise amplifier, and the noise figure formula of the multi-stage cascaded low noise amplifier can be:

NF＝NF ₁ +(NF ₂ -1)/G ₁ +(NF ₃ -1)/(G ₁ *G ₂ )+...

Among them, NF _n is the noise figure (Noise Figure, NF) of the nth stage LNA, and G _n is the gain of the nth stage LNA. It can be seen from the above formula that the noise of the first stage LNA and its The essential. It can be seen that in order to make the total noise figure of the receiver small, the noise figure of the low-noise amplifiers at all levels is required to be small and the power gain is high; and the influence of internal noise at each level is different, and the higher the number of stages, the greater the impact on the total noise figure , so the total noise figure mainly depends on the first few stages, which is the main reason why the receiver should use a high-gain low-noise amplifier.

FIG. 2 is a circuit diagram of the first bias unit in an embodiment. The first bias unit 110 includes a first transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5. The bases of the first triode Q1 are respectively connected to the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is grounded, and the other end of the second resistor R2 is connected to the positive voltage supply terminal V _OUT ; the first three The collector of the transistor Q1 is connected to the negative voltage supply terminal V _NEG via the third resistor R3 and the fourth resistor R4; the emitter of the first triode Q1 is connected to the positive voltage supply terminal V _OUT via the fifth resistor R5. The source of the transistor amplifier M1 is grounded; the gate of the transistor amplifier M1 is connected to the common point of the third resistor R3 and the fourth resistor R4; the drain of the transistor amplifier M1 is connected to the emitter of the first transistor Q1.

Through the first triode Q1 and the resistor in the first bias unit 110, the required positive bias voltage and negative bias voltage can be provided for the transistor amplifier M1, so that the transistor amplifier M1 works at the drain voltage V _DS = 2V, the best working condition of I _DS =10mA. At the same time, the first bias unit 110 also plays the role of stabilizing the current, so that the transistor amplifier M1 can obtain a stable DC state. If the current of the transistor amplifier M1 increases due to the influence of the temperature change, the emitter current of the first triode Q1 decreases, so the collector current of the first triode Q1 also decreases accordingly. Furthermore, the voltage of the first triode collector Q1 connected to the negative voltage power supply terminal is also reduced, that is, the gate voltage of the transistor amplifier M1 is reduced, and the source-drain current I _DS of the transistor amplifier M1 is reduced, thus playing the role of negative feedback , so that the transistor amplifier M1 obtains a stable DC state.

FIG. 3 is a circuit diagram of the first bias unit in another embodiment. The first bias unit 110 also includes a second transistor Q2; the emitter of the second transistor Q2 is connected to the positive voltage supply terminal V _OUT through the second resistor R2, and the collector of the second transistor Q2 is connected to the second The base of the transistor Q2 is connected; the base of the second transistor Q2 is respectively connected with the base of the first resistor R1 and the first transistor Q1. At the same time, setting the second triode Q2 also plays the role of temperature compensation and stabilizing the working point.

In an embodiment, the first bias unit 110 further includes a sixth resistor R6 and a seventh resistor R7. The seventh resistor R7 is connected in series between the emitter of the first triode Q1 and the drain of the transistor amplifier M1, and the sixth resistor R6 is connected in series between the common point of the third resistor R3 and the fourth resistor R4 and the transistor amplifier M1 between the gates. In this embodiment, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are all adjustable resistors, which can be used to adjust the output current value of the transistor amplifier.

In this embodiment, both the first triode Q1 and the second triode are PNP type triodes, they may also be NPN type first triodes, and the PNP type first triodes are used. In other embodiments, the first triode Q1 and the second triode are both NPN transistors according to actual needs, and can also be replaced by MOS transistors.

Since the source of the transistor amplifier M1 is grounded, the emitter of the first triode Q1 is connected to the positive voltage supply terminal V _OUT via the fifth resistor R5, wherein the positive voltage supply terminal V _OUT is a positive voltage supply terminal of 5 volts. In this embodiment, the positive voltage supply terminal V _OUT is provided with a voltage of 5 volts by the positive voltage output terminal of the second bias unit 120 . The voltage of 5 volts is divided by the first resistor R1 and the second resistor R2 connected to the ground, and then divided to the base of the first transistor Q1, which is the base bias of the first transistor Q1. At the same time, the drain of the transistor amplifier M1 is connected to the emitter of the first triode Q1 through the seventh resistor R7 to obtain a positive bias voltage, and the gate of the transistor amplifier M1 is connected to the negative electrode through the sixth resistor R6 and the fourth resistor R4. The voltage supply terminal V _ENG is connected. In this embodiment, the negative voltage output terminal of the second bias unit 120 provides a voltage of -2.5V to the negative voltage supply terminal V _ENG to obtain a negative bias voltage. In other embodiments, the voltages of the positive voltage supply terminal and the negative voltage supply terminal in the first bias unit 110 may also be powered by a direct current power supply, which is not limited thereto.

The second bias unit 120 is a DC bias chip U1. Referring to FIG. Voltage positive voltage output terminal V _OUT and negative voltage output terminal V _ENG . Wherein, the drain bias pin D provides a positive voltage for the gate of the transistor amplifier, and the gate bias pin G provides a negative voltage for the drain of the transistor amplifier. In this embodiment, the DC bias chip U1 includes four sets of gate bias pins (G1, G2, G3, G4) and drain bias pins (D1, D2, D3, D4) that are set correspondingly. There is a set of a positive voltage output terminal V _OUT and a negative voltage output terminal V _ENG providing voltages for the first bias unit 110 . Since the drain voltage of a transistor amplifier operating in the Ka band is 2V, the gate is generally negative. In this embodiment, the positive voltage output by the drain bias pin D of the DC bias chip U1 is 2 volts, and the negative voltage output by the gate bias pin G is -0.6 volts.

As shown in Figure 5, it is the drain current-drain voltage characteristic diagram of the transistor amplifier. Since each transistor amplifier has different characteristic curves, in this embodiment, when the source of the transistor amplifier is grounded and the drain voltage When the gate voltage of the transistor amplifier is 2 volts and the drain current is 10 mA, the gate voltage of the transistor amplifier under this operating condition is -0.6 volts. In other embodiments, the specific value of the DC bias voltage can be set according to the actual working conditions of the transistor amplifier.

In this embodiment, the down-conversion module used for satellite signal reception is amplified using a three-stage transistor amplifier, referring to FIG. Transistor amplifier M3. Among them, a plurality of DC blocking capacitors (C1, C2) are also included, and the DC blocking capacitors are connected in series between adjacent two-stage transistor amplifiers. Each stage of transistor amplifiers is cascaded through DC blocking capacitors (C1, C2), so that the DC bias of each stage of transistor amplifiers does not affect each other.

In order to make the total noise figure of the receiver small, the noise figures of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 have a great influence on the total noise figure of the receiver. Referring to Figure 5, the first-stage transistor amplifier M1 is The bias unit is the first bias unit 110 ; the bias unit for the second-stage transistor amplifier M2 is the first bias unit 110 ′; the device for biasing the third-stage transistor amplifier M3 is the second bias unit U1 .

Wherein, the positive voltage output terminal V _OUT of the second bias unit U1 is connected to the fifth resistor R5 in the first bias unit (110, 110′); the negative voltage output terminal V _NEG of the second bias unit U1 is both It is connected with the fourth resistor R4 in the first bias unit (110, 110'). The drain of the first-stage transistor amplifier M1 is connected to the gate of the second-stage transistor amplifier M2 via the first DC blocking capacitor C1. In any group of the second bias unit U1, the gate bias pin G and the drain bias pin D are correspondingly connected to the gate and drain of the third transistor amplifier M3. In this embodiment, the gate bias pin G3 in the second bias unit U1 is connected to the gate of the third-stage transistor amplifier M3, and the drain bias pin D3 is connected to the drain of the third-stage transistor amplifier M3 connect. The drain of the second-stage transistor amplifier M2 is connected to the gate of the third-stage transistor amplifier M3 via the second DC blocking capacitor C2. The drain of the third-stage transistor amplifier M3 outputs the amplified high-frequency signal to other devices (filters, etc.).

Both the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 adopt the same active DC bias, and the transistor amplifier is subjected to DC bias through the first transistor Q1, which can ensure that the first-stage transistor amplifier M1 and the second-stage The best DC working state of the transistor amplifier M2 also has certain temperature stability. The third-stage transistor amplifier M3 is biased by the DC bias chip U1, and the DC bias chip U1 directly outputs the gate and drain bias voltage required by the third-stage transistor amplifier M3. Q1 provides a positive voltage and a negative voltage, while satisfying the performance of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 with better noise coefficient performance, the circuit design is simplified, and the PCB area and cost are reduced.

In one of the embodiments, the low noise amplifying circuit includes a PNP type general-purpose double transistor U2 that simultaneously biases the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2; and biases the third-stage transistor amplifier M3 is the second bias unit U1.

Wherein, the grid M2 of the first-stage transistor amplifier M1 and the second-stage transistor amplifier is respectively connected to the collector of the PNP type general-purpose double transistor U2; the drains of the first-stage transistor amplifier M1 and the second transistor amplifier M2 are respectively connected to The emitter of the PNP type universal double transistor U2 is connected; the sources of the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 are grounded. The positive voltage output terminal of the second bias unit U1 is connected to the emitter of the PNP-type general dual transistor U2; the negative voltage output terminal of the second bias unit U1 is connected to the collector of the PNP-type general dual transistor U2. The gate bias pin G and the drain bias pin D in any group of the second bias unit U1 are connected to the gate and drain of the third transistor amplifier M3 respectively. That is, the first bias unit 110 for biasing the first-stage transistor amplifier M1 and the second-stage transistor amplifier M2 can be used to bias the two first triodes (Q1 , Q1') can be integrated together to form a component. Referring to Figure 7, the integrated components can be replaced by a PNP-type general-purpose double transistor (NXP/PUMT1), which simplifies the use of electronic components and reduces The use area of the PCB board is reduced.

In one of the embodiments, referring to FIG. 9, the first bias unit 110 is used to bias each stage of the three-stage low-noise amplifier, that is, three first bias units (110, 110', 110") to bias the three-stage transistor amplifiers (M1, M2, M3) respectively. The first transistors (Q1, Q1, The emitters of Q1', Q1") are all loaded with positive voltage, and the collectors of the first transistors (Q1, Q1', Q1") are all loaded with negative voltage. The three-stage transistor amplifiers (M1, M2, M3) are biased by three separate first transistors (Q1, Q1', Q1"), which can be provided to the three-stage transistor amplifiers (M1, M2, M3 ) the best DC working state, and also has a certain temperature stability, the total noise figure of the receiver is small, and the power gain is high. Among them, in the three first bias units (110, 110', 110"), Any two adjacent first triodes can be replaced by general-purpose double first triodes (NXP/PUMT1).

In one of the embodiments, referring to FIG. 8 , the first bias unit 110 is used to bias the first-stage transistor amplifier M1; The second bias unit U1.

Wherein, the positive voltage output terminal V _OUT of the second bias unit U1 is connected to the fifth resistor R5 in the first bias unit 110; the negative voltage output terminal V _NEG of the second bias unit U1 is connected to the first bias unit 110 The fourth resistor R4 in the connection. The gate bias pin G2 and the drain bias pin D2 of the first group in the second bias unit U1 are respectively connected to the gate and drain of the second-stage transistor amplifier M2; in the second bias unit U1 The gate bias pin G3 and the drain bias pin D3 in the second group are respectively connected to the gate and drain of the third-stage transistor amplifier M3. In another embodiment, the second bias unit U1 can also be used to bias the three-stage cascaded transistor amplifiers (M1, M2, M3) at the same time, and the gate bias voltage provided by the second bias unit U1 , The drain bias unit needs to meet actual requirements. By reasonably setting the first triode and the DC bias chip U1 to bias the three-stage transistor amplifier, the usage of electronic components on the PCB can be reduced, the circuit design can be simplified, and the area and cost of the PCB can be reduced. .

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (9)

1. A low noise amplifier circuit includes a cascade of a plurality of low noise amplifiers and a first bias unit for biasing the low noise amplifiers at each stage; wherein,

the first biasing unit comprises a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor; the base electrode of the first triode is respectively connected with the first resistor and the second resistor, the other end of the first resistor is grounded, and the other end of the second resistor is connected with the positive voltage power supply end; the collector of the first triode is connected with a negative voltage power supply end through the third resistor and the fourth resistor; the emitter of the first triode is connected with the positive voltage power supply end through the fifth resistor;

the low noise amplifier is a transistor amplifier, and the source electrode of the transistor amplifier is grounded; the grid electrode of the transistor amplifier is connected with the common point of the third resistor and the fourth resistor; the drain electrode of the transistor amplifier is connected with the emitter electrode of the first triode.

2. The low-noise amplification circuit according to claim 1, wherein the first bias unit further comprises a second transistor;

the emitter of the second triode is connected with the positive voltage power supply end through the second resistor, and the collector of the second triode is connected with the base of the second triode; and the base electrode of the second triode is respectively connected with the first resistor and the base electrode of the first triode.

3. The low-noise amplification circuit according to claim 1, wherein the first bias unit further includes a sixth resistor and a seventh resistor;

the seventh resistor is connected between the emitter of the first triode and the drain of the transistor amplifier in series; the sixth resistor is connected in series between a common point of the third resistor and the fourth resistor and the grid of the transistor amplifier.

4. The low-noise amplification circuit of claim 3, wherein the fifth resistor, the sixth resistor, and the seventh resistor are all adjustable resistors, and are configured to adjust a current value of the output of the transistor amplifier.

5. The low-noise amplification circuit according to claim 1, further comprising a second bias unit that supplies a bias voltage to the first bias unit.

6. The low-noise amplification circuit of claim 5, wherein the second bias unit is a DC bias chip;

the direct current bias chip comprises a positive voltage output end and a negative voltage output end which provide voltage for the first bias unit.

7. The low-noise amplification circuit according to claim 1, wherein the low-noise amplification circuit comprises a first-stage transistor amplifier, a second-stage transistor amplifier, and a third-stage transistor amplifier cascaded in three stages.

8. The low noise amplifier circuit according to claim 7, wherein the first bias unit is used for biasing each of the low noise amplifiers in the three stages of the low noise amplifiers;

and the emitting electrodes of the first triodes in the first bias unit are loaded with positive voltage, and the collecting electrodes of the first triodes are loaded with negative voltage.

9. The low noise amplifier circuit according to claim 1, further comprising a plurality of dc blocking capacitors, wherein the dc blocking capacitors are connected in series between two adjacent stages of the low noise amplifier.