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CN108566104A - A kind of synchronous commutating control circuit - Google Patents

A kind of synchronous commutating control circuit Download PDF

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CN108566104A
CN108566104A CN201810427388.1A CN201810427388A CN108566104A CN 108566104 A CN108566104 A CN 108566104A CN 201810427388 A CN201810427388 A CN 201810427388A CN 108566104 A CN108566104 A CN 108566104A
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CN108566104B (en
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李泽宏
熊涵风
罗仕麟
张成发
赵念
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

一种同步整流控制电路，属于电子电路技术。本发明通过检测整流管的漏源压差来开启和关断整流管，包括电压检测模块、同步整流逻辑控制模块和驱动模块，电压检测模块用于检测整流管的漏源压差，同步整流逻辑控制模块用于控制整流管的最小导通时间，避免开启整流管后发生震荡，驱动模块用于提供栅极驱动。本发明提供的驱动方式简单可靠，可以大幅降低整流器的功耗，降低整流桥的温度，提升系统可靠性；同时可实现较低的导通损耗，提高发电机整体效率，起到节约能源，清洁环保的作用。

A synchronous rectification control circuit belongs to electronic circuit technology. The invention turns on and off the rectifier by detecting the drain-source pressure difference of the rectifier, including a voltage detection module, a synchronous rectification logic control module and a drive module, the voltage detection module is used to detect the drain-source pressure difference of the rectifier, and the synchronous rectification logic The control module is used to control the minimum conduction time of the rectifier tube to avoid oscillation after turning on the rectifier tube, and the drive module is used to provide gate drive. The driving method provided by the present invention is simple and reliable, can greatly reduce the power consumption of the rectifier, reduce the temperature of the rectifier bridge, and improve the reliability of the system; at the same time, it can achieve lower conduction loss, improve the overall efficiency of the generator, and save energy and clean The role of environmental protection.

Description

一种同步整流控制电路A synchronous rectification control circuit

技术领域technical field

本发明属于电子电路技术，具体的说是涉及一种用于电机发电的整流电路的控制电路。The invention belongs to the electronic circuit technology, and in particular relates to a control circuit for a rectifier circuit used for electric motor power generation.

背景技术Background technique

目前发电机整流器主要使用硅二极管作为整流元件，硅二极管正向压降大约为0.3～1V，大电流时通态功耗很大。随着汽车的大量普及，由硅二极管整流带来的功耗不容忽视。At present, the generator rectifier mainly uses silicon diodes as rectification elements. The forward voltage drop of silicon diodes is about 0.3-1V, and the on-state power consumption is very large when the current is high. With the popularization of automobiles, the power consumption caused by silicon diode rectification cannot be ignored.

同步整流技术(Synchronous Rectification，SR)采用低电压的功率金属-氧化物半导体场效应晶体管(Power MOSFET)作为整流器件，利用其沟道通态电阻，可以很好的降低整流器模块的整体功耗。而采用同步整流技术的主要难度在于其整流管的栅极控制。Synchronous rectification technology (Synchronous Rectification, SR) uses a low-voltage power metal-oxide semiconductor field effect transistor (Power MOSFET) as a rectifier device, and its channel on-state resistance can be used to reduce the overall power consumption of the rectifier module. The main difficulty in adopting synchronous rectification technology lies in the gate control of its rectifier tube.

整流管的驱动主要采用脉冲宽度调制PWM方式，其实现较为复杂，需要建立空间矢量数学模型，进行复杂的变换求解，因此在电路组成上需要大量的逻辑处理，增加了技术难度和成本；而汽车发电机受汽车转速影响，更增加了控制算法的难度，应用成本太高，不利于同步整流技术的普及。The drive of the rectifier mainly adopts the pulse width modulation PWM method, and its implementation is relatively complicated, and it is necessary to establish a space vector mathematical model and perform complex transformation solutions. Therefore, a large amount of logic processing is required in the circuit composition, which increases technical difficulty and cost; The generator is affected by the speed of the car, which increases the difficulty of the control algorithm, and the application cost is too high, which is not conducive to the popularization of synchronous rectification technology.

发明内容Contents of the invention

本发明的目的，就是针对目前同步整流技术中存在的在技术难度和成本上的问题，提出一种控制电路，用于控制电机发电的整流电路，结构简单，电路功耗低、可靠性高。The purpose of the present invention is to propose a control circuit for controlling the rectification circuit of motor power generation in view of the problems of technical difficulty and cost in the current synchronous rectification technology, which has simple structure, low power consumption and high reliability.

本发明技术方案为：Technical scheme of the present invention is:

一种同步整流控制电路，用于控制同步整流系统中的整流管，包括电压检测模块、同步整流逻辑控制模块和驱动模块，A synchronous rectification control circuit, used to control a rectifier tube in a synchronous rectification system, comprising a voltage detection module, a synchronous rectification logic control module and a drive module,

所述电压检测模块用于检测整流管的漏源电压并产生第一检测信号和第二检测信号；The voltage detection module is used to detect the drain-source voltage of the rectifier and generate a first detection signal and a second detection signal;

所述同步整流逻辑控制模块包括最小导通时间产生模块、周期性唤醒模块、最小消隐时间产生模块、第一或门T2和第四反相器T3，The synchronous rectification logic control module includes a minimum on-time generation module, a periodic wake-up module, a minimum blanking time generation module, a first OR gate T2 and a fourth inverter T3 ,

所述最小导通时间产生模块包括第一D触发器D1、第二反相器G1、第二或门G2、第一与非门G3和第一上升沿延迟模块，第二反相器G1的输入端连接第一与非门G3的第一输入端和第一或门T2的输出端，其输出端连接第一D触发器D1的时钟端；第一或门T2的第一输入端连接所述第一检测信号；第一D触发器D1的数据输入端连接使能信号EN，其复位端连接第二或门G2的输出端，其Q输出端连接第一上升沿延迟模块的输入端，其Q非输出端连接第一与非门G3的第二输入端；第二或门G2的第一输入端连接使能信号的反相信号ENB，其第二输入端连接第四反相器T3的输出端，其第三输入端连接第一上升沿延迟模块的输出端；第四反相器T3的输入端连接所述第二检测信号；第一与非门G3的输出端作为所述最小导通时间产生模块的输出端；The minimum on-time generating module includes a first D flip-flop D 1 , a second inverter G 1 , a second OR gate G 2 , a first NAND gate G 3 and a first rising edge delay module, and the second inverter The input end of the phase device G1 is connected to the first input end of the first NAND gate G3 and the output end of the first OR gate T2 , and its output end is connected to the clock end of the first D flip-flop D1 ; the first OR gate The first input terminal of T2 is connected to the first detection signal; the data input terminal of the first D flip-flop D1 is connected to the enable signal EN, its reset terminal is connected to the output terminal of the second OR gate G2 , and its Q output terminal Connect the input terminal of the first rising edge delay module, its Q non-output terminal is connected to the second input terminal of the first NAND gate G3 ; the first input terminal of the second OR gate G2 is connected to the inversion signal ENB of the enable signal , its second input terminal is connected to the output terminal of the fourth inverter T3 , its third input terminal is connected to the output terminal of the first rising edge delay module; the input terminal of the fourth inverter T3 is connected to the second detection signal; the output end of the first NAND gate G 3 is used as the output end of the minimum on-time generating module;

所述周期性唤醒模块包括第二D触发器D2、第一与非门G4、第三或门G5、第一与门G6和第二上升沿延迟模块，The periodic wake-up module includes a second D flip-flop D 2 , a first NAND gate G 4 , a third OR gate G 5 , a first AND gate G 6 and a second rising edge delay module,

第二D触发器D2的时钟端连接第一或门T2的输出端，其数据输入端连接第三或门G5的第二输入端和所述最小导通时间产生模块中第一D触发器D1的Q输出端，其复位端连接第一与非门G4的输出端，其Q输出端连接第一或门T2的第二输入端，其Q非输出端连接第三或门G5的第一输入端；第一与门G6的第一输入端连接第三或门G5的输出端并作为所述周期性唤醒模块的输出端，其第二输入端连接所述第一检测信号，其输出端连接第二上升沿延迟模块的输入端；第一与非门G4的第一输入端连接第二上升沿延迟模块的输出端，其第二输入端连接所述使能信号的反相信号ENB，其第三输入端连接第四反相器T3的输出端；The clock terminal of the second D flip-flop D2 is connected to the output terminal of the first OR gate T2 , and its data input terminal is connected to the second input terminal of the third OR gate G5 and the first D in the minimum on-time generation module. The Q output terminal of flip-flop D1 , its reset terminal is connected to the output terminal of the first NAND gate G4 , its Q output terminal is connected to the second input terminal of the first OR gate T2 , and its Q non-output terminal is connected to the third OR The first input end of the gate G5 ; the first input end of the first AND gate G6 is connected to the output end of the third OR gate G5 and is used as the output end of the periodic wake-up module, and its second input end is connected to the The first detection signal, its output end is connected to the input end of the second rising edge delay module; the first input end of the first NAND gate G4 is connected to the output end of the second rising edge delay module, and its second input end is connected to the said The inversion signal ENB of the enable signal, the third input end of which is connected to the output end of the fourth inverter T3 ;

所述最小消隐时间产生模块包括第三D触发器D3、第三上升沿延迟模块、第二与门G7、第四或门G8和第五或门G9，The minimum blanking time generation module includes a third D flip-flop D 3 , a third rising edge delay module, a second AND gate G 7 , a fourth OR gate G 8 and a fifth OR gate G 9 ,

第二与门G7的第一输入端连接第一或门T2的输出端，其第二输入端连接所述最小导通时间产生模块中第一D触发器D1的Q非输出端，其第三输入端连接所述周期性唤醒模块中第二D触发器D2的Q非输出端，其输出端连接第三D触发器D3的时钟端和第五或门G9的第一输入端；第三D触发器D3的数据输入端连接使能信号EN，其复位端连接第四或门G8的输出端，其Q输出端连接第三上升沿延迟模块的输入端和第五或门G9的第二输入端；第五或门G9的输出端作为所述最小消隐时间产生模块的输出端；第四或门G8的第一输入端连接第三上升沿延迟模块的输出端，其第二输入端连接所述周期性唤醒模块中第二D触发器D2的Q输出端，其第三输入端连接第四反相器T3的输出端；The first input end of the second AND gate G7 is connected to the output end of the first OR gate T2 , and its second input end is connected to the Q non-output end of the first D flip-flop D1 in the minimum on-time generation module, Its third input end is connected to the Q non-output end of the second D flip-flop D2 in the periodic wake-up module, and its output end is connected to the clock end of the third D flip-flop D3 and the first of the fifth OR gate G9. Input terminal; the data input terminal of the third D flip-flop D3 is connected to the enable signal EN, its reset terminal is connected to the output terminal of the fourth OR gate G8 , and its Q output terminal is connected to the input terminal of the third rising edge delay module and the first The second input end of five OR gate G9 ; The output end of the fifth OR gate G9 is as the output end of the minimum blanking time generation module; The first input end of the fourth OR gate G8 is connected to the third rising edge delay The output terminal of the module, its second input terminal is connected to the Q output terminal of the second D flip-flop D2 in the periodic wake-up module, and its third input terminal is connected to the output terminal of the fourth inverter T3 ;

所述驱动模块的第一输入端所述最小导通时间产生模块的输出端，其第二输入端连接所述周期性唤醒模块的输出端，其第三输入端连接所述最小消隐时间产生模块的输出端，其输出端连接所述整流管的栅极。The first input terminal of the driving module is the output terminal of the minimum on-time generation module, its second input terminal is connected to the output terminal of the periodic wake-up module, and its third input terminal is connected to the minimum blanking time generation module. The output terminal of the module is connected to the grid of the rectifier tube.

具体的，所述电压检测模块包括第一比较器Comp1、第二比较器Comp2、第一电压源和第二电压源，第一比较器Comp1的同相输入端连接所述整流管的漏极，其反相输入端连接第一电压源的正向端，其输出端输出所述第一检测信号；第二比较器Comp2的同相输入端连接第二电压源的正向端，其反相输入端连接所述整流管的漏极，其输出端输出所述第二检测信号；第一电压源和第二电压源的负向端连接所述整流管的源极。Specifically, the voltage detection module includes a first comparator Comp1, a second comparator Comp2, a first voltage source and a second voltage source, and the non-inverting input terminal of the first comparator Comp1 is connected to the drain of the rectifier tube, which The inverting input terminal is connected to the positive terminal of the first voltage source, and its output terminal outputs the first detection signal; the non-inverting input terminal of the second comparator Comp2 is connected to the positive terminal of the second voltage source, and its inverting input terminal is connected to The output terminal of the drain of the rectifier tube outputs the second detection signal; the negative ends of the first voltage source and the second voltage source are connected to the source of the rectifier tube.

具体的，所述第一比较器Comp1为迟滞比较器。Specifically, the first comparator Comp1 is a hysteresis comparator.

具体的，所述第一上升沿延迟模块、第二上升沿延迟模块和第三上升沿延迟模块具有相同的结构，所述第一上升沿延迟模块包括第一电流源I1、第一电容C1、第一MOS管M1、第二或非门T5、第二与非门T6和第一施密特触发器T7，第二与非门T6的第一输入端作为所述第一上升沿延迟模块的输入端，其第二输入端连接所述使能信号EN，其输出端连接第一MOS管M1的栅极；第一电容C1的一端连接第一MOS管M1的漏极、第一施密特触发器T7的输入端和第一电流源I1的负向端，其另一端连接第一MOS管M1的源极并接地；第一电流源I1的正向端连接电源电压；第二或非门T5的输入端连接第一施密特触发器T7的输出端，其输出端作为所述第一上升沿延迟模块的输出端。Specifically, the first rising edge delay module, the second rising edge delay module and the third rising edge delay module have the same structure, and the first rising edge delay module includes a first current source I 1 , a first capacitor C 1. The first MOS transistor M 1 , the second NOR gate T 5 , the second NAND gate T 6 and the first Schmitt trigger T 7 , the first input terminal of the second NAND gate T 6 is used as the The input end of the first rising edge delay module, its second input end is connected to the enable signal EN, its output end is connected to the gate of the first MOS transistor M1 ; one end of the first capacitor C1 is connected to the first MOS transistor M 1 , the input terminal of the first Schmitt trigger T7 and the negative terminal of the first current source I1 , the other end of which is connected to the source of the first MOS transistor M1 and grounded; the first current source I The positive terminal of 1 is connected to the power supply voltage; the input terminal of the second NOR gate T5 is connected to the output terminal of the first Schmitt trigger T7 , and its output terminal is used as the output terminal of the first rising edge delay module.

具体的，所述同步整流逻辑控制模块还包括用于产生所述使能信号EN的反相信号的第一反相器T1，第一反相器T1的输入端连接所述使能信号EN，其输出端输出所述使能信号的反相信号ENB。Specifically, the synchronous rectification logic control module further includes a first inverter T1 for generating an inversion signal of the enable signal EN, the input terminal of the first inverter T1 is connected to the enable signal EN, Its output terminal outputs the inverted signal ENB of the enable signal.

具体的，所述驱动模块包括第三与门T4、第二或非门T5和驱动输出级，第三与门T4的第一输入端作为所述驱动模块的第一输入端，其第二输入端连接第二或非门T5的输出端，其输出端连接所述驱动输出级的输入端；第二或非门T5的第一输入端作为所述驱动模块的第二输入端，其第二输入端作为所述驱动模块的第三输入端；所述驱动输出级包括偶数个级联的反相器，其输出端作为所述驱动模块的输出端。Specifically, the drive module includes a third AND gate T4, a second NOR gate T5 and a drive output stage, the first input terminal of the third AND gate T4 serves as the first input terminal of the drive module, and its second input End is connected with the output end of the second NOR gate T5, and its output end is connected with the input end of the described drive output stage; The first input end of the second NOR gate T5 is used as the second input end of the drive module, and its second The input end is used as the third input end of the driving module; the driving output stage includes an even number of cascaded inverters, and the output end thereof is used as the output end of the driving module.

本发明的有益效果为：本发明提供的控制电路，通过检测发电机整流器中的整流管的漏源压差控制整流管的导通和关断，能够实现整流器具有较低的导通损耗，提高发电机的整体效率，驱动方式简单可靠，且节约能源，清洁环保；同时本发明提供的控制电路可以大幅降低整流器的功耗，降低了整流桥的温度，提升了系统可靠性。The beneficial effects of the present invention are: the control circuit provided by the present invention controls the conduction and shutdown of the rectifier by detecting the drain-source pressure difference of the rectifier in the generator rectifier, so that the rectifier can have a lower conduction loss and improve The overall efficiency of the generator, the driving method is simple and reliable, energy saving, clean and environmentally friendly; at the same time, the control circuit provided by the invention can greatly reduce the power consumption of the rectifier, reduce the temperature of the rectifier bridge, and improve system reliability.

附图说明Description of drawings

图1是本发明提供的一种同步整流控制电路的整体结构示意图。FIG. 1 is a schematic diagram of the overall structure of a synchronous rectification control circuit provided by the present invention.

图2是本发明提供的一种同步整流控制电路在实施例中的具体电路结构示意图。FIG. 2 is a schematic diagram of a specific circuit structure in an embodiment of a synchronous rectification control circuit provided by the present invention.

图3是本发明提供的一种同步整流控制电路中的上升沿延迟模块在实施例中的电路结构示意图。FIG. 3 is a schematic circuit structure diagram of a rising edge delay module in an embodiment of a synchronous rectification control circuit provided by the present invention.

图4是本发明提供的一种同步整流控制电路的工作流程图。Fig. 4 is a working flowchart of a synchronous rectification control circuit provided by the present invention.

具体实施方式Detailed ways

下面结合附图和具体实施例，详细描述本发明的技术方案。The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

本发明提出的一种同步整流控制电路，通过检测同步整流电路中整流管(即功率MOSFET)的漏源压差来开启和关断整流管。如图1所示，包括电压检测模块、同步整流逻辑控制模块和驱动模块，电压检测模块用于检测整流管(即外置功率MOSFET)的漏极和源极之间电压差，同步整流逻辑控制模块用于控制功率MOSFET管的最小导通时间，避免开启功率MOSFET后发生震荡，驱动模块用于提供栅极驱动。A synchronous rectification control circuit proposed by the present invention turns on and off the rectifier by detecting the drain-source pressure difference of the rectifier (ie power MOSFET) in the synchronous rectifier circuit. As shown in Figure 1, it includes a voltage detection module, a synchronous rectification logic control module and a drive module. The module is used to control the minimum on-time of the power MOSFET to avoid oscillation after turning on the power MOSFET, and the driver module is used to provide gate drive.

如图1和图2所示为电压检测模块的一种实现电路形式，电压检测模块用于检测整流管的漏源电压并产生第一检测信号和第二检测信号，包括第一比较器Comp1、第二比较器Comp2、第一电压源和第二电压源，第一比较器Comp1的同相输入端连接整流管的漏极，其反相输入端连接第一电压源的正向端，其输出端输出第一检测信号；第二比较器Comp2的同相输入端连接第二电压源的正向端，其反相输入端连接整流管的漏极，其输出端输出第二检测信号；第一电压源和第二电压源的负向端连接整流管的源极。一些实施例中，第一比较器Comp1为迟滞比较器，其门限电压为开启阈值电压VTH1和关断阈值电压VTH2；第二比较器Comp2为电压比较器，其比较电压为复位阈值电压VTH3。开启阈值电压VTH1、关断阈值电压VTH2和复位阈值电压VTH3可以通过调节电压源的大小来进行设定。As shown in Figure 1 and Figure 2, it is an implementation circuit form of the voltage detection module, the voltage detection module is used to detect the drain-source voltage of the rectifier and generate the first detection signal and the second detection signal, including the first comparator Comp1, The second comparator Comp2, the first voltage source and the second voltage source, the non-inverting input terminal of the first comparator Comp1 is connected to the drain of the rectifier tube, its inverting input terminal is connected to the positive terminal of the first voltage source, and its output terminal output the first detection signal; the noninverting input terminal of the second comparator Comp2 is connected to the positive terminal of the second voltage source, its inverting input terminal is connected to the drain of the rectifier tube, and its output terminal outputs the second detection signal; the first voltage source The negative end of the second voltage source is connected to the source of the rectifier. In some embodiments, the first comparator Comp1 is a hysteresis comparator, and its threshold voltage is the turn-on threshold voltage V TH1 and the turn-off threshold voltage V TH2 ; the second comparator Comp2 is a voltage comparator, and its comparison voltage is the reset threshold voltage V TH3 . The turn-on threshold voltage V TH1 , the turn-off threshold voltage V TH2 and the reset threshold voltage V TH3 can be set by adjusting the voltage source.

同步整流逻辑控制模块如图2所示，包括最小导通时间产生模块(MOT)、周期性唤醒模块(MCC)、最小消隐时间产生模块(MFT)、第一或门T2和第四反相器T3，最小导通时间产生模块包括第一D触发器D1、第二反相器G1、第二或门G2、第一与非门G3和第一上升沿延迟模块，第二反相器G1的输入端连接第一与非门G3的第一输入端和第一或门T2的输出端，其输出端连接第一D触发器D1的时钟端；第一或门T2的第一输入端连接第一检测信号；第一D触发器D1的数据输入端连接使能信号EN，其复位端连接第二或门G2的输出端，其Q输出端连接第一上升沿延迟模块的输入端，其Q非输出端连接第一与非门G3的第二输入端；第二或门G2的第一输入端连接使能信号的反相信号ENB，其第二输入端连接第四反相器T3的输出端，其第三输入端连接第一上升沿延迟模块的输出端；第四反相器T3的输入端连接第二检测信号；第一与非门G3的输出端作为最小导通时间产生模块的输出端。最小导通时间产生模块的作用在于当整流管导通时，该模块可以让整流管继续导通一端时间，当第一上升沿延迟模块采用图3所示的电路结构时，这个导通时间的长短由第一上升沿延迟模块中的电流源和电容决定。The synchronous rectification logic control module is shown in Figure 2, including the minimum on-time generation module (MOT), the periodic wake-up module (MCC), the minimum blanking time generation module (MFT), the first OR gate T2 and the fourth inverter phase T 3 , the minimum on-time generation module includes a first D flip-flop D 1 , a second inverter G 1 , a second OR gate G 2 , a first NAND gate G 3 and a first rising edge delay module, The input end of the second inverter G1 is connected to the first input end of the first NAND gate G3 and the output end of the first OR gate T2 , and its output end is connected to the clock end of the first D flip-flop D1 ; The first input terminal of an OR gate T2 is connected to the first detection signal; the data input terminal of the first D flip-flop D1 is connected to the enable signal EN, its reset terminal is connected to the output terminal of the second OR gate G2 , and its Q output terminal is connected to the input terminal of the first rising edge delay module, and its Q non-output terminal is connected to the second input terminal of the first NAND gate G3 ; the first input terminal of the second OR gate G2 is connected to the inverting signal of the enable signal ENB, its second input end is connected to the output end of the fourth inverter T3 , its third input end is connected to the output end of the first rising edge delay module; the input end of the fourth inverter T3 is connected to the second detection signal ; The output terminal of the first NAND gate G3 is used as the output terminal of the minimum on-time generation module. The function of the minimum on-time generation module is that when the rectifier is turned on, this module can make the rectifier continue to conduct for one end time. When the first rising edge delay module adopts the circuit structure shown in Figure 3, the on-time The length is determined by the current source and capacitor in the first rising edge delay module.

周期性唤醒模块包括第二D触发器D2、第一与非门G4、第三或门G5、第一与门G6和第二上升沿延迟模块，第二D触发器D2的时钟端连接第一或门T2的输出端，其数据输入端连接第三或门G5的第二输入端和最小导通时间产生模块中第一D触发器D1的Q输出端，其复位端连接第一与非门G4的输出端，其Q输出端连接第一或门T2的第二输入端，其Q非输出端连接第三或门G5的第一输入端；第一与门G6的第一输入端连接第三或门G5的输出端并作为周期性唤醒模块的输出端，其第二输入端连接第一检测信号，其输出端连接第二上升沿延迟模块的输入端；第一与非门G4的第一输入端连接第二上升沿延迟模块的输出端，其第二输入端连接使能信号的反相信号ENB，其第三输入端连接第四反相器T3的输出端。周期性唤醒模块的作用是在整流管的栅驱动波形发生震荡时，将驱动输出在一段时间内屏蔽，当第二上升沿延迟模块采用图3所示的电路结构时，这个屏蔽时间的长短由第二上升沿延迟模块中的电流源和电容决定。The periodic wake-up module includes a second D flip-flop D 2 , a first NAND gate G 4 , a third OR gate G 5 , a first AND gate G 6 and a second rising edge delay module, and the second D flip-flop D 2 The clock terminal is connected to the output terminal of the first OR gate T2 , and its data input terminal is connected to the second input terminal of the third OR gate G5 and the Q output terminal of the first D flip-flop D1 in the minimum on-time generation module, which The reset terminal is connected to the output terminal of the first NAND gate G4 , its Q output terminal is connected to the second input terminal of the first OR gate T2 , and its Q non-output terminal is connected to the first input terminal of the third OR gate G5 ; The first input end of an AND gate G6 is connected to the output end of the third OR gate G5 and used as the output end of the periodic wake-up module, its second input end is connected to the first detection signal, and its output end is connected to the second rising edge delay The input terminal of the module; the first input terminal of the first NAND gate G4 is connected to the output terminal of the second rising edge delay module, its second input terminal is connected to the inversion signal ENB of the enable signal, and its third input terminal is connected to the first Output of quad inverter T3 . The function of the periodic wake-up module is to shield the drive output for a period of time when the gate drive waveform of the rectifier tube oscillates. When the second rising edge delay module adopts the circuit structure shown in Figure 3, the length of the shielding time is determined by The current source and capacitance in the second rising edge delay block are determined.

最小消隐时间产生模块包括第三D触发器D3、第三上升沿延迟模块、第二与门G7、第四或门G8和第五或门G9，第二与门G7的第一输入端连接第一或门T2的输出端，其第二输入端连接最小导通时间产生模块中第一D触发器D1的Q非输出端，其第三输入端连接周期性唤醒模块中第二D触发器D2的Q非输出端，其输出端连接第三D触发器D3的时钟端和第五或门G9的第一输入端；第三D触发器D3的数据输入端连接使能信号EN，其复位端连接第四或门G8的输出端，其Q输出端连接第三上升沿延迟模块的输入端和第五或门G9的第二输入端；第五或门G9的输出端作为最小消隐时间产生模块的输出端；第四或门G8的第一输入端连接第三上升沿延迟模块的输出端，其第二输入端连接周期性唤醒模块中第二D触发器D2的Q输出端，其第三输入端连接第四反相器T3的输出端。最小消隐时间产生模块的作用是当栅驱动关断整流管时，将驱动输出在一段时间内屏蔽，当第三上升沿延迟模块采用图3所示的电路结构时，这个屏蔽时间的长短由第三上升沿延迟模块中的电流源和电容决定。The minimum blanking time generating module includes a third D flip-flop D 3 , a third rising edge delay module, a second AND gate G 7 , a fourth OR gate G 8 and a fifth OR gate G 9 , and the second AND gate G 7 The first input terminal is connected to the output terminal of the first OR gate T2 , its second input terminal is connected to the Q non-output terminal of the first D flip-flop D1 in the minimum on-time generation module, and its third input terminal is connected to the periodic wake-up The Q non-output end of the second D flip-flop D2 in the module, its output end connects the clock end of the third D flip-flop D3 and the first input end of the fifth OR gate G9 ; the third D flip-flop D3 The data input terminal is connected to the enable signal EN, its reset terminal is connected to the output terminal of the fourth OR gate G8 , and its Q output terminal is connected to the input terminal of the third rising edge delay module and the second input terminal of the fifth OR gate G9 ; The output end of the fifth OR gate G9 is used as the output end of the minimum blanking time generation module; the first input end of the fourth OR gate G8 is connected to the output end of the third rising edge delay module, and its second input end is connected to the periodic The third input terminal of the Q output terminal of the second D flip-flop D2 in the wake-up module is connected to the output terminal of the fourth inverter T3 . The function of the minimum blanking time generation module is to shield the drive output for a period of time when the gate driver turns off the rectifier tube. When the third rising edge delay module adopts the circuit structure shown in Figure 3, the length of the shielding time is determined by The current source and capacitance in the third rising edge delay block are determined.

其中使能信号EN为外部给定，使能信号的反相信号ENB可以将使能信号EN通过一个反相器得到，如图2所示，同步整流逻辑控制模块还包括第一反相器T1，第一反相器T1的输入端连接使能信号EN，其输出端输出使能信号的反相信号ENB。使能信号EN和使能信号的反相信号ENB用于复位同步整流逻辑控制模块中的数字电路。The enable signal EN is given externally, and the inversion signal ENB of the enable signal can be obtained by passing the enable signal EN through an inverter. As shown in Figure 2, the synchronous rectification logic control module also includes a first inverter T1 , the input terminal of the first inverter T1 is connected to the enable signal EN, and the output terminal thereof outputs the inversion signal ENB of the enable signal. The enable signal EN and the inverted signal ENB of the enable signal are used to reset the digital circuit in the synchronous rectification logic control module.

第一上升沿延迟模块、第二上升沿延迟模块和第三上升沿延迟模块可以具有相同的结构，用于对上升沿信号进行延迟，其延迟时间由第一电容C1和第一电流源I1决定，对下降沿不产生延迟。下面以第一上升沿延迟模块为例，如图3所示是第一上升沿延迟模块的一种实现电路结构，包括第一电流源I1、第一电容C1、第一MOS管M1、第二或非门T5、第二与非门T6和第一施密特触发器T7，第二与非门T6的第一输入端作为第一上升沿延迟模块的输入端，其第二输入端连接使能信号EN，其输出端连接第一MOS管M1的栅极；第一电容C1的一端连接第一MOS管M1的漏极、第一施密特触发器T7的输入端和第一电流源I1的负向端，其另一端连接第一MOS管M1的源极并接地；第一电流源I1的正向端连接电源电压；第二或非门T5的输入端连接第一施密特触发器T7的输出端，其输出端作为第一上升沿延迟模块的输出端。The first rising edge delay module, the second rising edge delay module and the third rising edge delay module can have the same structure, and are used to delay the rising edge signal, and the delay time is determined by the first capacitor C1 and the first current source I 1 decision, there is no delay on the falling edge. Taking the first rising edge delay module as an example, as shown in Figure 3, it is a realization circuit structure of the first rising edge delay module, including the first current source I 1 , the first capacitor C 1 , and the first MOS transistor M 1 , the second NOR gate T5 , the second NAND gate T6 and the first Schmitt trigger T7 , the first input terminal of the second NAND gate T6 is used as the input terminal of the first rising edge delay module, Its second input end is connected to the enable signal EN, and its output end is connected to the gate of the first MOS transistor M1 ; one end of the first capacitor C1 is connected to the drain of the first MOS transistor M1 , the first Schmitt trigger The input end of T7 and the negative end of the first current source I1 , the other end of which is connected to the source of the first MOS transistor M1 and grounded; the positive end of the first current source I1 is connected to the power supply voltage; the second or The input terminal of the NOT gate T5 is connected to the output terminal of the first Schmitt trigger T7 , and its output terminal is used as the output terminal of the first rising edge delay module.

驱动模块的第一输入端最小导通时间产生模块的输出端，其第二输入端连接周期性唤醒模块的输出端，其第三输入端连接最小消隐时间产生模块的输出端，其输出端连接整流管的栅极。如图2所示是驱动模块的一种实现电路结构，包括第三与门T4、第二或非门T5和驱动输出级，第三与门T4的第一输入端作为驱动模块的第一输入端，其第二输入端连接第二或非门T5的输出端，其输出端连接驱动输出级的输入端；第二或非门T5的第一输入端作为驱动模块的第二输入端，其第二输入端作为驱动模块的第三输入端；驱动输出级包括偶数个级联的反相器，其输出端作为驱动模块的输出端。The first input terminal of the driving module is the output terminal of the minimum on-time generation module, its second input terminal is connected to the output terminal of the periodic wake-up module, its third input terminal is connected to the output terminal of the minimum blanking time generation module, and its output terminal Connect the grid of the rectifier. As shown in Figure 2, it is an implementation circuit structure of the driving module, including the third AND gate T4, the second NOR gate T5 and the driving output stage, and the first input terminal of the third AND gate T4 is used as the first input of the driving module end, its second input end is connected to the output end of the second NOR gate T5, and its output end is connected to the input end of the driving output stage; the first input end of the second NOR gate T5 is used as the second input end of the driving module, and its The second input terminal is used as the third input terminal of the driving module; the driving output stage includes an even number of cascaded inverters, and the output terminal thereof is used as the output terminal of the driving module.

图4为本发明的工作流程图，将本发明提供的一种同步整流控制电路集成到芯片中，当使能信号EN为高(即使能管脚使能)后控制电路开始工作(即进入准备模式)，同时检测芯片供电电压VCC和环境温度是否正常；当供电电压VCC和环境温度满足条件之后第二比较器Comp2等待复位信号(即功率MOSFET漏源压差大于复位阈值电压VTH3)，当检测到的功率MOSFET(即整流管)的漏源压差大于复位阈值电压VTH3，芯片所有逻辑复位，并触发最小消隐时间产生模块，所有逻辑在消隐时间内不工作；经历消隐时间后第二比较器Comp2检测功率MOSFET漏源压差是否在关断阈值电压VTH2和复位阈值电压VTH3之间，若满足条件则逻辑退出复位，开始检测功率MOSFET漏源压差是否满足导通条件(即功率MOSFET漏源压差小于开启阈值电压VTH1)；当迟滞比较器Comp1检测到功率MOSFET漏源压差小于开启阈值电压VTH1时，功率MOSFET导通，触发最小导通时间MOT限制；结束最小导通时间MOT限制后迟滞比较器Comp1开始检测功率MOSFET漏源压差是否大于关闭阈值电压VTH2，若功率MOSFET漏源压差满足条件则关闭功率MOSFET，然后开始等待复位信号Reset，当下一个复位信号Reset来的时候又进入上述流程。Fig. 4 is the work flowchart of the present invention, a kind of synchronous rectification control circuit provided by the present invention is integrated into the chip, when the enable signal EN is high (that is, the pin is enabled), the control circuit starts to work (that is, enters the preparation Mode), while detecting whether the chip power supply voltage V CC and the ambient temperature are normal; when the power supply voltage V CC and the ambient temperature meet the conditions, the second comparator Comp2 waits for the reset signal (that is, the drain-source voltage difference of the power MOSFET is greater than the reset threshold voltage V TH3 ) , when the detected drain-source voltage difference of the power MOSFET (that is, the rectifier) is greater than the reset threshold voltage V TH3 , all the logic of the chip is reset and the minimum blanking time generation module is triggered, and all logics do not work during the blanking time; After the hidden time, the second comparator Comp2 detects whether the drain-source voltage difference of the power MOSFET is between the turn-off threshold voltage V TH2 and the reset threshold voltage V TH3 . Turn-on condition (that is, the power MOSFET drain-source voltage difference is less than the turn-on threshold voltage V TH1 ); when the hysteresis comparator Comp1 detects that the power MOSFET drain-source voltage difference is less than the turn-on threshold voltage V TH1 , the power MOSFET is turned on and the minimum on-time is triggered MOT limit: After the minimum on-time MOT limit is over, the hysteresis comparator Comp1 starts to detect whether the power MOSFET drain-source voltage difference is greater than the turn-off threshold voltage V TH2 , and if the power MOSFET drain-source voltage difference meets the conditions, the power MOSFET is turned off, and then begins to wait for the reset signal Reset, when the next reset signal Reset comes, it will enter the above process again.

综上，本发明提出了一种用于电机发电整流电路的控制电路，通过检测整流电路中整流管(即功率MOSFET)的漏源压差控制功率MOSFET导通和关断，通过检测功率MOSFET的体二极管是否导通控制功率MOSFET，当体二极管导通时控制电路驱动输出高，功率MOSFET导通，当体二极管反偏时控制电路驱动输出低，功率MOSFET耐压。本发明中通过将使能信号EN拉高开始工作，使得功率MOSFET管工作在反向电阻区，在整流过程中主要是MOSFET的沟道电阻流过大电流，实现较低的导通损耗，提高发电机整体效率，起到节约能源，清洁环保的作用；另外本发明提供的控制电路可以大幅降低同步整流电路中整理器的功耗，降低了整流桥的温度，提升了系统可靠性。To sum up, the present invention proposes a kind of control circuit that is used for the rectification circuit of motor power generation, by detecting the drain-source pressure difference of the rectifier tube (i.e. power MOSFET) in the rectification circuit to control the power MOSFET on and off, by detecting the voltage difference of the power MOSFET Whether the body diode is turned on controls the power MOSFET. When the body diode is turned on, the control circuit drives the output high, and the power MOSFET is turned on. When the body diode is reverse-biased, the control circuit drives the output low, and the power MOSFET withstands voltage. In the present invention, the enable signal EN is pulled high to start working, so that the power MOSFET tube works in the reverse resistance region, and in the rectification process, the channel resistance of the MOSFET mainly flows through a large current to achieve lower conduction loss and improve The overall efficiency of the generator plays the role of saving energy and being clean and environmentally friendly; in addition, the control circuit provided by the invention can greatly reduce the power consumption of the finisher in the synchronous rectification circuit, reduce the temperature of the rectifier bridge, and improve system reliability.

可以理解的是，本发明不限于上文示出的精确配置和组件。在不脱离权利要求书的保护范围基础上，可以对上文方法和结构的步骤顺序、细节及操作做出各种修改、改变和优化。It is to be understood that the invention is not limited to the precise configuration and components shown above. Various modifications, changes and optimizations may be made to the step sequence, details and operations of the above methods and structures without departing from the scope of protection of the claims.

Claims (6)

1. a kind of synchronous commutating control circuit, for controlling the rectifying tube in synchronous rectification system, which is characterized in that including voltage Detection module, synchronous rectification Logic control module and drive module,
The voltage detection module is used to detect the drain-source voltage of rectifying tube and generates first detection signal and the second detection signal；
The synchronous rectification Logic control module includes minimum turn-on time generation module, periodic wakeup module, minimum blanking Time generation module, first or door (T2) and the 4th phase inverter (T3),
The minimum turn-on time generation module includes the first d type flip flop (D1), the second phase inverter (G1), second or door (G2), One NAND gate (G3) and the first rise edge delay module, the second phase inverter (G1) input terminal connect the first NAND gate (G3) One input terminal and first or door (T2) output end, output end connect the first d type flip flop (D1) clock end；First or door (T2) first input end connect the first detection signal；First d type flip flop (D1) data input pin connect enable signal (EN), reset terminal connects second or door (G2) output end, Q output connect the first rise edge delay module input End, the non-output ends of Q connect the first NAND gate (G3) the second input terminal；Second or door (G2) first input end connection it is enabled The inversion signal (ENB) of signal, the second input terminal connect the 4th phase inverter (T3) output end, third input terminal connection the The output end of one rise edge delay module；4th phase inverter (T3) input terminal connection it is described second detection signal；First with it is non- Door (G3) output end of the output end as the minimum turn-on time generation module；
The periodic wakeup module includes the second d type flip flop (D2), the first NAND gate (G4), third or door (G5), first and door (G6) and the second rise edge delay module,
Second d type flip flop (D2) clock end connect first or door (T2) output end, data input pin connects third or door (G5) the second input terminal and the minimum turn-on time generation module in the first d type flip flop (D1) Q output, reset terminal Connect the first NAND gate (G4) output end, Q output connect first or door (T2) the second input terminal, the non-output ends of Q connect Meet third or door (G5) first input end；First and door (G6) first input end connection third or door (G5) output end simultaneously As the output end of the periodic wakeup module, the second input terminal connects the first detection signal, output end connection The input terminal of second rise edge delay module；First NAND gate (G4) first input end connect the second rise edge delay module Output end, the second input terminal connect the inversion signal (ENB) of the enable signal, and third input terminal connects the 4th phase inverter (T3) output end；
The minimum blanking time generation module includes third d type flip flop (D3), third rise edge delay module, second and door (G7), the 4th or door (G8) and the 5th or door (G9),
Second and door (G7) first input end connect first or door (T2) output end, the second input terminal connects the minimum First d type flip flop (D in turn-on time generation module1) the non-output ends of Q, third input terminal connects the periodic wakeup mould Second d type flip flop (D in block2) the non-output ends of Q, output end connects third d type flip flop (D3) clock end and the 5th or door (G9) first input end；Third d type flip flop (D3) data input pin connection enable signal (EN), reset terminal connection the 4th Or door (G8) output end, Q output connect third rise edge delay module input terminal and the 5th or door (G9) it is second defeated Enter end；5th or door (G9) output end of the output end as the minimum blanking time generation module；4th or door (G8) One input terminal connects the output end of third rise edge delay module, and the second input terminal connects in the periodic wakeup module the 2-D trigger (D2) Q output, third input terminal connect the 4th phase inverter (T3) output end；
The output end of minimum turn-on time generation module described in the first input end of the drive module, the connection of the second input terminal The output end of the periodic wakeup module, third input terminal connect the output end of the minimum blanking time generation module, Its output end connects the grid of the rectifying tube.
2. synchronous commutating control circuit according to claim 1, which is characterized in that the voltage detection module includes first Comparator (Comp1), the second comparator (Comp2), first voltage source and the second voltage source, first comparator (Comp1) it is same Phase input terminal connects the drain electrode of the rectifying tube, and inverting input connects the forward end of first voltage source, output end output The first detection signal；The forward end of the in-phase input end connection the second voltage source of second comparator (Comp2), reverse phase are defeated Enter the drain electrode that end connects the rectifying tube, output end output the second detection signal；First voltage source and the second voltage source Negative end connect the source electrode of the rectifying tube.
3. synchronous commutating control circuit according to claim 2, which is characterized in that the first comparator (Comp1) is Hysteresis comparator.
4. synchronous commutating control circuit according to claim 1, which is characterized in that the first rise edge delay module, Second rise edge delay module and third rise edge delay module structure having the same, the first rise edge delay module packet Include the first current source (I1), the first capacitance (C1), the first metal-oxide-semiconductor (M1), the second nor gate (T5), the second NAND gate (T6) and first Schmidt trigger (T7), the second NAND gate (T6) input terminal of the first input end as the first rise edge delay module, Its second input terminal connects the enable signal (EN), and output end connects the first metal-oxide-semiconductor (M1) grid；First capacitance (C1) One end connect the first metal-oxide-semiconductor (M1) drain electrode, the first Schmidt trigger (T7) input terminal and the first current source (I1) it is negative Xiang Duan, the other end connect the first metal-oxide-semiconductor (M1) source electrode and ground connection；First current source (I1) forward end connect supply voltage； Second nor gate (T5) input terminal connect the first Schmidt trigger (T7) output end, output end is as on described first Rise the output end along Postponement module.
5. synchronous commutating control circuit according to claim 1, which is characterized in that the synchronous rectification Logic control module Further include the first phase inverter (T1) of the inversion signal for generating the enable signal (EN), the input of the first phase inverter (T1) End connects the enable signal (EN), and output end exports the inversion signal (ENB) of the enable signal.
6. synchronous commutating control circuit according to claim 1, which is characterized in that the drive module includes third and door (T4), the second nor gate (T5) and driving output stage, the first input end of third and door (T4) as the drive module the One input terminal, the second input terminal connect the output end of the second nor gate (T5), and output end connects the driving output stage Input terminal；Second input terminal of the first input end of second nor gate (T5) as the drive module, the second input terminal are made For the third input terminal of the drive module；The driving output stage includes the cascade phase inverter of even number, output end conduct The output end of the drive module.
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