CN108541112B - An LED short-circuit protection circuit for BUCK-BOOST LED drive circuit - Google Patents

Abstract

The invention relates to the technical field of LED driving circuits, in particular to an LED short-circuit protection circuit for a BUCK-BOOST LED driving circuit, which comprises a comparator, a timer, a first RS trigger, a first NOT gate, a second NOT gate, a third NOT gate and a first NOT gate, wherein the timer comprises a first D trigger, a second D trigger, a third D trigger, a fourth D trigger, a fifth D trigger, a sixth D trigger, a second RS trigger, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate and an eleventh NOT gate; when the invention is applied to the BUCK-BOOST LED drive circuit, the system stability is improved, the chip and even the frying machine are prevented from being damaged under the condition of short circuit of the LED, and the input power consumption of the system is reduced under the condition of short circuit of the LED.

Description

An LED short-circuit protection circuit for BUCK-BOOST LED drive circuit

Technical Field

The present invention relates to the technical field of LED drive circuits, and in particular to an LED short-circuit protection circuit for a BUCK-BOOST LED drive circuit.

Background technique

At present, most of the Buck-Boost LED driving circuits in the domestic market use traditional voltage technology and require an external power supply system, which provides the VCC voltage from the positive end of the LED load through a resistor and a diode. Due to market needs, the inventor has previously developed a BUCK-BOOST LED driving circuit that uses an integrated high-voltage JFET power supply. This driving circuit does not require an external power supply circuit, so it is simpler in system application solutions. However, due to the change in circuit structure, it also has new problems in LED short-circuit protection.

The traditional Buck-Boost LED drive circuit does not use high-voltage integrated technology. Its power supply system is provided by the startup resistor and the load through the resistor and diode. When the load LED is short-circuited, the load power supply system through the resistor and diode will also be short-circuited to the ground. At this time, the VCC voltage drops to the UVLO lower voltage, and the system is shut down. Then the VCC is powered on through the startup resistor, and this is repeated. The VCC voltage is a triangular waveform, and the system keeps turning on and off.

When the Buck-Boost LED driver circuit integrates a built-in high-voltage JFET, the startup resistor and the power supply loop from the load through the resistor and the diode are omitted, and the system VCC voltage is obtained by the internal JFET through the high-voltage to low-voltage module. By adjusting the size of the JFET, different currents can be provided to the chip. Its circuit schematic is shown in Figure 1. When the load LED is short-circuited, since the system has no power supply loop and the system power supply is provided by the built-in high-voltage JFET, the VCC voltage will remain unchanged and will not be powered off. At this time, due to the short circuit of the load, the time for the inductor to discharge through the load will be very long, the voltage obtained by the internal calculation circuit is low, the voltage of the COMP pin will rise rapidly, the on-time of the high-voltage MOSFET will increase, and the current flowing through the ISEN sampling resistor will increase. Since the Ton_max (maximum on-time) and Toff_max (maximum demagnetization time) are set internally, the system will work in the Ton_max and Toff_max working states. Since the load LED is short-circuited, the system cannot discharge all the current of the inductor within the Toff_max time, and the current of the inductor will become larger and larger. When it increases to a certain extent, the high-voltage MOSFET will burn out and break down, causing the circuit to fail.

Summary of the invention

In view of the problems in the prior art, the present invention provides an LED short-circuit protection circuit for a BUCK-BOOST LED driving circuit.

In order to achieve the above technical objectives, the technical solution of the present invention is:

An LED short circuit protection circuit for a BUCK-BOOST LED driving circuit comprises a comparator, a timer, a first RS trigger, a first NOT gate, a second NOT gate, a third NOT gate and a first NAND gate;

The timer includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a second RS flip-flop, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, a tenth NAND gate and an eleventh NAND gate;

The output terminal of the comparator is connected to the first input terminal of the first NAND gate;

The Q output terminal of the second D flip-flop is connected to the first input terminal of the second NAND gate, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the third D flip-flop;

The Q output terminal of the third D flip-flop is connected to the first input terminal of the third AND gate, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the fourth D flip-flop;

The Q output terminal of the fourth D flip-flop is connected to the first input terminal of the second AND gate, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the fifth D flip-flop;

The Q output terminal of the fifth D flip-flop is connected to the first input terminal of the first AND gate, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the sixth D flip-flop;

The Q output terminal of the sixth D flip-flop is connected to the second input terminal of the first AND gate, and the Q output terminal is connected to the D input terminal of the sixth D flip-flop;

The output terminal of the first AND gate is connected to the second input terminal of the second AND gate;

The output terminal of the second AND gate is connected to the second input terminal of the third AND gate;

The output terminal of the third AND gate is connected to the second input terminal of the second NAND gate;

The output terminal of the second NAND gate is connected to the input terminal of the fourth NOT gate and the input terminal of the seventh NOT gate;

The output terminal of the fourth NOT gate is connected to the first input terminal of the third NAND gate;

The output terminal of the fifth NOT gate is connected to the second input terminal of the third NAND gate;

The output terminal of the third NAND gate is connected to the input terminal of the sixth NAND gate;

The output terminal of the sixth NOT gate is connected to the second input terminal of the first NAND gate;

The output end of the seventh NOT gate is connected to the input end of the eighth NOT gate;

The output terminal of the eighth NOT gate is connected to the first input terminal of the fourth AND gate;

The output terminal of the ninth NOT gate is connected to the S input terminal of the second RS flip-flop;

The output terminal of the tenth NOT gate is connected to the R input terminal of the second RS flip-flop;

A Q output terminal of the second RS flip-flop is connected to a D input terminal of the first D flip-flop;

The Q output terminal of the first D flip-flop is connected to the second input terminal of the fourth AND gate;

The third input terminal of the fourth AND gate is connected to the R input terminal of the first D flip-flop, and the output terminal is connected to the input terminal of the eleventh NOT gate;

The output end of the eleventh NOT gate is connected to the R input end of the second D flip-flop, the R input end of the third D flip-flop, the R input end of the fourth D flip-flop, the R input end of the fifth D flip-flop, the R input end of the sixth D flip-flop and the input end of the first NOT gate;

The output terminal of the first NOT gate is connected to the R input terminal of the first RS flip-flop;

The S input terminal of the first RS flip-flop is connected to the input terminal of the ninth NOT gate, and the Q output terminal is connected to the input terminal of the second NOT gate NOT2;

The output terminal of the second NOT gate is connected to the third input terminal of the first NAND gate;

The output terminal of the first NAND gate is connected to the input terminal of the third NAND gate;

The non-inverting input terminal, the inverting input terminal, the CP input terminal of the second D flip-flop, the input terminal of the fifth NOT gate, the S input terminal of the first RS flip-flop, the input terminal of the tenth NOT gate and the CP input terminal and the R input terminal of the first D flip-flop serve as input terminals of the LED short-circuit protection circuit, and the output terminal of the third NOT gate serves as an output terminal of the LED short-circuit protection circuit.

Preferably, the first RS trigger is composed of two NOR gates.

Preferably, the second RS flip-flop is composed of two NAND gates.

It can be seen from the above description that the present invention has the following advantages: when the present invention is applied to the BUCK-BOOST LED driving circuit, it can not only improve the stability of the system and prevent chip damage or even machine crash in the case of LED short circuit, but also reduce the system input power consumption in the case of LED short circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an existing Buck-Boost LED driving circuit;

Fig. 2 is a circuit structure diagram of the present invention;

FIG3 is a diagram showing the internal circuit structure of a timer of the present invention;

FIG4 is a timing waveform diagram of the present invention;

FIG. 5 is a circuit structure diagram of the present invention applied to a Buck-Boost LED driving circuit.

Detailed ways

2 to 5 , a specific embodiment of the present invention is described in detail, but no limitation is imposed on the claims of the present invention.

As shown in FIG. 2 and FIG. 3 , an LED short circuit protection circuit for a BUCK-BOOST LED driving circuit includes a comparator, a timer, a first RS trigger RS1, a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3 and a first NAND gate NAND1;

The first RS flip-flop RS1 is composed of two NOR gates, the timer includes a first D flip-flop DFFR1, a second D flip-flop DFFR2, a third D flip-flop DFFR3, a fourth D flip-flop DFFR4, a fifth D flip-flop DFFR5, a sixth D flip-flop DFFR6, a second RS flip-flop RS2, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NOT gate NOT4, a fifth NOT gate NOT5, a sixth NOT gate NOT6, a seventh NOT gate NOT7, an eighth NOT gate NOT8, a ninth NOT gate NOT9, a tenth NOT gate NOT10 and an eleventh NOT gate NOT11, and the second RS flip-flop RS2 is composed of two NAND gates NAND;

The output terminal of the comparator is connected to the first input terminal of the first NAND gate NAND1;

The Q output terminal of the second D flip-flop DFFR2 is connected to the first input terminal of the second NAND gate NAND2, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the third D flip-flop DFFR3;

The Q output terminal of the third D flip-flop DFFR3 is connected to the first input terminal of the third AND gate AND3, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the fourth D flip-flop DFFR4;

The Q output terminal of the fourth D flip-flop DFFR4 is connected to the first input terminal of the second AND gate AND2, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the fifth D flip-flop DFFR5;

The Q output terminal of the fifth D flip-flop DFFR5 is connected to the first input terminal of the first AND gate AND1, and the Q output terminal is connected to its own D input terminal and the CP input terminal of the sixth D flip-flop DFFR6;

The Q output terminal of the sixth D flip-flop DFFR6 is connected to the second input terminal of the first AND gate AND1. The output terminal is connected to its own D input terminal;

An output terminal of the first AND gate AND1 is connected to a second input terminal of the second AND gate AND2;

An output terminal of the second AND gate AND2 is connected to a second input terminal of the third AND gate AND3;

An output terminal of the third AND gate AND3 is connected to a second input terminal of the second NAND gate NAND2;

The output terminal of the second NAND gate NAND2 is connected to the input terminal of the fourth NOT gate NOT4 and the input terminal of the seventh NOT gate NOT7;

An output terminal of the fourth NOT gate NOT4 is connected to a first input terminal of the third NAND gate NAND3;

An output terminal of the fifth NOT gate NOT5 is connected to a second input terminal of the third NAND gate NAND3;

An output terminal of the third NAND gate NAND3 is connected to an input terminal of a sixth NOT gate NOT6;

An output terminal of the sixth NOT gate NOT6 is connected to a second input terminal of the first NAND gate NAND1;

The output end of the seventh NOT gate NOT7 is connected to the input end of the eighth NOT gate NOT8;

An output terminal of the eighth NOT gate NOT8 is connected to a first input terminal of the fourth AND gate AND4;

The output terminal of the ninth NOT gate NOT9 is connected to the S input terminal of the second RS flip-flop RS2;

The output terminal of the tenth NOT gate NOT10 is connected to the R input terminal of the second RS flip-flop RS2;

A Q output terminal of the second RS flip-flop RS2 is connected to a D input terminal of the first D flip-flop DFFR1;

A Q output terminal of the first D flip-flop DFFR1 is connected to a second input terminal of the fourth AND gate AND4;

A third input terminal of the fourth AND gate AND4 is connected to the R input terminal of the first D flip-flop DFFR1, and an output terminal thereof is connected to the input terminal of the eleventh NOT gate NOT11;

The output terminal of the eleventh NOT gate NOT11 is connected to the R input terminal of the second D flip-flop DFFR2, the R input terminal of the third D flip-flop DFFR3, the R input terminal of the fourth D flip-flop DFFR4, the R input terminal of the fifth D flip-flop DFFR5, the R input terminal of the sixth D flip-flop and the input terminal of the first NOT gate NOT1;

An output terminal of the first NOT gate NOT1 is connected to an R input terminal of the first RS flip-flop RS1;

The S input terminal of the first RS flip-flop RS1 is connected to the input terminal of the ninth NOT gate NOT9, and the Q output terminal is connected to the input terminal of the second NOT gate NOT2;

An output terminal of the second NOT gate NOT2 is connected to a third input terminal of the first NAND gate NAND1;

An output terminal of the first NAND gate NAND1 is connected to an input terminal of a third NOT gate NOT3;

The non-inverting input terminal, the inverting input terminal, the CP input terminal of the second D flip-flop DFFR2, the input terminal of the fifth NOT gate NOT5, the S input terminal of the first RS flip-flop RS1, the input terminal of the tenth NOT gate NOT10 and the CP input terminal and the R input terminal of the first D flip-flop DFFR1 serve as input terminals of the LED short-circuit protection circuit, and the output terminal of the third NOT gate NOT3 serves as the output terminal of the LED short-circuit protection circuit.

The working principle of the present invention is:

The non-inverting input of the comparator is connected to the VREF1 signal, the inverting input of the comparator is connected to the ZCD signal, the CP input of the second D flip-flop DFFR2 is connected to the DRV_DM1 signal, the input of the fifth NOT gate NOT5 is connected to the DRV_DM2 signal, the S input of the first RS flip-flop RS1 is connected to the TOFF_MAX signal, the input of the tenth NOT gate is connected to the LEB2 signal, the CP input of the first D flip-flop DFFR1 is connected to the LEB1 signal, and the R input of the first D flip-flop DFFR1 is connected to the EN signal;

As shown in FIG2 , it is a circuit structure diagram of the LED short-circuit protection circuit of the present invention. The EN signal is the UVLO signal of the system (i.e., Buck-Boost LED drive circuit, hereinafter referred to as the system). When the system voltage reaches UVLO_ON, the EN signal jumps from a low potential to a high potential, the timer circuit is initialized, and starts working. At this time, the system starts working, VREF1 is the internally set reference voltage (this circuit is set to 50mv), and the ZCD voltage is the voltage obtained by the load through the resistor voltage divider (this voltage is also used to set the LED open circuit protection point). Under normal circumstances, if the LED is not short-circuited, the ZCD voltage is relatively high and greater than 50mv, and the typical value is generally about 1V. The CMP_ZCD signal output by the comparator outputs a low potential during the detection period, and the OUT signal output is a low potential. When the system is initially powered on, since the load voltage has not been established, the ZCD signal is lower than 50mv. At this time, the system works in the maximum demagnetization time mode. TOFF_MAX is a square wave with a duty cycle. When continuous TOFF_MAX signals appear, the timer starts counting. When the timer counts the internally set value continuously (32 cycles for this circuit), the timer COUNT outputs a high potential. If the ZCD signal is lower than 50mv at this time, the CMP_ZCD output is a high potential, and the OUT signal output is a high potential, triggering the system LED short circuit protection function. At this time, the system will turn off the internal JFET, and the VCC voltage will begin to decrease to the UVLO voltage. The system will start to restart and re-detect whether the LED is short-circuited. This will be repeated. When the LED short-circuit fault is removed, the ZCD voltage signal begins to rise and is greater than 50mv. CMP_ZCD outputs a low potential during the detection cycle, and the OUT signal output is a low potential. At this time, the system begins to exit the maximum demagnetization working mode, and the TOFF_MAX signal becomes a low potential. The timer stops working and is initialized. When the LED is short-circuited, it enters the maximum demagnetization working mode, TOFF_MAX outputs a square wave, and the timer starts working. At the same time, the timer must count 32 cycles continuously before it is considered that the load LED is short-circuited. This is to prevent false triggering due to system voltage fluctuations.

The internal logic of the timer is shown in Figure 3, and its working principle is as follows: when the system starts working and UVLO power-on is completed, the EN signal becomes high, and the EN signal resets all D flip-flops and starts timing. When the output LED is not short-circuited, TOFF_MAX has no square wave signal and is low. The LEB2 signal is a delay signal of the DRV signal (DRV signal is a drive signal for driving the power MOSFET, and DRV_DM1 and DRV_DM2 are demagnetization signals). The second RS flip-flop is reset every cycle, and the second RS flip-flop outputs a low potential to the D end of the first D flip-flop DFFR1. LEB1 is a sampling signal (the sampling signal is obtained by processing the DRV signal), which controls the CP input end of the first D flip-flop DFFR1. At this time, it is sampled to a low potential, and the Q end output of the first D flip-flop DFFR1 is a low potential, then the RST output is a low potential, the second D flip-flop DFFR2, the third D flip-flop DFFR3, the fourth D flip-flop DFFR4, the fifth D flip-flop DFFR5, and the sixth D flip-flop DFFR6 remain in the reset state, the timer stops working, and COUNT remains at a low potential. When the LED load is short-circuited, since ZCD becomes about 0V, the system will work in the maximum demagnetization time mode. At this time, TOFF_MAX starts to output a square wave waveform, and the second RS trigger output is high. The first D trigger DFFR1 samples the high potential and outputs a high potential, then the RST signal is high. At this time, the timer starts to work. When 32 cycles are counted, COUNT outputs a high potential, triggering the LED short-circuit protection. The system turns off the JFET power supply high-voltage tube, and the VCC voltage drops. When it drops to the UVLO lower voltage, the system starts to power on again. Repeat this process. When 32 cycles are not counted, the system returns to normal. Since the TOFF_MAX signal is low, the timer will be reset, which can avoid system mis-triggering caused by the current voltage and other interference.

The timing waveform diagram of the present invention is shown in FIG4 , and the circuit structure diagram of the present invention applied to the Buck-Boost LED driving circuit shown in FIG1 is shown in FIG5 .

In summary, the present invention has the following advantages: when the present invention is applied to the BUCK-BOOST LED driving circuit, it can not only improve the stability of the system and prevent chip damage or even machine crash in the case of LED short circuit, but also reduce the system input power consumption in the case of LED short circuit.

It is understood that the above specific description of the present invention is only used to illustrate the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that the present invention can still be modified or replaced by equivalents to achieve the same technical effects; as long as the use requirements are met, they are within the protection scope of the present invention.

Claims (1)

1. An LED short-circuit protection circuit for a BUCK-BOOST LED drive circuit, which is characterized in that: the device comprises a comparator, a timer, a first RS trigger, a first NOT gate, a second NOT gate, a third NOT gate and a first NAND gate;

the timer includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a second RS flip-flop, a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, a sixth and gate, a seventh and gate, an eighth and gate, a ninth and gate, a tenth and eleventh and gate;

the output end of the comparator is connected with the first input end of the first NAND gate;

the Q output end of the second D trigger is connected with the first input end of the second NAND gate, and the Q output end of the second D trigger is connected with the D input end of the second D trigger and the CP input end of the third D trigger;

the Q output end of the third D trigger is connected with the first input end of the third AND gate, and the Q output end of the third D trigger is connected with the D input end of the third D trigger and the CP input end of the fourth D trigger;

the Q output end of the fourth D trigger is connected with the first input end of the second AND gate, and the Q output end of the fourth D trigger is connected with the D input end of the fourth D trigger and the CP input end of the fifth D trigger;

the Q output end of the fifth D trigger is connected with the first input end of the first AND gate, and the Q output end of the fifth D trigger is connected with the D input end of the fifth D trigger and the CP input end of the sixth D trigger;

the Q output end of the sixth D trigger is connected with the second input end of the first AND gate, and the Q output end of the sixth D trigger is connected with the D input end of the sixth D trigger;

the output end of the first AND gate is connected with the second input end of the second AND gate;

the output end of the second AND gate is connected with the second input end of the third AND gate;

the output end of the third AND gate is connected with the second input end of the second NAND gate;

the output end of the second NAND gate is connected with the input end of the fourth NAND gate and the input end of the seventh NAND gate;

the output end of the fourth NAND gate is connected with the first input end of the third NAND gate;

the output end of the fifth NOT gate is connected with the second input end of the third NOT gate;

the output end of the third NAND gate is connected with the input end of the sixth NAND gate;

the output end of the sixth NOT gate is connected with the second input end of the first NOT gate;

the output end of the seventh NOT gate is connected with the input end of the eighth NOT gate;

the output end of the eighth NOT gate is connected with the first input end of the fourth AND gate;

the output end of the ninth NOT gate is connected with the S input end of the second RS trigger;

the output end of the tenth NOT gate is connected with the R input end of the second RS trigger;

the Q output end of the second RS trigger is connected with the D input end of the first D trigger;

the Q output end of the first D trigger is connected with the second input end of the fourth AND gate;

the third input end of the fourth AND gate is connected with the R input end of the first D trigger, and the output end of the fourth AND gate is connected with the input end of the eleventh NOT gate;

the output end of the eleventh NOT gate is connected with the R input end of the second D trigger, the R input end of the third D trigger, the R input end of the fourth D trigger, the R input end of the fifth D trigger, the R input end of the sixth D trigger and the input end of the first NOT gate;

the output end of the first NOT gate is connected with the R input end of the first RS trigger;

the S input end of the first RS trigger is connected with the input end of the ninth NOT gate, and the Q output end of the first RS trigger is connected with the input end of the second NOT gate NOT 2;

the output end of the second NOT gate is connected with the third input end of the first NOT gate;

the output end of the first NAND gate is connected with the input end of the third NAND gate;

the in-phase input end, the reverse phase input end, the CP input end of the second D trigger, the input end of the fifth NOT gate, the S input end of the first RS trigger, the input end of the tenth NOT gate, the CP input end and the R input end of the first D trigger are used as the input end of the LED short-circuit protection circuit, and the output end of the third NOT gate is used as the output end of the LED short-circuit protection circuit;

the first RS trigger consists of two NOR gates;

the second RS flip-flop is constituted by two nand gates.