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CN108536623A - Multichannel NAND Flash controllers and movable storage device - Google Patents

Multichannel NAND Flash controllers and movable storage device Download PDF

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Publication number
CN108536623A
CN108536623A CN201810364432.9A CN201810364432A CN108536623A CN 108536623 A CN108536623 A CN 108536623A CN 201810364432 A CN201810364432 A CN 201810364432A CN 108536623 A CN108536623 A CN 108536623A
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China
Prior art keywords
flash
data
host
buffer
controllers
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Pending
Application number
CN201810364432.9A
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Chinese (zh)
Inventor
杨继光
吴大畏
李晓强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen City A Microelectronics LLC
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Shenzhen City A Microelectronics LLC
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Priority to CN201810364432.9A priority Critical patent/CN108536623A/en
Publication of CN108536623A publication Critical patent/CN108536623A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1684Details of memory controller using multiple buses
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1673Details of memory controller using buffers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses a kind of multichannel NAND Flash controllers and movable storage device, the multichannel NAND Flash controllers include:MCU kernels and the Flash master controls for corresponding to flash storage respectively;The MCU kernels, read write command for obtaining host transmission, the read write command is converted into Flash operational order sequences, by the Flash operational orders sequence writing commands buffer, the first dma controller is controlled simultaneously, completes data write-in and read operation between Host and data buffer;The Flash master controls complete data write-in and read operation between data buffer and flash storage by controlling flash storage and the second dma controller.Multichannel NAND Flash controllers provided by the invention complete the write-in to Flash and read operation, compared with other storage master controls need complicated interface protocol, more simple and flexible reduces development cost by being interacted with the I/O resource of general MCU.

Description

Multichannel NAND Flash controllers and movable storage device
Technical field
The present invention relates to storage control field more particularly to a kind of multichannel NAND Flash controllers and mobile storages Equipment.
Background technology
Currently there are Flash storage controls, from interface type classification have universal serial bus It is (Universal Serial Bus, USB), embedded multi-media card (Embedded Multi Media Card, EMMC), fast Fast file system (Unified File System, UFS), Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) and high speed serialization computer expansion bus (Peripheral Component Interconnect Express, PCIE) etc., in single channel application scenarios, the above different agreement interface can meet different Rate requirement.
It is as each to different vendor's performance in used in scene system in view of the application scenarios for needing to be extended to more data paths Different controller, and need independent data storage and access access, multiple interfaces agreement in this case increase whole The complexity and development difficulty of collaboration system, and the controller of certain manufacturers does not store the corresponding protocol interface of master control, Increase design difficulty.
Invention content
The main purpose of the present invention is to provide a kind of multichannel NAND Flash controllers and movable storage devices, it is intended to Solution provides agile and all-purpose interactive interface between various host and Flash controller master controls, reduces the technology of development cost Problem.
To achieve the above object, the present invention provides a kind of multichannel NAND Flash controllers, the multichannel NAND Flash controllers include MCU kernels and correspond to the Flash master controls of flash storage respectively;
The read write command is converted to Flash operations by the MCU kernels, the read write command for obtaining host transmission The Flash operational orders sequence is sent to corresponding command buffer, and controls the first dma controller by instruction sequence, complete At between host and data buffer data write-in and read operation;
The Flash master controls, the Flash operational order sequences for receiving the command buffer, according to the Flash Operational order sequence simultaneously controls the second dma controller, and second dma controller is to correspond to connect with several command buffers The dma controller connect completes data write-in and read operation between data buffer and flash storage.
Preferably, the MCU kernels are additionally operable to obtain the read write command that the host is sent, by the read write command into Row caching, queuing and merging treatment.
Preferably, the MCU kernels are additionally operable to obtain the read write command that the host is sent, according to preset algorithm by institute It states read write command and is converted to Flash operational order sequences, Flash operational order sequences include Flash command sequences and to second The transmission control instruction of dma controller, and the operational order sequence is sent to order corresponding with the Flash master controls and is delayed Storage.
Preferably, the Flash master controls are additionally operable to the data information of data buffer generating corresponding Error Correction of Coding simultaneously Data information after coding is sent to the flash storage.
Preferably, the Flash master controls are additionally operable to receive the data information that the flash storage obtains, and to described Data information error correction decoding is obtained, and the data information after error correction decoding is sent to data buffer.
Preferably, the multichannel NAND Flash controllers further include:The order for corresponding to the Flash master controls respectively is slow Storage and data buffer;
The command buffer, the Flash operational order sequences sent for receiving the MCU kernels;
The data buffer, the data information to be written sent when host is written for receiving the host, host are read The data information of flash storage is read when taking for receiving the Flash master controls.
Preferably, the data buffer, for when data to be written are written in host, receiving waiting for for the host transmission Data are written, when host reads data, obtain the data information that flash storage is read in the Flash master controls.
Preferably, first dma controller, is controlled by MCU kernels, executes the transmission control instruction of the MCU kernels, The data information of the host transmission is received according to the transmission control instruction and the data buffer is written into data information Or the data information of the data buffer is sent to the host;
Second dma controller, is controlled by Flash master controls, is additionally operable to execute the transmission control in the command buffer System instruction, will be in the digital independent of flash storage to the data buffer or by institute according to the transmission control instruction State the data write-in flash storage of data buffer.
Preferably, the MCU kernels connect the host by the control line of default number of branches, and the Flash master controls pass through The data line of default number of branches connects the host.
In addition, to achieve the above object, the present invention also proposes that a kind of movable storage device, the movable storage device include Flash storage and multichannel NAND Flash controllers as described above, the multichannel NAND Flash controllers connection The flash storage.
Multichannel NAND Flash controllers provided by the present invention, the multichannel NAND Flash controllers include MCU kernels and the Flash master controls for corresponding to flash storage respectively;The MCU kernels, the read-write for obtaining host transmission refer to It enables, the read write command is converted into Flash operational order sequences, the Flash operational orders sequence writing commands are cached Device, while the first dma controller is controlled, complete data write-in and read operation between Host and data buffer;It is described Flash master controls, the Flash operational order sequences for executing corresponding command buffer, by controlling flash storage and second Dma controller completes data write-in and read operation between data buffer and flash storage.It is provided by the invention more Channel NAND Flash controllers are interacted by the I/O resource of general MCU with the multichannel NAND Flash controllers, are completed Write-in to Flash and read operation, compared with other storage master controls need complicated interface protocol, more simple and flexible reduces Development cost.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with The structure shown according to these attached drawings obtains other attached drawings.
Fig. 1 is the circuit structure diagram of one embodiment of multichannel NAND Flash controllers of the present invention;
The structural schematic diagram of Fig. 2 one embodiments of movable storage device of the present invention.
Drawing reference numeral explanation:
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation describes, it is clear that described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Base Embodiment in the present invention, those of ordinary skill in the art obtained without creative efforts it is all its His embodiment, shall fall within the protection scope of the present invention.
If it is to be appreciated that related in the embodiment of the present invention directionality instruction (such as up, down, left, right, before and after ...), Then directionality instruction be only used for explaining relative position relation under a certain particular pose (as shown in the picture) between each component, Motion conditions etc., if the particular pose changes, directionality instruction also correspondingly changes correspondingly.
If in addition, relating to the description of " first ", " second " etc. in the embodiment of the present invention, it is somebody's turn to do " first ", " second " etc. Description be used for description purposes only, be not understood to indicate or imply its relative importance or implicitly indicate indicated skill The quantity of art feature." first " is defined as a result, the feature of " second " can explicitly or implicitly include at least one spy Sign.In addition, the technical solution between each embodiment can be combined with each other, but must be with those of ordinary skill in the art's energy It is enough realize based on, when the knot that conflicting or cannot achieve when will be understood that this technical solution occurs in the combination of technical solution Conjunction is not present, also not the present invention claims protection domain within.
Referring to Fig.1, the structural schematic diagram of one embodiment of multichannel NAND Flash controllers of the present invention is proposed, it is described mostly logical Road NAND Flash controllers 100 include MCU kernels 10 and correspond to the Flash master controls 30 of flash storage 20 respectively.
The MCU kernels 10 connect host 90 by the interface control line 120 of default number of branches, and the Flash master controls 30 are logical The interface data wire 50 for crossing default number of branches connects the host 90, and the MCU kernels 10 connect institute by MCU kernels control line 40 Flash master controls 30 are stated, in the present embodiment, the bus interface by designing default number of branches carries out the distribution of data, and will be described Bus is divided into interface data wire 50 and interface control line 120, and number is realized by the interface data wire 50 and interface control line 120 According to transmitted in parallel, such as by the interface data wire 50 be used to send the data information of the host 90, the interface control Line 120 processed is used to send the control instruction of the host 90.
In the present embodiment, the connection with MCU kernels 10 and Flash master controls 30 can be realized by interface bus, it is described Interface bus is mainly made of 1 group interface control line 120 and 4 group interface data lines 50, and the interface control line 120 connects described Host 90 and the MCU kernels 10, the interface control line 120 divide for read-write control line 120, command address control line 120, make Energy control line 120, the MCU kernels control line 40 connect the MCU kernels 10 and Flash master controls 30, the Flash master controls 30 can be multiple, and multiple Flash master controls 30 correspond to multiple flash storages 20 respectively, and the interface bus can be multigroup, sheet Embodiment is not restricted this.
The MCU kernels 10, the read write command for obtaining the transmission of host 90, Flash is converted to by the read write command The Flash operational orders sequence is sent to corresponding command buffer 60, and controls the first DMA controls by operational order sequence Device 80 processed completes data write-in and read operation between host 90 and data buffer 70.
In the concrete realization, the MCU kernels 10 are used to obtain the read write command of the transmission of host 90, by the read write command It is converted to Flash operational order sequences and is sent to the Flash master controls 30;The Flash master controls 30, for described in reception The operational order sequence that MCU kernels 10 are sent, when host write operation, obtain the data to be written of the transmission of the host 90, according to The data to be written are written in corresponding flash storage 20 read write command, and when host read operation is similar.Pass through General interface data wire 50 and interface control line 120 handle the order transmission of host 90 and Flash master controls 30 and data pass It is defeated, multiple interfaces agreement need not be established, is achieved the purpose that cost-effective.
It is understood that there is MCU kernels 10 in storage device, Flash master controls 30 and flash storage 20 are described MCU kernels 10 are for running the primary control program stored in flash storage 20, and the primary control program is to flash storage 20 It when carrying out volume production, is stored in flash storage 20, to which MCU kernels 10 and Flash master controls 30 can pass through flash storage The data received are stored in flash storage 20 by the primary control program in 20, or are read and be stored in flash storage 20 Data.
In the present embodiment, the multichannel NAND Flash controllers be equipped with multiple Flash master controls 30 and with it is described The flash storage 20 that Flash master controls 30 are separately connected, Flash master controls 0 as shown in Figure 1, Flash master controls 1, Flash master Control 2 etc. and the flash storage 20 being separately connected with the Flash master controls 30, to realize parallel processing.
The Flash master controls 30 receive the Flash operational order sequences of the command buffer 70, according to the Flash Operational order sequence simultaneously controls the second dma controller 110, and second dma controller 110 is and several command buffers 60 1 One dma controller being correspondingly connected with completes the data write-in between data buffer 70 and flash storage 20 and reads behaviour Make.
The Flash master controls 30 are in the data to be written and the MCU kernels 10 hair for receiving the transmission of the host 90 When the write operation Flash operational order sequences sent, the data to be written are written according to the Flash operational orders sequence In corresponding flash storage 20.
The Flash master controls 30 are additionally operable to when the host 90 sends read data operation, and the MCU kernels 10 are sent The Flash operational order sequences of read operation, host 90 is sent to by the digital independent in flash storage 20.
It should be noted that the Flash master controls 30 connect the host 90, each Flash by interface data wire 50 Master control 30 connects the host 90 by individual interface data wire 50, and the Flash master controls 30 can pass through the interface data Data information is sent in target Flash master controls 30 by line 50.
The MCU kernels 10 are additionally operable to obtain the read write command that the host is sent, according to preset algorithm by the read-write Instruction is converted to Flash operational order sequences, and Flash operational order sequences include Flash command sequences and control the 2nd DMA The transmission control instruction of device, and the operational order sequence is sent to command buffer corresponding with the Flash master controls.
The multichannel NAND Flash controllers 100 that the present embodiment is provided, the multichannel NAND Flash controllers 100 include MCU kernels 10 and correspond to the Flash master controls 30 of flash storage 20 respectively;The MCU kernels 10, for obtaining master The read write command that machine 90 is sent, is converted to Flash operational order sequences by the read write command and is sent to the Flash master controls 30;When host write operation, the Flash master controls 30, the Flash operational order sequences sent for executing the MCU kernels 10 Row, and the data to be written of the transmission of the host 90 are obtained, according to the Flash operational orders sequence by the data to be written It is written in corresponding flash storage 20;When host read operation, the Flash master controls 30, for executing the MCU kernels The 10 Flash operational order sequences sent, read the data information of flash storage 20.Pass through general interface data wire 50 Order transmission and the data transmission that host 90 and Flash master controls 30 are handled with interface control line 120, need not establish a variety of connect Mouth agreement, reduces development cost.
The multichannel NAND Flash controllers 100 further include:The order caching of the Flash master controls 30 is corresponded to respectively Device 60 and data buffer 70.
The command buffer 60, the Flash operational orders sequence sent for receiving the MCU kernels 10.
The data buffer 70, the data to be written letter for receiving the transmission of the host 90 when host 90 is written Breath reads the data information of flash storage 20 for receiving the Flash master controls 30 when host 90 is read.
It should be noted that the MCU kernels 10 are separately connected the command buffer 60 by MCU kernels control line 40 With data buffer 70, the input terminal of the command buffer 60 connects the MCU kernels 10, the command buffer 60 it is defeated Outlet connects the control signal of the Flash master controls 30, and the data input pin of the data buffer 70 connects host 90, institute The data output end for stating data buffer 70 connects the data input pin of the Flash master controls 30, the data buffer 70 Control signal connects MCU kernels 10, and the command buffer 60 and data buffer 70 can be to correspond to Flash master controls 30 respectively Multiple command buffers 60 and data buffer 70.
It is understood that static cache device, the data buffer 70 can be used can be used for the command buffer 60 The lower dynamic buffering device of cost.In the concrete realization, the command buffer 60 is located in the Flash master controls 30 and MCU Between core 10, the Flash operational order sequences that MCU kernels 10 can be sent to the Flash master controls 30 cache, the number According to buffer 70 between the host 90 and the Flash master controls 30, the data information that the host 90 is sent is put into It is cached in the data buffer 70, or the data information of the flash storage 20 of reading is cached, accelerate institute State the data information interaction between host 90 and the flash storage 20.
In the present embodiment, between the host 90 and the Flash master controls 30 and the MCU kernels 10 with it is described It is equipped with data buffer 70 and command buffer 60 between Flash master controls 30, passes through the data buffer 70 and order Buffer 60 carries out the caching of data and order, can be lost to avoid the data and order, can accelerate 90 He of host Information exchange between Flash master controls 30.
The data buffer 70, for when data to be written are written in host 90, receiving waiting for for the transmission of the host 90 Data are written, when host 90 reads data, obtain the data information that flash storage 20 is read in the Flash master controls 30.
The MCU kernels 10 are additionally operable to obtain the read write command of the transmission of the host 90, and the read write command are carried out The processing such as caching, queuing, merging.
It should be noted that the MCU kernels 10 cache the read write command of the host 90, are lined up and merged Deng processing, and operation flash memory conversion layer (Flash Translation Layer, FTL) algorithm, the order that host 90 is sent turn Flash operational order sequences are changed to, and the Flash operational orders sequence is sent in the command buffer 60 in each channel.
In the concrete realization, the command buffer 60 is used to cache the order of Flash master controls 30, and ensures MCU kernels The instruction sequence of 10 fillings will not be capped, and described instruction sequence includes mainly:Flash orders, address command and DMA2 numbers It is instructed according to transmission, the command buffer 60 can receive the configuration information that the MCU kernels 10 are sent and to Flash master controls 30 Generic configuration, such as random seed using rule, coding and error correcting code system setting, in the MCU kernels 10 only need Initially it is configured.
It should be noted that in the present embodiment, the one of which command format that the order memory 60 may be used As follows, the design of command format is very flexible, but meet Flash orders and DMA2 transmission instruction cache all existing for this feature together Within the scope of this patent.
The format of 30 command portion of Flash master controls, label CC+ orders number+piece choosing+order;
The format of address part, the addresses label AA+ number+address are sent to flash storage 20;
The format of data portion, label DD+ length+storage address+Flash master controls address;
The 0xFF of continuous 4 byte indicates that command queue terminates;
In the concrete realization, such as the command queue of the erasing operation of a SLC is:CC 3 0x0 0xDa 0x60 AA 3 0x42 0x00 0x00 CC 3 0x0 0xD0 0x70;
The command queue of write operation is:CC 3 0x0 0xDa 0x80 AA 5 0x00 0x24 0x00 0x00 0x00 0x20 DD 0x800 0x10000 0x00 CC 3 0x0 0x10 0x70;
The command queue of write operation is:CC 3 0x0 0xDa 0x00 AA 5 0x24 0x00 0x00 0x00 0x20 CC 0x2 0x30 0x70 DD 0x800 0x10000 0x00。
The command buffer 60, can also be enabled according to the choosing of the piece of flash storage in channel 20 (Chip Enable, CE) number divides equally space, it is only necessary to set CE number in channel, with 2CE, be introduced for the 2K of space.
CE0 orders 0~1K of space, CE1 orders space 1K~2K, by taking reading as an example, Flash master control fetching rules are CE0 lives Enable 3 0x0 0xDa 0x00, CE1 orders CC of CC, 3 0x0 0xDa 0x00, CE0 address AA, 5 0x24 0x00 0x00 5 0x24 0x00 0x00 0x00 0x20, CE0 order CC 0x2 0x30 0x70, CE1 lives of 0x00 0x20, CE1 address AA CC 0x2 0x30 0x70 are enabled, first ready flash storage 20 can first continue the transmission that fetching carries out data, ensure with this Fetching is parallel between CE in channel.
In the present embodiment, the command buffer 60 designs command format, to meet multichannel NAND The command process of Flash controllers 100.
The multichannel NAND Flash controllers 100 further include the first dma controller 80 and second controller 110.Institute The first dma controller 80 is stated, the transmission control instruction of the MCU kernels 10 is executed, according to the transmission control instruction by host 90 data information, which receives, is written the data buffer 70, or the data information of data buffer 70 is sent to the host 90。
Second dma controller, for executing the transmission control instruction in the command buffer 60, according to the biography Defeated control instruction will be in the digital independent of flash storage 20 to the data buffer 70 or by the data buffer 70 Data be written flash storage 20.
The Flash master controls 30 are additionally operable to the data information of data buffer 70 generating corresponding Error Correction of Coding and incite somebody to action Data information after coding is sent to the flash storage 20.
The Flash master controls 30 are additionally operable to obtain the data information of flash storage 20, be entangled to the data information of acquisition Code is misexplained, and the data information after the error correction decoding is sent to data buffer 70.
Technical solution provided in this embodiment can realize 90 He of host by DMA1 controllers 80 and DMA2 controllers 110 The high efficiency of transmission of 20 data of flash storage can also be equipped with Error Correction of Coding, to avoid counting in the Flash master controls 30 When according to loss of data occur in transmission process, the data of loss can be restored.
In addition, the embodiment of the present invention also proposes that a kind of movable storage device, the movable storage device include Flash storages Device and multichannel NAND Flash controllers as described above, the multichannel NANDFlash controllers connect the Flash and deposit Reservoir.
The structural schematic diagram of one embodiment of movable storage device as shown in Figure 2, the movable storage device 200 include Flash storage 20 and as described above multichannel NAND Flash controllers 100, the multichannel NAND Flash controllers 100 connect the flash storage 20.
It these are only the preferred embodiment of the present invention, be not intended to limit the scope of the invention, it is every to utilize this hair Equivalent structure or equivalent flow shift made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant skills Art field, is included within the scope of the present invention.

Claims (10)

1. a kind of multichannel NAND Flash controllers, which is characterized in that the multichannel NAND Flash controllers include MCU Kernel and the Flash master controls for corresponding to flash storage respectively;
The MCU kernels, the read write command for obtaining host transmission, Flash operational orders are converted to by the read write command The Flash operational orders sequence is sent to corresponding command buffer, and controls the first dma controller by sequence, completes master Data write-in between machine and data buffer and read operation;
The Flash master controls, the Flash operational order sequences for receiving the command buffer are operated according to the Flash Instruction sequence simultaneously controls the second dma controller, and second dma controller connects one to one with several command buffers Dma controller completes data write-in and read operation between data buffer and flash storage.
2. multichannel NAND Flash controllers as described in claim 1, which is characterized in that the MCU kernels are additionally operable to obtain The read write command is cached, is lined up and merging treatment by the read write command for taking the host to send.
3. multichannel NAND Flash controllers as described in claim 1, which is characterized in that the MCU kernels are additionally operable to obtain The read write command for taking the host to send, Flash operational order sequences are converted to according to preset algorithm by the read write command, Flash operational order sequences include Flash command sequences and the transmission control instruction to the second dma controller, and by the behaviour It is sent to command buffer corresponding with the Flash master controls as instruction sequence.
4. multichannel NAND Flash controllers as claimed any one in claims 1 to 3, which is characterized in that the Flash Master control is additionally operable to the data information of data buffer generating corresponding Error Correction of Coding and is sent to the data information after coding The flash storage.
5. multichannel NAND Flash controllers as claimed any one in claims 1 to 3, which is characterized in that the Flash Master control is additionally operable to receive the data information that the flash storage obtains, and to the acquisition data information error correction decoding, and Data information after error correction decoding is sent to data buffer.
6. multichannel NAND Flash controllers as claimed in claim 5, which is characterized in that the multichannel NAND Flash Controller further includes:The command buffer and data buffer of the Flash master controls are corresponded to respectively;
The command buffer, the Flash operational order sequences sent for receiving the MCU kernels;
The data buffer, the data information to be written sent when host is written for receiving the host, when host is read The data information of flash storage is read for receiving the Flash master controls.
7. multichannel NAND Flash controllers as claimed in claim 6, which is characterized in that the data buffer is used for When data to be written are written in host, the data to be written that the host is sent are received, when host reads data, described in acquisition The data information of flash storage is read in Flash master controls.
8. multichannel NAND Flash controllers as claimed in claim 7, which is characterized in that first dma controller, by The transmission control instruction that the MCU kernels are executed in MCU kernels is controlled, receiving the host according to the transmission control instruction sends out Data information is simultaneously written the data buffer or is sent to the data information of the data buffer by the data information that send The host;
Second dma controller, is controlled by Flash master controls, is additionally operable to execute the control of the transmission in the command buffer and refers to It enables, it will be in the digital independent of flash storage to the data buffer or by the number according to the transmission control instruction Flash storage is written according to the data of buffer.
9. such as multichannel NAND Flash controllers described in any item of the claim 1 to 8, the MCU kernels pass through default The control line of item number connects the host, and the Flash master controls connect the host by the data line of default number of branches.
10. a kind of movable storage device, the movable storage device includes Flash and such as any one of claim 1 to 9 institute Multichannel NAND Flash controllers are stated, the multichannel NAND Flash controllers connect the Flash.
CN201810364432.9A 2018-04-19 2018-04-19 Multichannel NAND Flash controllers and movable storage device Pending CN108536623A (en)

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Cited By (6)

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CN109582243A (en) * 2018-12-03 2019-04-05 深圳市得微电子有限责任公司 Storage extended method, device, readable storage medium storing program for executing and the system of master control memory
CN109597576A (en) * 2018-11-30 2019-04-09 深圳市得微电子有限责任公司 Improve method, apparatus, readable storage medium storing program for executing and the system of NCQ command response speed
CN110209352A (en) * 2019-05-14 2019-09-06 西安艾可萨科技有限公司 A kind of control method of memory, Memory Controller, electronic equipment and storage medium
CN110968520A (en) * 2018-09-30 2020-04-07 北京忆恒创源科技有限公司 Multi-stream storage device based on unified cache architecture
WO2020087401A1 (en) * 2018-10-31 2020-05-07 华北电力大学扬中智能电气研究中心 Program writing device, system and method
CN117349203A (en) * 2023-10-23 2024-01-05 哈尔滨商业大学 Control data processing method and device

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