CN108445818A - A kind of data interaction intelligent terminal system and communication means - Google Patents

Abstract

The present invention relates to a kind of data interaction intelligent terminal system and communication means, host terminal, it includes key control unit, DIDO isolation cards circuit, AI isolation cards circuit, AO isolation cards circuit, association's processing unit interface circuit, serial ports isolation card circuit, integrated communication card circuit, human-computer interaction circuit, PWM counter isolation boards circuit, I/O expansion card circuit and Power Management Unit；Terminal system includes data interaction smart host terminal, data/address bus, the 1st slave terminal to N slave terminals；Communication means is the communication carried out from module using flames of war relay primary module and flames of war relay；The present invention has flexibly can assembled characteristic；The present invention have efficient, powerful secondary development characteristic and efficiently, easily slave extended attribute；So that host is detached from such a way that communication bus selects slave, original two-way response formula communication is become into relay answer-mode, improves real-time communication；Anti-interference ability of the present invention and stability are stronger, slave plug and play, realize tandem type infinite expanding.

Description

A data interaction intelligent terminal system and communication method

technical field

The invention relates to a data interaction intelligent terminal system and a communication method, belonging to the technical field of automatic control.

Background technique

In the industry, it is often necessary to collect the signals of some equipment or to automatically control some equipment, and the controllers and signals used in industrial equipment are various, which requires a controller or medium that can be connected to a variety of equipment. The type of signal connected It needs to cover DI (digital input), DO (digital output), AI (analog input), AO (analog output) and various serial communication data signals (such as 485 communication, CAN communication, Ethernet, etc.). The existing processing methods are generally as follows: 1. Use PLC. Although PLC is easy to use and has high reliability, its cost is high, and its system structure is closed. Various PLC manufacturers are also contending with each other, their hardware systems are not compatible with each other, and their programming languages and instruction systems are also different. After purchasing PLC products, you must choose the corresponding control procedures and learn a specific programming language. This undoubtedly prolongs the development cycle, especially in places with frequent personnel turnover; 2. Purchase some general-purpose modules and conduct secondary research and development. Although there are many kinds of signals in the control site, different control sites have different emphases, which makes it difficult for one control medium to be applied to various communication occasions, and the developers of the control medium often need to purchase different signals for different industrial sites. Modules are used to develop different control devices; the above two methods will cause waste of human resources and material resources to a certain extent. Moreover, although electronic products are convenient to use, their potential harm to the environment is great, and the recovery rate is low and low. In today's increasingly serious environmental problems, it is not conducive to the development of ecological civilization.

Contents of the invention

Aiming at the above problems, the present invention draws on the idea of movable type printing, and proposes a data interactive intelligent terminal system and communication method, which realizes functional decomposition without affecting the needs of industrial sites, and each functional module is formed independently, and can be used in When assembled according to needs, the utilization rate of electronic products is greatly improved.

The technical scheme that the present invention adopts is as follows:

A data interaction intelligent host terminal, which includes a core control unit, a DIDO isolation card circuit, an AI isolation card circuit, an AO isolation card circuit, a co-processing unit interface circuit, a serial port isolation card circuit, an integrated communication card circuit, a human-computer interaction circuit, PWM counter isolation board circuit, IO expansion card circuit and power management unit; The core control unit is bidirectionally connected with the corresponding port of the serial port isolation card circuit, and the serial port isolation card circuit is bidirectionally connected with the serial port signal port to be tested; The core control unit is bidirectionally connected with the corresponding port of the integrated communication card circuit, and the integrated communication card circuit is bidirectionally connected with the serial digital signal port; the core control unit is bidirectionally connected with the corresponding port of the IO expansion card circuit, The IO expansion card circuit is bidirectionally connected to the multifunctional data interactive intelligent slave terminal port; the core control unit is bidirectionally connected to the corresponding port of the co-processing unit interface circuit, and the first input terminal of the co-processing unit interface circuit connected to the intrusion detection and interrupt input signal port, the first output terminal of the co-processing unit interface circuit is connected to the corresponding input terminal of the human-computer interaction circuit, and the second output terminal of the co-processing unit interface circuit is connected to the PWM counter isolation board The corresponding input terminal of the circuit; the human-computer interaction circuit is bidirectionally connected with the corresponding port of the core control unit; the core control unit is bidirectionally connected with the corresponding port of the PWM counter isolation board circuit, and the pulse signal port to be tested is connected with the corresponding port of the PWM counter isolation board circuit. The corresponding port of the PWM counter isolation board circuit is bidirectionally connected; the output terminal of the core control unit is connected to the corresponding port input terminal of the AO isolation card circuit, and the output terminal of the AO isolation card circuit is connected to the analog control signal port; The input terminal of the AI isolation card circuit receives the measured analog signal port, and the output terminal of the AI isolation card circuit is connected to the corresponding input terminal of the core control unit; the DIDO isolation card circuit is bidirectional with the corresponding port of the core control unit connection, the DIDO isolation card circuit is bidirectionally connected to the corresponding port of the switch signal port; the output end of the power management unit is respectively connected to the core control unit, DIDO isolation card circuit, AI isolation card circuit, AO isolation card circuit, cooperating The processing unit interface circuit, serial port isolation card circuit, integrated communication card circuit, man-machine interaction circuit, PWM counter isolation board circuit, corresponding power ports of the IO expansion card circuit, and the input terminal of the power management unit are connected to an external power supply.

The data interaction intelligent host terminal also includes a main board and first to tenth circuit boards; the interface circuit of the co-processing unit is arranged on the main board; the core control unit is arranged on the first circuit board; the DIDO The isolation card circuit is set on the second circuit board; the AI isolation card circuit is set on the third circuit board; the AO isolation card circuit is set on the fourth circuit board; the serial port isolation card circuit is set on the fifth circuit board; the integrated communication card The circuit is set on the sixth circuit board; the human-computer interaction circuit is set on the seventh circuit board; the PWM counter isolation board circuit is set on the eighth circuit board; the IO expansion card circuit is set on the ninth circuit board; the power management unit is set On the tenth circuit board; the first to tenth circuit boards are connected to the main board in a plug-in manner.

An assembled data interactive intelligent terminal system, which includes a data interactive intelligent host terminal, a data bus, the first slave terminal to the Nth slave terminal, wherein N is an integer greater than 1; the first slave terminal to the Nth slave terminal The structure of the N slave terminals is the same, and the expansion form of the first slave terminal to the N slave terminal is a cascade type; the data interaction intelligent host terminal passes through the first slave terminal, the second slave terminal, ..., the N-1th slave terminal is connected to the Nth slave terminal; the data interaction intelligent master terminal, the first slave terminal to the Nth slave terminal are respectively connected to the data bus.

The method of using the assembled data interactive intelligent terminal system for communication, which uses the communication between the beacon relay master module and the beacon relay slave module, the specific steps are as follows:

(1) Initialize the core processing unit so that the pin of the selection signal input terminal FH of the beacon relay main module is at a low level, and the pin of the clock signal input terminal CLK of the beacon relay main module is at a high level;

(2) The embedded chip 1U1 sends a selection signal to the pin of the selection signal input terminal FH of the beacon relay main module, that is, sends a high level;

(3) The embedded chip 1U1 sends a clock signal of one cycle to the pin of the clock signal input terminal CLK of the beacon relay main module, that is, high level-low level-high level;

(4) The embedded chip 1U1 sends a clear signal to the pin of the selection signal input terminal FH of the beacon relay main module, that is, low level, and clears the slave address i;

(5) The embedded chip 1U1 sends a clock signal of one cycle to the pin of the clock signal input terminal CLK of the beacon relay master module, and increments the slave address i by 1;

(6) The embedded chip 1U1 detects whether the slave address i is greater than the limit number m of the slave, if yes, then executes step (7), otherwise executes step (8);

(7) When the beacon relay slave module is abnormal, output an abnormal notification;

(8) The embedded chip 1U1 judges whether the termination signal is received, and the pin of the feedback signal output terminal FHFK of the beacon relay main module sends the selection signal to a low level. If not received, execute step (9), otherwise execute step (10);

(9) The embedded chip 1U1 outputs the read and write data notification, and then jumps to step (5);

(10) The embedded chip 1U1 judges whether the slave address i exceeds the number n of data interaction intelligent slave terminals detected by the beacon relay master module, if yes, jump to step (2), otherwise execute step (11) step;

(11) Embedded chip 1U1 outputs the notification that the slave terminal goes online and offline;

(12) Reset the number n of data interaction intelligent slave terminals to i-1, and jump to step (2);

In the above steps, i is the slave address; n is the number of slave terminals; m is the limit number of slave terminals; wherein, the value range of i is 1~100, the value range of n is 1~100, and the value of m is The value range is 1~100.

The beneficial effects of the present invention are as follows: the present invention has flexible assembly characteristics, can replace PLC work, and it has highly flexible secondary development performance, AI, AO, DI, DO, serial communication interface to the core control unit , providing a flexible user expansion module interface, users can design isolation circuits or other functional circuits according to actual needs, which makes the entire architecture as open source systems, which can be easily improved; also like movable type printing, no need to Due to partial improvement, the entire set of circuit boards is re-produced; the present invention has high-efficiency and powerful secondary development characteristics, and the embedded system of .NET Micro Framework enables the application of object-oriented design ideas to hardware development, enabling software Developers quickly enter from the PC development end of C#.Net/VB.NET, and use the high productivity of Visual Studio to develop hardware systems without the need for professional hardware development engineers, thereby reducing labor costs for secondary development enterprises; the present invention With efficient and convenient slave expansion features, the data interaction host terminal and the data interaction expansion slave terminal integrate a unique beacon relay module, which uses a unique signal transmission method (here named: beacon relay method), so that the host is separated from the through communication The bus selects the slave mode. After the slave machine detects the relay signal, it can automatically connect to the communication bus to send data. In this way, the original two-way response communication is changed into a relay answer mode. The slave machine automatically answers without the host shouting. It improves the real-time performance of communication; and the slave terminal it serves does not need a programmable MCU. Compared with the MCU series, it has stronger anti-interference ability and stability; and it only needs to use the power line, ground line, etc. 4 lines, you can make the slave machine plug and play, realize the theoretical cascading infinite expansion; the invention is applicable to steel, petroleum, chemical industry, electric power, building materials, machinery manufacturing, automobile, textile, transportation It can be used in all walks of life, such as environmental protection, etc., and can be used in all automatic control fields that require switch logic control, process control, data processing, and communication networking.

Description of drawings

Fig. 1 is the functional block diagram of the data interaction intelligent host terminal of the present invention;

Fig. 2 is the circuit schematic diagram of the power management unit of the present invention;

Fig. 3 is the circuit principle diagram of core control unit of the present invention;

Fig. 4 is the circuit principle diagram of IO expansion bus communication circuit of the present invention;

Fig. 5 is the circuit schematic diagram of the beacon relay main module circuit of the present invention;

Fig. 6 is the circuit schematic diagram of the first serial port isolation card circuit of the present invention;

7 is a schematic circuit diagram of the first AI isolation circuit of the present invention;

Fig. 8 is the circuit schematic diagram of AO isolation card circuit of the present invention;

Fig. 9 is a schematic circuit diagram of the parallel-to-serial conversion input circuit of the present invention;

Fig. 10 is the circuit schematic diagram of the serial-to-parallel conversion output circuit of the present invention;

11 is a circuit schematic diagram of the first DO drive circuit of the present invention;

12 is a schematic circuit diagram of the first DO isolation circuit of the present invention;

13 is a schematic circuit diagram of the first DI isolation circuit of the present invention;

FIG. 14 is a schematic circuit diagram of the DIDO isolation circuit of the present invention;

Fig. 15 is the circuit schematic diagram of the PWM counter isolation board circuit of the present invention;

Fig. 16 is a schematic circuit diagram of the first human-computer interaction circuit of the present invention;

Fig. 17 is the circuit schematic diagram of the second human-computer interaction circuit of the present invention

Fig. 18 is the circuit schematic diagram of the serial port circuit of the present invention;

Fig. 19 is a schematic circuit diagram of the CAN bus circuit of the present invention;

Fig. 20 is a functional block diagram of the assembled data interaction intelligent terminal system of the present invention;

Fig. 21 is a functional block diagram of the first slave terminal of the present invention;

Fig. 22 is a schematic circuit diagram of the beacon relay slave module circuit of the present invention;

Fig. 23 is a circuit diagram of the bus controller of the present invention.

Detailed ways

From the embodiment shown in Figure 1-23, it can be seen that it involves a data interaction intelligent host terminal, including a core control unit, a DIDO isolation card circuit, an AI isolation card circuit, an AO isolation card circuit, a co-processing unit interface circuit, and a serial port isolation card circuit, integrated communication card circuit, human-computer interaction circuit, PWM counter isolation board circuit, IO expansion card circuit and power management unit; the core control unit is bidirectionally connected with the corresponding port of the serial port isolation card circuit, and the serial port isolation The card circuit is bidirectionally connected with the serial port signal port to be tested; the core control unit is bidirectionally connected with the corresponding port of the integrated communication card circuit, and the integrated communication card circuit is bidirectionally connected with the serial digital signal port; the core control unit Two-way connection with the corresponding port of the IO expansion card circuit, the two-way connection between the IO expansion card circuit and the multifunctional data interaction intelligent slave terminal port; the two-way connection between the core control unit and the corresponding port of the co-processing unit interface circuit The first input terminal of the co-processing unit interface circuit is connected to the intrusion detection and interrupt input signal port, the first output terminal of the co-processing unit interface circuit is connected to the corresponding input terminal of the human-computer interaction circuit, and the co-processing unit interface The second output terminal of the circuit is connected to the corresponding input terminal of the PWM counter isolation board circuit; the human-computer interaction circuit is bidirectionally connected to the corresponding port of the core control unit; the core control unit is connected to the PWM counter isolation board circuit The corresponding port of the corresponding port is bidirectionally connected, and the pulse signal port to be tested is bidirectionally connected with the corresponding port of the PWM counter isolation board circuit; the output terminal of the core control unit is connected to the corresponding port input terminal of the AO isolation card circuit, and the The output terminal of the AO isolation card circuit is connected to the analog control signal port; the input terminal of the AI isolation card circuit receives the measured analog signal port, and the output terminal of the AI isolation card circuit is connected to the corresponding input terminal of the core control unit; the DIDO The isolation card circuit is bidirectionally connected to the corresponding port of the core control unit, and the DIDO isolation card circuit is bidirectionally connected to the corresponding port of the switch signal port; the output ends of the power management unit are respectively connected to the core control unit, the DIDO isolation card circuit, AI isolation card circuit, AO isolation card circuit, co-processing unit interface circuit, serial port isolation card circuit, integrated communication card circuit, human-computer interaction circuit, PWM counter isolation board circuit, corresponding power port of IO expansion card circuit, power management The input terminal of the unit is connected to an external power supply.

The data interaction intelligent host terminal also includes a main board and first to tenth circuit boards; the co-processing unit interface circuit is arranged on the main board; the core control unit is arranged on the first circuit board; the DIDO isolation card circuit It is set on the second circuit board; the AI isolation card circuit is set on the third circuit board; the AO isolation card circuit is set on the fourth circuit board; the serial port isolation card circuit is set on the fifth circuit board; the integrated communication card circuit is set on the The sixth circuit board; the human-computer interaction circuit is set on the seventh circuit board; the PWM counter isolation board circuit is set on the eighth circuit board; the IO expansion card circuit is set on the ninth circuit board; the power management unit is set on the tenth circuit board On a circuit board; the first to tenth circuit boards are connected to the main board in a plug-in manner.

The power management unit is composed of chip U1, chip U5, chip U8, diode D101, inductor L101, capacitor C101-capacitor C105, resistor R101-resistor R104; the model of the chip U1 is MP2403, and the model of the chip U5 is APL117- 3.3, the model of the chip U8 is DC1212, and the model of the diode D101 is SS14;

The input pin 2 of the chip U1 is connected to the external power supply WB; the output pin 3 of the chip U1 is connected to one end of the inductor L101, and the other end of the inductor L101 is the output terminal +5V; the capacitor C101 is connected to the input pin 2 of the chip U1 Between the ground and the ground, the diode D101 is connected between the output pin 3 of the chip U1 and the ground, the capacitor C102 is connected between the 1 pin and the 3 pin of the chip U1, the 4 pin of the chip U1 is grounded, and the 5 pin of the chip U1 is connected by a resistor R102 is connected to the output terminal +5V, resistor R101 is connected between pin 5 of chip U1 and ground, capacitor C104 is connected in series with resistor R103 between pin 6 of chip U1 and ground, and capacitor C105 is connected to output terminal + Between 5V and ground, resistor R104 is connected between pin 7 and pin 2 of chip U1, and capacitor C103 is connected between pin 8 of chip U1 and ground;

The input terminal Vin of the chip U5 is connected to the output terminal +5V, the output terminal Vout of the chip U5 is the output terminal +3.3V, and the ground terminal of the chip U5 is grounded;

The input pin 2 of the chip U8 is connected to the external power supply WB, the 1 pin and the 3 pin of the chip U8 are grounded, and the 4 pin of the chip U8 is the output terminal +12V;

The core control unit includes an embedded chip 1U1 and its peripheral components switch 1S2, crystal oscillator 1Y101-1Y102, resistors 1R101-1R103, capacitors 1C101-1C107, data latches 1U2-1U3 and inverter chip 1U8; The type chip 1U1 is an embedded chip of the type STM32F103ZET6 implanted with the .Net Micro Framwork microframe, and the reset circuit composed of the switch 1S2, the resistor 1R103 and the capacitor 1C105 is connected between pin 25 of the embedded chip 1U1 and the ground. The first crystal oscillator circuit composed of the crystal oscillator 1Y102, resistor 1R102 and capacitor 1C103-1C104 is connected between pin 23 and pin 24 of the embedded chip 1U1, and the second crystal oscillator circuit composed of the crystal oscillator 1Y101, resistor 1R101 and capacitor 1C101-1C102 The circuit is connected between pins 8 and 9 of the embedded chip 1U1; the model of the data latch 1U2-1U3 is 74HC573, and the input pins 2-9 of the data latch 1U2 are respectively connected to the embedded 86-85 pins, 114-115 pins, 58-60 pins, 63 pins of the chip 1U1, 10 pins of the data latch 1U2 are grounded, and 20 pins of the data latch 1U2 are connected to the output terminal +3.3 V; the input pins 2-9 pins of the data latch 1U3 are respectively connected to the 64-68 pins and 77-79 pins of the embedded chip 1U1, and the 10 pins of the data latch 1U3 are grounded, and the data lock Pin 20 of the memory 1U3 is connected to the output terminal +3.3V; the model of the inverter chip 1U8 is 74LVC2G04, and pin 1 of the inverter chip 1U8 is connected to pin 137 of the embedded chip 1U1. Pin 3 of the inverter chip 1U8 is connected to pin 110 of the embedded chip 1U1, and pin 6 of the inverter chip 1U8 is connected to pin 11 of the data latch 1U2 and pin 11 of the data latch 1U3, inverting Pin 2 of the inverter chip 1U8 is grounded, and pin 5 of the inverter chip 1U8 is connected to the output terminal +3.3V;

The core control unit also includes a chip 1U4, a chip 1U5, and a chip 1U7;

The model of the chip 1U4 is an externally expanded SRAM chip SRAM-IS62WV51216BLL, and the 7-pin-10 pin, 13-pin-16 pin, 29-pin-32 pin, and 35-pin-38 pin of the chip 1U4 are respectively connected to the embedded chip 86-85 pins, 114-115 pins, 58-60 pins, 63-68 pins, 77-79 pins of 1U1; 5-1 pins, 44-42 pins, 27 pins of the chip 1U4 Pin-24 pins, 22 pins-19 pins are respectively connected to the output pins 19-12 pins of the data latch 1U2, and the output pins 19-12 pins of the data latch 1U3; the 18 pins, Pins 23 and 28 are respectively connected to pins 80-82 of the embedded chip 1U1; pins 6, 17, 39-41 of the chip 1U4 are respectively connected to pins 123 and 119 of the embedded chip 1U1 , 41 pins-42 pins, 118 pins; the 11 pins and 33 pins of the power supply end of the chip 1U4 are connected to the output terminal +3.3V, the capacitor 1C401 is connected between the 11 pins of the chip 1U4 and the ground, and the capacitor 1C402 is connected to the chip 1U4 Between pin 33 and ground, resistor 1R401 is connected between pin 6 of chip 1U4 and the output terminal +3.3V;

The model of the chip 1U5 is the external expansion FLASH chip MX29LV320, and the 29 pins, 31 pins, 33 pins, 35 pins, 38 pins, 40 pins, 42 pins, 44 pins, 30 pins, 32 pins, and 34 pins of the chip 1U5 , 36 pins, 39 pins, 41 pins, 43 pins, and 45 pins are respectively connected to 86 pins-85 pins, 114 pins-115 pins, 58 pins-60 pins, 63 pins-68 pins, and 77 pins of the embedded chip 1U1 -79 pins; 25 pins-18 pins and 8 pins-1 pins of the chip 1U5 are respectively connected to the output pins 19-12 pins of the data latch 1U2, and the output pins 19-12 pins of the data latch 1U3 Pins; 48 pins, 17 pins-16 pins, 9 pins-10 pins of the chip 1U5 are respectively connected to 80 pins-82 pins, 2 pins-3 pins of the embedded chip 1U1; 11 pins, 2 pins-3 pins of the chip 1U5 12 pins, 15 pins, 28 pins, and 26 pins are respectively connected to 119 pins, 25 pins, 122 pins, 118 pins, and 125 pins of the embedded chip 1U1; 14 pins of the chip 1U5 are connected to the output terminal through a resistor 1R502 +3.3V, the 15 pins of the chip 1U5 are connected to the output terminal +3.3V through the resistor 1R501, the 37 pins of the chip 1U5 are connected to the output terminal +3.3V, and the filter capacitor 1C501 is connected to the 37 pins of the chip 1U5 and Between the ground;

The chip 1U7 is an external expansion memory MT29F1G08, and the 29 pins-32 pins, 41 pins-44 pins, 26 pins-28 pins, 33 pins, 40 pins, 45 pins-47 pins of the chip 1U7 are respectively connected to the embedded 86-pin-85 pin, 114-pin-115 pin, 58-pin-60 pin, 63-pin-68 pin, 77-pin-79 pin of chip 1U1; 7-pin, 8-pin, 9-pin, 18-pin of chip 1U7 respectively Connect the 122 pins, 118 pins, 124 pins, and 119 pins of the embedded chip 1U1; the 16 pins-17 pins of the chip 1U7 are respectively connected to the 81 pins-80 pins of the embedded chip 1U1; Pin 19 is connected to pin 14 of the chip 1U5; pins 12, 34, 37, and 39 of the chip 1U7 are all connected to the output terminal +3.3V, and the capacitor 1C701 is connected between pin 12 of the chip 1U7 and the ground .

The IO expansion card circuit includes an IO expansion bus communication circuit and a beacon relay main module circuit;

The IO expansion card circuit includes an IO expansion bus communication circuit and a beacon relay main module circuit; the IO expansion bus communication circuit consists of optocoupler 2U5, NAND gate 2U6, optocoupler 2U1 to 2U4, chips 2U7 to 2U8, and resistance 2RP101 to 2RP104 and resistors 2R501 to 2R506; the model of the optocoupler 2U5 is TLP281-2, the model of the NAND gate 2U6 is 74HC00, the model of the optocoupler 2U1 to 2U4 is TLP281-4, and the model of the chip 2U7 to 2U8 is 74HC245 ;

The beacon relay main module circuit consists of chip 12U4, amplifier 12U3, optocoupler 12U1, chip 12U2, chip 12U5, constant current source 12U6, triode 12Q01-transistor 12Q03, potentiometer 12RJ01, resistor 12R11-resistance 12R15, resistor 12R31-resistance 12R35 , resistor 12R22-resistor 12R27 and capacitor 12C31-capacitor 12C33; the model of the chip 12U4 is 74HC74, the model of the amplifier 12U3 is LM358, the model of the optocoupler 12U1 is TLP281-4, the model of the chip 12U2 is LM393, and the model of the chip 12U5 The model is CN5710, and the model of the constant current source 12U6 is E-102T;

The serial port isolation card circuit includes first to fourth serial port isolation card circuits; the first to fourth serial port isolation card circuits have the same structure; wherein the first serial port isolation card circuit is composed of chip 10U1 to chip 10U7, digital transistor 10Q3 to digital Transistor 10Q5, diode 10D1, resistors 10R51 to 10R59, and capacitors 10C11 to 10C21 are composed; the model of the chip 10U1 is MAX232, the model of the chip 10U2 is MAX485, the model of the chip 10U3 is SN75179B, and the model of the chip 10U4 is XC6401. The model of 10U5 is TLP281-2, the model of chip 10U6 is ADUM1201ARZ, and the model of chip 10U7 is DC-DC05; the transistor 10Q3 and transistor 10Q4 are PNP digital transistors, and the transistor 10Q5 is an NPN digital transistor; diode 10D1 is a common cathode type diode; the second serial port isolation card circuit consists of chip 2-10U1 to chip 2-10U7, digital transistor 2-10Q3 to digital transistor 2-10Q5, diode 2-10D1, resistor 2-10R51 to resistor 2-10R59 and Composed of capacitor 2-10C11 to capacitor 2-10C21; the third serial port isolation card circuit consists of chip 3-10U1 to chip 3-10U7, digital transistor 3-10Q3 to digital transistor 3-10Q5, diode 3-10D1, resistor 3 -10R51 to resistor 3-10R59 and capacitor 3-10C11 to capacitor 3-10C21; the fourth serial port isolation card circuit consists of chip 4-10U1 to chip 4-10U7, digital triode 4-10Q3 to digital triode 4-10Q5 , diode 4-10D1, resistor 4-10R51 to resistor 4-10R59 and capacitor 4-10C11 to capacitor 4-10C21;

The AI isolation card circuit includes a first AI isolation circuit and a second AI isolation circuit; the first AI isolation circuit is composed of amplifier 4U1, amplifier 4U2, resistance 4R11-4R18, resistance 4R21-resistance 4R28, resistance 4R31-resistance 4R38, Composed of capacitors 4C11-4C12 and exclusion resistors 4RP511-4RP512; the models of the amplifier 4U1 and amplifier 4U2 are both LM324;

The AO isolation card circuit is composed of an amplifier 5U1, transistors 5Q1-5Q2, resistors 5R1-5R12 and capacitors 5C1-5C2; the model of the amplifier 5U1 is LM324;

The co-processing unit circuit is composed of a parallel-to-serial conversion input circuit and a serial-to-parallel conversion output circuit; the parallel-to-serial conversion input circuit consists of chip 6U1, chip 6U5 to chip 6U7, chip 6UA to chip 6UB, triode 6Q701-6Q702, triode 6Q602 , resistors 6R701-6R708, resistors 6R601-6R603, capacitors 6C701-6C702, and capacitors 6C601-6C605; the model of the chip 6U1 is TLP281-2, the model of the chips 6U5 to 6U6 is 74HC165, and the model of the chip 6U7 is BL1551, the model of the chip 6UA is 74HC165, and the model of the chip 6UB is 74HC86;

The serial-to-parallel conversion output circuit is composed of chips 7U1 to 7U5, chips 7U8 to 7U9, capacitors 7C701 to 7C705, and capacitors 7C708 to 7C709; the models of chips 7U1 to 7U5 and chip 7U9 are 74HC594. The model of chip 7U8 is 74HC139;

The 2 pins and 4 pins of the optocoupler 2U5 of the IO expansion bus communication circuit are grounded, the 6 pins and 8 pins of the optocoupler 2U5 are connected to the output terminal +5V, and the 5 pins and 7 pins of the optocoupler 2U5 are respectively connected to the resistor 2R504 , resistance 2R503 is grounded; pins 1, 5, 10, 13-14 of the NAND gate 2U6 are connected to the output +5V, pins 3 and 12 of the NAND gate 2U6 are connected, and the NAND gate 2U6 The 6 pins of the NAND gate 2U6 are connected to the 9 pins, the 2 pins of the NAND gate 2U6 are connected to the 7 pins of the optocoupler 2U5, and the 4 pins of the NAND gate 2U6 are connected to the 5 pins of the optocoupler 2U5;

Optocouplers 2U1 to 2U2, chip 2U7, and exclusion 2RP101 to 2RP102 form a signal output circuit; one end of the exclusion 2RP101 to 2RP102 is connected to pins 93, 10-15, and 132 of the embedded chip 1U1. The other end of resistance 2RP101 to 2RP102 is sequentially connected to pin 1, pin 3, pin 5, and pin 7 of the optocoupler 2U1, pin 1, pin 3, pin 5, and pin 7 of the optocoupler 2U2; pin 2 of the optocoupler 2U1 pins, 4 pins, 6 pins, 8 pins, 2 pins, 4 pins, 6 pins, 8 pins of 2U2 are grounded; 16 pins, 14 pins, 12 pins, 10 pins of the optocoupler 2U1, 16 pins of 2U2, Pins 14, 12, and 10 are all connected to the output terminal +3.3V; pins 15, 13, 11, and 9 of the optocoupler 2U1, and pins 15, 13, 11, and 9 of 2U2 are in order Connect pins 2-9 of the chip 2U7; pins 1 and 20 of the chip 2U7 are connected to the output terminal +3.3V, and pin 19 of the chip 2U7 is connected to pin 6 of the NAND gate 2U6;

Optocouplers 2U3 to 2U4, chip 2U8, and exclusion 2RP103 to 2RP06 form a signal input circuit; one end of the exclusion 2RP103 to 2RP104 is sequentially connected to pins 18-11 of the chip 2U7, and the other end of the exclusion 2RP103 to 2RP104 is in turn Connect pins 1, 3, 5, and 7 of the optocoupler 2U3, pins 1, 3, 5, and 7 of the optocoupler 2U4; pins 2, 4, and 6 of the optocoupler 2U3 8 pins, 2 pins, 4 pins, 6 pins, and 8 pins of 2U4 are all grounded; 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 2U3, 16 pins, 14 pins, 12 pins, and 10 pins of 2U4 Both are connected to the output terminal +3.3V; the 15 pins, 13 pins, 11 pins, and 9 pins of the optocoupler 2U3, and the 15 pins, 13 pins, 11 pins, and 9 pins of the 2U4 are sequentially connected to the 2 pins-9 of the chip 2U8 pin; pin 1 and pin 20 of the chip 2U8 are all connected to the output terminal +3.3V, and pin 19 of the chip 2U8 is connected to pin 4 of the chip 7U9 of the serial-to-parallel conversion output circuit of the co-processing unit interface circuit; pin 18 of the chip 2U8 Pins-11 are sequentially connected to pins 93, 10-15, and 132 of the embedded chip 1U1, and pins 2-9 of the chip 2U8 are grounded through exclusion 2RP105 and 2RP106;

The 12 pins of the chip 12U4 are connected to the 49 pins of the embedded chip 1U1, the 11 pins of the chip 12U4 are connected to the 50 pins of the embedded chip 1U1, the 5 pins of the chip 12U4 are the feedback signal FHFK of the beacon relay main module circuit, and the 1 pins of the chip 12U4 are Pin, pin 4, pin 10, pin 13, and pin 14 are connected to the output terminal +3.3V, pin 2 of the chip 12U4 is grounded through a resistor 12R14, pin 3 of the chip 12U4 is connected to the collector of the triode 12Q03; the triode 12Q03 The collector is connected to the output terminal +3.3V through the resistor 12R34, the base is connected to the pin 7 of the amplifier 12U3 through the resistor 12R33, the emitter of the triode 12Q03 is grounded, and the capacitor 12C32 is connected between the base of the triode 12Q03 and the ground ; Pin 1 of the amplifier 12U3 is connected to pin 6 of the optocoupler 12U1, resistor 12R31 and resistor 12R32 are connected in series between the output terminal +3.3V and ground, pin 2 and pin 6 of the amplifier 12U3 are connected The node of resistor 12R31 and resistor 12R32, pin 7 of the amplifier 12U3 is connected to pin 7 of the optocoupler 12U1; pin 3 of the amplifier 12U3 is connected to pin 12 of the chip 12U4, pin 5 of the amplifier 12U3 is connected to pin 11 of the chip 12U4 ; Pin 3 of the optocoupler 12U1 is connected to pin 9 of the chip 12U4, pin 1 of the optocoupler 12U1 is connected to the collector of the triode 12Q02 through the potentiometer 12RJ01, and the resistor 12R25 and resistor 12R24 are connected in series to the 12U2 Between pin 7 and the ground, the base of the triode 12Q02 is connected to the node of the resistor 12R25 and the resistor 12R24, the emitter of the triode 12Q02 is grounded, pin 2 of the optocoupler 12U1 is grounded through the constant current source 12U6, pin 4 of the optocoupler 12U1 is connected to the optocoupler The 5 pins of the optocoupler 12U1 are connected, the 8 pins of the optocoupler 12U1 are grounded through the resistor 12R15, the 9 pins of the optocoupler 12U1 are grounded through the resistor 12R13, the 11 pins of the optocoupler 12U1 are grounded through the resistor 12R12, the 10 pins and 16 pins of the optocoupler 12U1 are grounded Connect to +5V, pin 15 of the optocoupler 12U1 is connected to pin 2 of the chip 12U4; pin 5 of the chip 12U2 is connected to pin 11 of the optocoupler 12U1, pin 7 of the chip 12U2 is connected to the output terminal + through a resistor 12R26 5V, pin 1 of the chip 12U2 is connected to the output terminal +5V through the resistor 12R23, pin 6 of the chip 12U2 is connected to pin 2, pin 3 of the chip 12U2 is connected to pin 9 of the optocoupler 12U1; pin 1 of the chip 12U5 The pin is connected to pin 1 of the chip 12U2, the pin 3 of the chip 12U5 is grounded through the resistor 12R27, the pin 5 of the chip 12U5 is connected to the collector of the triode 12Q02, and the pin 5 of the chip 12U5 is the clock output port FHCLK of the beacon relay main module circuit ; The base of the triode 12Q01 is connected to the 12 pins of the optocoupler 12U1, the resistor 12R21 and the resistor 12R22 are connected in series between the output terminal +5V and the ground, and the 2 pins of the chip 12U2 are connected to The node of resistor 12R21 and resistor 12R22, the collector of triode 12Q01 is the signal sending port FHn of the beacon relay main module circuit;

Pin 2 of the chip 10U7 of the first serial port isolation card circuit is connected to the output terminal +5V, pin 1 of the chip 10U7 of the first serial port isolation card circuit is grounded, and pin 3 of the chip 10U7 of the first serial port isolation card circuit is output In isolation, pin 4 of the chip 10U7 of the first serial port isolation card circuit is an output isolated power supply, pin 2 of the chip 10U4 is connected to pin 4 of the chip 10U7, pin 1 of the chip 10U4 is connected to the chip 10U7 via a resistor 10R59 The collector of digital transistor 10Q5 is connected to pin 1 of chip 10U4, the base of transistor 10Q5 is connected to pin 3 of chip 10U4, the emitter of transistor 10Q5 is connected to pin 3 of chip 10U7, and the capacitor 10C21 is connected to the collector of transistor 10Q5 Between pin 3 of chip 10U7; pin 6 of chip 10U4 is the first output terminal VCC1, pin 4 of chip 10U4 is the second output terminal VCC2, pin 5 of chip 10U4 is connected to pin 3 of chip 10U7, and pin 4 of chip 10U4 is connected to pin 3 of chip 10U4. Pin 6 is connected to the first anode of the diode 10D1, pin 4 of the chip 10U4 is connected to the second anode of the diode 10D1, the cathode of the diode 10D1 is the output terminal VCC0, and the capacitor 10C19 is connected to pin 6 of the chip 10U4 and pin 3 of the chip 10U7. Between pins, capacitor 10C20 is connected between pin 4 of chip 10U4 and pin 3 of chip 10U7;

Pin 2 of the chip 10U6 is connected to pin 101 of the embedded chip 1U1, pin 3 of the chip 10U6 is connected to pin 102 of the embedded chip 1U1, pin 1 of the chip 10U6 is connected to the output terminal +5V, and the resistor 10R57 is connected to Between pin 2 and pin 7 of chip 10U6, resistor 10R58 is connected between pin 3 and pin 6 of chip 10U6, pin 8 of chip 10U6 is connected to the output terminal VCC0, and capacitor 10C18 is connected between pin 1 and pin 10U6 of chip 10U6. Between the 3 pins of 10U7, the capacitor 10C17 is connected between the 8 pins of the chip 10U6 and the 3 pins of the chip 10U7; the emitter of the triode 10Q3 is connected to the output terminal VCC0, and the base of the triode 10Q3 is connected to the chip 10U5 8 pins, the collector of the triode 10Q3 is connected to the 3 pin of the chip 10U7 through the resistor 10R53, the emitter of the triode 10Q4 is connected to the output terminal VCC0, the base of the triode 10Q4 is connected to the 6 pin of the chip 10U5, and the collector of the triode 10Q4 The electrode is connected to pin 3 of chip 10U7 via resistor 10R54, the collector of triode 10Q4 is connected to pin 3 of chip 10U4; pin 1 of chip 10U5 is connected to pin 1 of 7U9 via resistor 10R55, and pin 3 of chip 10U5 is connected to pin 3 of chip 10U5 via resistor 10R56 Pin 15 of 7U1, the collector of triode 10Q3 is connected to pin 15 of 7U9 through resistor 10R51, the collector of triode 10Q4 is connected to pin 15 of 7U1 through resistor 10R52, and pins 2, 4, 5 and 7 of chip 10U5 are all connected to the chip Pin 3 of 10U7; pin 1 of the chip 10U2 is connected to pin 7 of the chip 10U6; pin 2 and pin 3 of the chip 10U2 are connected to the collector of the triode 10Q3; pin 4 of the chip 10U2 is connected to pin 6 of the chip 10U6 , pin 8 of the chip 10U2 is connected to the output terminal VCC2, and a capacitor 10C16 is connected between pin 8 of the chip 10U2 and pin 3 of the chip 10U7; pin 1 of the chip 10U3 is connected to the output terminal VCC2, and pin 2 of the chip 10U3 Connect pin 1 of chip 10U2, pin 3 of chip 10U3 connect pin 4 of chip 10U2, pin 7 of chip 10U3 connect pin 7 of chip 10U2, pin 8 of chip 10U3 connect pin 6 of chip 10U2; pin 11 of chip 10U1 Connect to pin 3 of chip 10U3, pin 12 of chip 10U1 to pin 2 of chip 10U3, pin 13 of chip 10U1 to pin 7 of chip 10U3, pin 14 of chip 10U1 to pin 8 of chip 10U3, capacitor 10C13 to pin 10U1 Between pin 1 and pin 3, capacitor 10C15 is connected between pin 4 and pin 5 of chip 10U1, pin 16 of chip 10U1 is connected to the output terminal VCC1, capacitor 10C11 is connected between pin 16 of chip 10U1 and pin 3 of chip 10U7 between pin 2 of chip 10U1 and pin 3 of chip 10U7, and capacitor 10C14 is connected between pin 6 of chip 10U1 and pin 3 of chip 10U7;

The 2 pins of the chip 2-10U6 of the second serial port isolation card circuit are connected to the 37 pins of the embedded chip 1U1, the 3 pins of the chip 2-10U6 are connected to the 36 pins of the embedded chip 1U1, and the 36 pins of the chip 2-10U5 are connected to the embedded chip 1U1. Pin 3 is connected to pin 2 of 7U1, pin 1 of chip 2-10U5 is connected to pin 1 of 7U9; pin 2 of chip 3-10U6 of the third serial port isolation card circuit is connected to pin 70 of embedded chip 1U1, Pin 3 of the chip 3-10U6 is connected to pin 69 of the embedded chip 1U1, pin 3 of the chip 3-10U5 is connected to pin 4 of the 7U1, pin 1 of the chip 3-10U5 is connected to pin 2 of the 7U9; Pin 2 of the chip 4-10U6 of the fourth serial port isolation card circuit is connected to pin 112 of the embedded chip 1U1, pin 3 of the chip 4-10U6 is connected to pin 111 of the embedded chip 1U1, and pin 3 of the chip 4-10U5 Connect pin 6 of 7U1, pin 1 of chip 4-10U5 connect pin 3 of 7U9;

The DIDO isolation card circuit includes a DIDO isolation circuit, a DI isolation circuit, a DO isolation circuit and a DO drive circuit;

The DO drive circuit includes eight drive circuits with the same structure, which are the first DO drive circuit to the eighth DO drive circuit; Composed of R3; the collector of the triode Q1 is connected to the external drive power WV through the resistor R3 and the resistor R2 in turn, the collector of the triode Q1 is the output pin O+, connected to the switch signal port, and the emitter of the triode Q1 is the output of the first DO drive circuit. Pin O-, the base of the triode Q1 is connected to the collector of the triode Q2; the emitter of the triode Q2 is connected to the external drive power WV through the resistor R2, and the base of the triode Q2 is the input pin OC+ of the first DO drive circuit; The diode D2 is connected between the external driving power supply WV and the output pin O+, and the light emitting diode DS1 is connected between the emitter of the triode Q2 and the input pin OC+;

The second DO drive circuit is composed of triodes 2-Q1 to 2-Q2, light emitting diodes 2-DS1, diodes 2-D2, and resistors 2-R2 to 2-R3; the collector of the triode 2-Q1 is the output pin O+, Connect the switch signal port, the emitter of the triode 2-Q1 is the output pin O- of the second DO drive circuit, the base of the triode 2-Q2 is the input pin OC+ of the second DO drive circuit; the third DO drive circuit consists of the triode 3 -Q1 to 3-Q2, light-emitting diode 3-DS1, diode 3-D2, resistors 3-R2 to 3-R3; the collector of the triode 3-Q1 is the output pin O+, connected to the switch signal port, and the triode 3-Q1 The emitter is the output pin O- of the third DO drive circuit, the base of the triode 3-Q2 is the input pin OC+ of the third DO drive circuit; -DS1, diode 4-D2, and resistors 4-R2 to 4-R3; the collector of the triode 4-Q1 is the output pin O+, connected to the switch signal port, and the emitter of the triode 4-Q1 is the output pin of the fourth DO drive circuit O-, the base of the triode 4-Q2 is the input pin OC+ of the fourth DO drive circuit; the fifth DO drive circuit consists of triodes 5-Q1 to 5-Q2, light emitting diode 5-DS1, diode 5-D2, resistor 5 -R2 to 5-R3; the collector of the triode 5-Q1 is the output pin O+, connected to the switch signal port, the emitter of the triode 5-Q1 is the output pin O- of the fifth DO drive circuit, and the base of the triode 5-Q2 is The input pin OC+ of the fifth DO drive circuit; the sixth DO drive circuit is composed of transistors 6-Q1 to 6-Q2, light emitting diodes 6-DS1, diodes 6-D2, and resistors 6-R2 to 6-R3; the transistor 6 The collector of -Q1 is the output pin O+, connected to the switch signal port, the emitter of the triode 6-Q1 is the output pin O- of the sixth DO drive circuit, and the base of the triode 6-Q2 is the input pin OC+ of the sixth DO drive circuit; The seventh DO drive circuit is composed of triodes 7-Q1 to 7-Q2, light-emitting diodes 7-DS1, diodes 7-D2, and resistors 7-R2 to 7-R3; the collector of the triode 7-Q1 is the output pin O+, Connect the switch signal port, the emitter of the triode 7-Q1 is the output pin O- of the seventh DO drive circuit, the base of the triode 7-Q2 is the input pin OC+ of the seventh DO drive circuit; the eighth DO drive circuit is composed of the transistor 8 -Q1 to 8-Q2, light-emitting diode 8-DS1, diode 8-D2, resistors 8-R2 to 8-R3; the collector of the triode 8-Q1 is the output pin O+, connected to the switch signal port, and the triode 8-Q1 The emitter is the output pin O- of the eighth DO drive circuit, and the base of the transistor 8-Q2 is the input pin OC+ of the eighth DO drive circuit;

The DO isolation circuit includes a first DO isolation circuit and a second DO isolation circuit; the structure of the second DO isolation circuit is the same as that of the first DO isolation circuit; , Light-emitting diodes 3DO1-3DO4; the 2 pins, 4 pins, 6 pins, and 8 pins of the optocoupler 3U1 are connected to the ground, and the 1 pins, 3 pins, 5 pins, and 7 pins of the optocoupler 3U1 are respectively connected to the light-emitting diodes 3DO1-3DO4 One end of the exclusion 3RP1, the other end of the exclusion 3RP1 is the input terminal 3MDKI0~3MDKI3 of the first DO isolation circuit, and the 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 3U1 are respectively connected to the first DO drive circuit to the fourth The input pin OC+ of the DO drive circuit, and the 15 pins, 13 pins, 11 pins, and 9 pins of the optocoupler 3U1 are respectively connected to the output pin O- of the first DO drive circuit to the fourth DO drive circuit;

The second DO isolation circuit is composed of optocoupler 2-3U1, exclusion 2-3RP1, and light-emitting diodes 2-3DO1 to 2-3DO4; pins 1, 3, 5, and 7 of optocoupler 2-3U1 are respectively The light-emitting diodes 2-3DO1 to 2-3DO4 are connected to one end of the resistance exclusion 2-3RP1, and the other end of the exclusion resistance 2-3RP1 is the input terminal 3MDKI0~3MDKI3 of the second DO isolation circuit. The 16 pins of the optocoupler 2-3U1, Pins 14, 12, and 10 are respectively connected to the input pin OC+ of the fifth DO drive circuit to the eighth DO drive circuit, and pins 15, 13, 11, and 9 of the optocoupler 2-3U1 are respectively connected to the fifth DO drive circuit. To the output pin O- of the eighth DO drive circuit;

The DI isolation circuit includes a first DI isolation circuit and a second DI isolation circuit; the second DI isolation circuit has the same structure as the first DI isolation circuit; -3RP4, light-emitting diode 3DI1-3DI4; the 2 pins, 4 pins, 6 pins, and 8 pins of the optocoupler 3U5 are connected to the common end of the switch signal, and the 1 pin, 3 pins, 5 pins, and 7 pins of the optocoupler 3U5 are respectively Connect the 4-way switch signal ports with 3RP4 and light-emitting diodes 3D11-3D14 through resistance exclusion, connect pins 10, 12, 14, and 16 of the optocoupler 3U5, and then connect the output terminal +3.3V, and connect pins 15 and 16 of the optocoupler 3U5. Pins 13, 11, and 9 are grounded through the exclusion 3RP3, and pins 15, 13, 11, and 9 of the optocoupler 3U5 are respectively the signal output terminals 3MDKO0~3MDKO3 of the first DI isolation circuit; the second DI The isolation circuit is composed of optocoupler 2-3U5, exclusion 2-3RP3 to 2-3RP4, light emitting diode 2-3DI1 to 2-3DI4; the 15 pins, 13 pins, 11 pins and 9 pins of the optocoupler 2-3U5, They are the signal output terminals 3MDKO0~3MDKO3 of the second DI isolation circuit;

The DIDO isolation circuit is composed of chips 3U2-3U3, digital transistor 3Q1, resistor 3R1, and capacitor 3C1-3C2. The 20 pins of the chips 3U2-3U3 are all connected to the output terminal +3.3V, and the 10 pins of the chips 3U2-3U3 are all grounded. , the 19 pins of the chip 3U2 are connected to the 11 pins of the chip 7U8, the 18 pins-11 pins of the chip 3U2 are connected to the 2 pins-9 pins of the chip 3U3, and the 18 pins-11 pins of the chip 3U2 are respectively connected to the 56-pins of the embedded chip 1U1 57 pins, 87-92 pins, pin 1 of the chip 3U2 is connected to pin 5 of the chip 7U9, pins 2-5 of the chip 3U2 are connected to the signal output terminal 3MDKO0~3MDKO3 of the first DI isolation circuit, pins 6-9 of the chip 3U2 Connect to the signal output terminal 3MDKO0~3MDKO3 of the second DI isolation circuit; pin 1 of the chip 3U3 is connected to pin 3 of the chip 7U5, pin 11 is connected to the collector of the digital transistor 3Q1, pins 19-16 of the chip 3U3 are connected to the first DO isolation circuit The input terminal 3MDKI0~3MDKI3 of the chip 3U3 is connected to the input terminal 3MDKI0~3MDKI3 of the second DO isolation circuit, the base of the digital triode 3Q1 is connected to the 1 pin of the chip 3U2, and the emitter of the digital triode 3Q1 is connected to the chip 3U2 The resistor 3R1 is connected between the 11th pin of the chip 3U3 and the ground, the capacitor 3C1 is connected between the 20th pin of the chip 3U2 and the ground, and the capacitor 3C2 is connected between the 20th pin of the chip 3U3 and the ground;

The models of the amplifier 4U1 and the amplifier 4U2 of the first AI isolation circuit are both LM324, the same-direction input terminal 3 of the amplifier 4U1 is an analog signal port to be measured, and the same-direction input terminal 3 of the amplifier 4U1 is grounded through a resistor 4R31 , pin 2 of the reverse input terminal of the amplifier 4U1 is grounded through a resistor 4R12, pin 1 of the output terminal of the amplifier 4U1 is connected to pin 2 of the reverse input terminal of the amplifier 4U1 through a feedback resistor 4R11; pin 5 of the same input terminal of the amplifier 4U1 is used for measurement The analog signal port of the amplifier 4U1, the 5 pins of the same input end of the amplifier 4U1 are grounded through the resistor 4R32, the 6 pins of the reverse input end of the amplifier 4U1 are grounded through the resistor 4R14, the 7 pins of the output end of the amplifier 4U1 are connected to the reverse direction of the amplifier U1 through the feedback resistor 4R13 The 6-pin input terminal; the 10-pin input terminal of the amplifier 4U1 receives the analog signal port for measurement, the 10-pin input terminal of the amplifier 4U1 is grounded through the resistor 4R33, and the 9-pin reverse input terminal of the amplifier 4U1 is grounded through the resistor 4R16 , the output terminal 8 pins of the amplifier 4U1 are connected to the reverse input terminal 9 pins of the amplifier 4U1 through the feedback resistor 4R15; Grounded through resistor 4R34, the reverse input terminal 13 of the amplifier 4U1 is grounded through the resistor 4R18, the output terminal 14 of the amplifier 4U1 is connected to the reverse input terminal 13 of the amplifier 4U1 through the resistor 4R17; the 4 pin of the amplifier 4U1 is connected to the The output terminal is +5V, and the capacitor 4C11 is connected between pin 4 of the amplifier 4U1 and the ground;

The 3 pins of the same input end of the amplifier 4U2 receive the analog signal port for measurement, the 3 pins of the same input end of the amplifier 4U2 are grounded through the resistor 4R35, the 2 pins of the reverse input end of the amplifier 4U2 are grounded through the resistor 4R22, and the output of the amplifier 4U2 Pin 1 of the terminal is connected to pin 2 of the reverse input terminal of the amplifier 4U2 through the feedback resistor 4R21; pin 5 of the same input terminal of the amplifier 4U2 receives the analog signal port for measurement, and pin 5 of the same input terminal of the amplifier 4U2 is grounded through the resistor 4R36. The 6 pins of the reverse input terminal of the amplifier 4U2 are grounded through the resistor 4R24, the 7 pins of the output terminal of the amplifier 4U2 are connected to the 6 pins of the reverse input terminal of the amplifier 4U2 through the feedback resistor 4R23; the 10 pins of the same input terminal of the amplifier 4U2 are used for measurement Analog signal port, the 10 pins of the same input end of the amplifier 4U2 are grounded through the resistor 4R37, the 9 pins of the reverse input end of the amplifier 4U2 are grounded through the resistor 4R26, the 8 pins of the output end of the amplifier 4U2 are connected to the reverse input of the amplifier 4U2 through the feedback resistor 4R25 Terminal 9 pins; the 12 pins of the same-directional input end of the amplifier 4U2 receive the analog signal port for measurement, the 12 pins of the same-directional input end of the amplifier 4U2 are grounded through the resistor 4R38, and the 13 pins of the reverse input end of the amplifier 4U2 are grounded through the resistor 4R28, The output terminal 14 of the amplifier 4U2 is connected to the reverse input terminal 13 of the amplifier 4U2 via the feedback resistor 4R27; the 4 pin of the amplifier 4U2 is connected to the output terminal +5V, and the capacitor 4C12 is connected to the 4 pin of the amplifier 4U2 and the ground between;

The output terminals 1 pins, 7 pins, 8 pins and 14 pins of the amplifier 4U1 are respectively connected to the 34 pins, 35 pins, 42 pins and 43 pins of the embedded chip 1U1 through the exclusion 4RP511; the output terminals of the amplifier 4U2 Pin 1, pin 7, pin 8, and pin 14 are respectively connected to pin 46, pin 47, pin 26, and pin 27 of the embedded chip 1U1 through the exclusion 4RP512;

The second AI isolation circuit has the same structure as the first AI isolation circuit, consisting of amplifier 2-4U1, amplifier 2-4U2, resistors 2-4R11 to 2-4R18, resistor 2-4R21 to resistor 2-4R28, resistor 2-4R31 to resistor 2-4R38, capacitor 2-4C11 to 2-4C12, and exclusion 2-4RP511 to 2-4RP512; the output pins 1, 7, 8, and 14 of the amplifier 2-4U1 are respectively subjected to exclusion 2-4RP511 is connected to the 28 pins, 29 pins, 44 pins, and 45 pins of the embedded chip 1U1; the 1 pins, 7 pins, 8 pins, and 14 pins of the output terminals of the amplifier 2-4U2 are respectively blocked by 2-4RP512 Connect the 18 pins, 19 pins, 20 pins, and 21 pins of the embedded chip 1U1; the 3 pins, 5 pins, 10 pins, and 12 pins of the same input terminals of the amplifiers 2-4U1 and 2-4U2 respectively receive the measured analog signals port;

The resistor 5R4 of the AO isolation card circuit is connected in series with the resistor 5R11 and then connected between the input terminal 5 of the amplifier 5U1 and the ground, and the resistor 5R1 and the resistor 5R12 are connected in series and connected to the input terminal 10 of the amplifier 5U1 and the ground, the node of the resistor 5R4 and the resistor 5R11 is connected to pin 41 of the embedded chip 1U1, and the node of the resistor 5R1 and resistor 5R12 is connected to the pin 40 of the embedded chip 1U1; the node of the amplifier 5U1 Pin 1 and pin 2 are connected to pin 5 of the amplifier 5U1 via resistor 5R2, pin 7 of the amplifier 5U1 is connected to the base of the triode 5Q2, pin 6 of the amplifier 5U1 is connected to the emitter of the triode 5Q2 via resistor 5R5, and resistor 5R7 Connected between pin 6 of the amplifier 5U1 and the ground, capacitor 5C1 is connected between pin 7 of the amplifier 5U1 and the ground; the collector of the triode 5Q2 is connected to the output terminal +12V, and its emitter is connected through the resistor 5R10 Pin 3 of the amplifier 5U1; pin 13 of the amplifier 5U1 is connected to pin 14 of the amplifier 5U1 and connected to pin 10 of the amplifier 5U1 through a resistor 5R3; pin 8 of the amplifier 5U1 is connected to the base of the triode 5Q6; pin 9 of the amplifier 5U1 is connected to the base of the transistor 5Q6 The resistor 5R6 is connected to the emitter of the triode 5Q1, the resistor 5R8 is connected between pin 9 of the amplifier 5U1 and the ground, and the capacitor 5C2 is connected between the pin 8 of the amplifier 5U1 and the ground; the collector of the triode 5Q1 is connected to the output terminal + 12V, its emitter is connected to pin 12 of amplifier 5U1 through resistor 5R9;

Pin 1 and pin 4 of the chip 6U1 of the parallel-to-serial conversion input circuit are respectively connected to intrusion detection and interrupt input signals through resistor 6R702 and resistor 6R701, and pin 6 and pin 8 of the chip 6U1 are connected to the input signal through resistor 6R703 and resistor 6R704 respectively. Connect the output terminal +3.3V, the 5 pin of the chip 6U1 is grounded through the resistor 6R708, the capacitor 6C701 is connected in parallel with the resistor 6R708, the 7 pin of the chip 6U1 is grounded through the resistor 6R707, the capacitor 6C702 is connected in parallel with the resistor 6R702, the triode The base of 6Q701 is connected to pin 5 of chip 6U1, the emitter of triode 6Q701 is grounded, the collector of triode 6Q701 is connected to the output terminal +3.3V through resistor 6R706, the base of triode 6Q702 is connected to pin 7 of chip 6U1, and the triode The emitter of 6Q702 is grounded, the collector of triode 6Q702 is connected to the output terminal +3.3V through resistor 6R705, and the collector of triode 6Q702 is connected to pin 7 of the embedded chip 1U1; the chip 6U5 to chip 6U6, chip 6UA Both pins 2 are connected to pin 133 of the embedded chip 1U1, the collector of the triode 6Q602 is connected to the output terminal +3.3V through a resistor 6R601, the base of the triode 6Q602 is connected to pin 6 of the chip 6U7 through a resistor 6R602, and the triode 6Q602 The emitter of the chip is grounded, the resistor 6R603 and the capacitor 6C601 are connected in parallel and then connected between the base of the triode 6Q602 and the ground; the chips 6U5 to 6U6, and pin 1 of the chip 6UA are all connected to the collector of the triode 6Q602, and pin 3 of the chip 6U6 Connect the collector of the triode 6Q701, the 14 pins of the chip 6U6 are connected to the 5 pins of the chip 12U4; the 4 pins of the chip 6U7 are connected to the 134 pins of the embedded chip 1U1, and the 1 pins of the chip 6UB are connected to the chip 3 pins of 6U6, 2 pins of the chip 6UB are connected to 4 pins of the chip 6U6, 4 pins and 5 pins of the chip 6UB are respectively connected to 13 pins and 12 pins of the chip 6U5, and 11 pins of the chip 6UB are connected to the Pin 54 of the embedded chip 1U1, pin 3 of the chip 6UB is connected to pin 13 of the chip 6UB, pin 6 of the chip 6UB is connected to pin 12 of the chip 6UB;

The 11 pins of the chip 7U1 to the chip 7U5 of the serial-to-parallel conversion output circuit are all connected to the 133 pins of the embedded chip 1U1; the 14 pins of the chip 7U1 are connected to the 135 pins of the embedded chip 1U1, and the 15 pins of the chip 7U1 The pins, 2 pins, 4 pins, and 6 pins are respectively connected to the 3 pins of the chip 10U6 of the first serial port isolation card circuit, the 3 pins of the chip 2-10U6 of the second serial port isolation card circuit, and the chip 3-10U6 of the third serial port isolation card circuit. Pin 3 of 10U6, pin 3 of chip 4-10U6 of the fourth serial port isolation card circuit;

The 14 pins of the chip 7U5 are connected to the 9 pins of the chip 7U2, the 14 pins of the chip 7U3 are connected to the 9 pins of the chip 7U5; the 14 pins of the chip 7U4 are connected to the 9 pins of the chip 7U3;

The 15 pins of the chip 7U8 are connected to the 15 pins of the chip 7U5, the 1-3 pins of the chip 7U8 are respectively connected to the 110 pins, 55 pins, and 126 pins of the embedded chip 1U1, and the 4 pins of the chip 7U8 are connected to the chips 7U1 to 7U5. 12 pins, 6 pins of chip 6U7;

Pins 6-7 of the chip 7U9 are connected to pins 14-13 of the chip 7U8, pins 11-12 and 14 of the chip 7U9 are connected to pins 75, 76, and 74 of the embedded chip 1U1, and the chip 7U9 15 pins, 1 pin - 3 pins of the chip 10U5 of the first serial port isolation card circuit, 1 pin of the chip 2-10U5 of the second serial port isolation card circuit, and 3-10U5 of the chip 3-10U5 of the third serial port isolation card circuit Pin 1, pin 1 of chip 4-10U5 of the fourth serial port isolation card circuit; pin 3 of chip 7U5 is connected to pin 1 of the optocoupler 2U5 through resistor 2R501, pin 4 of chip 7U9 is connected to pin 3 of optocoupler 2U5 through resistor 2R502 foot.

The PWM counter isolation board circuit consists of chips 8U4-8U7, optocouplers 8U2-8U3, transistors 8Q201-8Q204, transistors 8Q301-8Q308, exclusion 8RP101, exclusion 8RP201, exclusion 8RP202, light emitting diodes 8D301-8D304, light emitting diode 8D201 -8D204 and resistor 8R301-8R304; the model of the chip 8U4-8U7 is an analog electronic switch BL1551, the model of the optocoupler 8U3 is TLP521-4, and the model of the optocoupler 8U4 is TLP281-4; the model of the chip 8U4-8U7 The 4 pins of the input pins are respectively connected with the 96 pins, 97 pins, 100 pins, and 136 pins of the embedded chip 1U1; Pin-5 pins, the output pins 3 of the chip 8U4-8U7 are respectively connected to the input pins 1, 3, 5, and 7 of the optocoupler 8U3 through the exclusion 8RP101 and the light-emitting diode 8D301-8D304, and the optocoupler 8U3’s 2 feet, 4 feet, 6 feet, 8 feet grounding;

The 9-16 pins of the optocoupler 8U3 are connected to four pulse output circuits with the same structure; the first pulse output circuit is composed of transistor 8Q301, transistor 8Q305 and resistor 8R301; the 16 pins of the optocoupler 8U3 are connected to the pulse signal The corresponding port of the port, the 16-pin of the optocoupler 8U3 is connected to the collector of the transistor 8Q301, the emitter of the transistor 8Q301 is connected to one end of the resistor 8R301, the emitter of the transistor 8Q305 is connected to the 15-pin of the optocoupler 8U3, and the collector of the transistor 8Q305 is connected to the transistor 8Q301 The base of transistor 8Q305 is connected to the other end of resistor 8R301; the second pulse output circuit is composed of transistor 8Q302, transistor 8Q306 and resistor 8R302; the collector of transistor 8Q302 is connected to pin 14 of optocoupler 8U3, Pin 14 of optocoupler 8U3 is connected to the corresponding port of the pulse signal port, and the emitter of transistor 8Q306 is connected to pin 13 of optocoupler 8U3; the third pulse output circuit is composed of transistor 8Q303, transistor 8Q307 and resistor 8R303; the transistor 8Q303 The collector is connected to the 12 pins of the optocoupler 8U3, the 12 pins of the optocoupler 8U3 are connected to the corresponding port of the pulse signal port, the emitter of the transistor 8Q307 is connected to the 11 pins of the optocoupler 8U3; the fourth pulse output circuit is composed of transistors 8Q304, Composed of transistor 8Q308 and resistor 8R304; the collector of the transistor 8Q304 is connected to pin 10 of the optocoupler 8U3, pin 10 of the optocoupler 8U3 is connected to the corresponding port of the pulse signal port, and the emitter of the transistor 8Q308 is connected to pin 9 of the optocoupler 8U3;

The PWM counter isolation board circuit pulse input circuit composed of the optocoupler 8U2, digital transistors 8Q201-8Q204, exclusion 8RP201, exclusion 8RP202, and light-emitting diodes 8D201-8D204; the anodes of the light-emitting diodes 8D201-8D204 are respectively transistors 8Q301-8Q304 The emitters of the light-emitting diodes 8D201-8D204 are respectively connected to pins 1, 3, 5, and 7 of the optocoupler 8U2, and pins 2, 4, 6, and 8 of the optocoupler 8U2 are respectively connected to The resistance exclusion 8RP201 is connected to the 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 8U3, and the 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 8U2 are respectively connected to the bases of the transistors 8Q201-8Q204. The 15 pins, 13 pins, 11 pins and 9 pins of the coupling 8U2 are all grounded; the collectors of the transistors 8Q201-8Q204 are respectively grounded through the resistance 8RP202, and the collectors of the transistors 8Q201-8Q204 are respectively connected to the 1 pin of the chip 8U4, the chip 8U5 pin 1 of the chip 8U6, pin 1 of the chip 8U7, and the emitters of the transistors 8Q201-8Q204 are connected to the output terminal +3.3V;

The human-computer interaction circuit includes a first human-computer interaction circuit and a second human-computer interaction circuit;

The first human-computer interaction circuit is composed of resistors 9R1-9R8 and light-emitting diodes 9D1-9D8; the resistor 9R1 is connected in series with the light-emitting diode 9D1 and then connected to pin 3 of the chip 7U4 in the serial-to-parallel conversion output circuit and ground The resistor 9R2 is connected in series with the light emitting diode 9D2 and then connected between pin 2 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground; the resistor 9R3 is connected in series with the light emitting diode 9D3 and then connected to the Between pin 1 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R4 is connected in series with the light-emitting diode 9D4 and connected between pin 15 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; The resistor 9R5 is connected in series with the light emitting diode 9D5 and then connected between pin 5 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground; the resistor 9R6 is connected in series with the light-emitting diode 9D6 and then connected to the serial-parallel conversion output Between pin 4 of the chip 7U4 in the circuit and the ground; the resistor 9R7 is connected in series with the light-emitting diode 9D7 and connected between pin 7 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground; the resistor 9R8 and the ground The light-emitting diode 9D8 is connected in series between pin 6 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground;

The second human-computer interaction circuit is composed of resistors 9R11-9R18, switches 9S1-9S8 and capacitors 9C1-9C8; the resistor 9R11 is connected in series with the switch 9S1 and connected between the output terminal +3.3V and ground, and the The node of the resistor 9R11 and the switch 9S1 is connected to pin 11 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R12 is connected in series with the switch 9S2 between the output terminal +3.3V and ground, and the resistor 9R12 The node connected with the switch 9S2 is connected to pin 12 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R13 is connected in series with the switch 9S3 and then connected between the output terminal +3.3V and ground, and the resistor 9R13 is connected to the switch The node of 9S3 is connected to pin 13 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R14 is connected in series with the switch 9S4 and then connected between the output terminal +3.3V and ground, and the resistor 9R14 is connected to the switch 9S4 The node is connected to pin 14 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R15 is connected in series with the switch 9S5 between the output terminal +3.3V and ground, and the node of the resistor 9R15 is connected to the switch 9S5 Pin 3 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R16 is connected in series with the switch 9S6 between the output terminal +3.3V and ground, and the node of the resistor 9R16 and the switch 9S6 is connected to the Pin 4 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R17 is connected in series with the switch 9S7 between the output terminal +3.3V and ground, and the node of the resistor 9R17 and the switch 9S7 is connected to the parallel string Convert pin 5 of the chip 6UA in the input circuit; the resistor 9R18 is connected in series with the switch 9S8 between the output terminal +3.3V and ground, and the node of the resistor 9R18 and the switch 9S8 is connected to the parallel-serial conversion input The 6 pins of the chip 6UA in the circuit; the capacitors 9C1-9C8 are respectively connected in parallel with the switches 9S1-9S8;

The integrated communication card circuit includes a serial port circuit and a CAN bus circuit; the serial port circuit is made up of a serial port chip 11U11, resistors 11R1-11R2 and capacitors 11C1-11C5; the model of the serial port chip 11U11 is MAX232, and the serial port chip 11U11 The 11 pins and 12 pins of the embedded chip 1U1 are respectively connected to the 113 pins and 116 pins of the embedded chip 1U1, the 11 pins and 12 pins of the serial port chip 11U11 are respectively connected to the corresponding external serial port signals, and the resistor 11R1 is connected to the 10 pins and 12 pins of the serial port chip 11U11. Between pins, resistor 11R2 is connected between pin 9 and pin 11 of serial chip 11U11, capacitor 11C3 is connected between pin 4 and pin 5 of serial chip 11U11, capacitor 11C5 is connected between pin 1 and pin 3 of serial chip 11U11 In between, capacitor 11C1 is connected between pin 16 of serial port chip 11U11 and the ground, pin 16 of serial port chip 11U11 is connected to the output +5V, capacitor 11C2 is connected between pin 2 of serial chip 11U11 and ground, capacitor 11C4 is connected to Between pin 6 of serial port chip 11U11 and ground;

Described CAN bus circuit is made up of isolating chip 11U21 and capacitor hair 11C6-11C7; The model of described isolating chip 11U21 is ISO1050; 1 pin of described isolating chip 11U21 is connected to described output +5V, and its 2 pins are connected to described Pin 140 of the embedded chip 1U1, pin 3 of the isolation chip 11U21 are connected to pin 139 of the embedded chip 1U1, pins 4 and 5 of the isolation chip 11U21 are grounded, pins 6 and 7 of the isolation chip 11U21 are CAN control bus At the output end, pin 8 of the isolation chip 11U21 is connected to the output +5V, capacitor 11C6 is connected between pin 1 of the isolation chip 11U21 and the ground, and capacitor 11C7 is connected between pin 8 of the isolation chip 11U21 and the ground.

The present invention also relates to an assembled data interactive intelligent terminal system, which includes a data interactive intelligent host terminal, a data bus, the first slave terminal to the Nth slave terminal, wherein N is an integer greater than 1; the first slave The structure from the machine terminal to the Nth slave terminal is the same, and the expansion form of the first slave terminal to the Nth slave terminal is a cascading type; the data interaction intelligent host terminal passes through the first slave terminal, the second The slave terminals, ..., the N-1th slave terminal are connected to the Nth slave terminal; the data interaction intelligent host terminal, the first slave terminal to the Nth slave terminal are respectively connected to the data bus.

The data bus includes the first data bus DWKZ0 to the eighth data bus DWKZ7, the ninth data bus WKWRZ, the tenth data bus WKOEZ, the data bus power line and the data bus ground wire; the data bus power line is connected to the +5V power supply, and the data bus ground wire;

The first slave terminal includes a slave core control unit, a slave isolation card, a slave power management unit, a first bus controller and a first beacon relay slave module circuit;

The slave core control unit has the same structure as the core control unit of the data interaction intelligent host terminal; the slave power management unit has the same structure as the data interaction intelligent host terminal power management unit;

The slave isolation card, the first bus controller and the first Beacon relay slave module circuit are respectively connected to the corresponding ports of the slave core control unit;

The external power supply supplies power to the core control unit of the slave, the isolation card of the slave, the first bus controller and the first beacon relay slave module circuit through the slave power management unit;

The first bus controller is composed of a chip 13U7 and a resistor 13R1; the model of the chip 13U7 is 74HC245, and pin 1 of the chip 13U7 is connected to the ninth data bus WKWRZ of the data bus; pins 2-9 of the chip 13U7 are respectively Connect the 93 pins, 10 pins to 15 pins and 132 pins of the embedded chip 1U1; the 10 pins of the chip 13U7 are grounded; the 18 pins to the 11 pins of the chip 13U7 are respectively connected to the first data bus DWKZ0 to the eighth data bus of the data bus On line DWKZ7; pin 20 of chip 13U7 is connected to +5V power supply; the resistor 13R1 is connected between pin 19 and pin 20 of chip 13U7;

The first beacon relay module circuit consists of optocoupler 13U1, chip 13U2, chip 13U3, chip 13U4, constant current source 13D1-13D2, transistor 13Q01, potentiometer 13RJ01, resistor 13R11-13R13, resistor 13R21-13R25 and capacitor 13C11- 13C14; the model of the optocoupler 13U1 is TLP281-4, the model of the chip 13U2 is LM393, the model of the chip 13U3 is CN5710, the model of the chip 13U4 is 74HB74, the model of the constant current source 13D1-13D2 is S-102T, the triode The model of 13Q1 is 8550; pin 5 of the optocoupler 13U1 is the signal input terminal FHn-1 of the first beacon relay slave module circuit through the constant current source 13D2, and pin 7 of the optocoupler 13U1 is connected to the constant current source 13D1 through the potentiometer 13RJ01 The input terminal of the constant current source 13D1 is the clock input terminal CLK of the first beacon relay slave module circuit, and the clock input terminal CLK of the first beacon relay slave module circuit is connected to the clock output of the beacon relay master module circuit Port FHCLK; pin 1 of optocoupler 13U1 is connected to pin 5 of the chip 13U4 via resistor 13R13, pin 2 of optocoupler 13U1 is connected to pin 3, pin 4, pin 6 and pin 8 of optocoupler 13U1 are grounded, and pin 13U1 of optocoupler The 9 pins of the optocoupler 13U1 are grounded through the resistor 13R11, the 11 pins of the optocoupler 13U1 are grounded through the resistor 13R12, the 10 pins and 12 pins of the optocoupler 13U1 are connected to the output terminal +5V, and the capacitor 13C12 is connected between the 9 pins and the 12 pins of the optocoupler 13U1 Between, capacitor 13C11 is connected between pin 11 and pin 12 of optocoupler 13U1, pin 15 and pin 16 of optocoupler 13U1 are respectively connected to pin 13 and pin 14 of optocoupler 12U1 in the beacon relay main module circuit; The 15 pins of the coupling 13U1 are connected to the 10 pins of the chip 13U7, and the 16 pins of the optocoupler 13U1 are connected to the 19 pins of the chip 13U7; Pin 1, pin 4, and pin 14 of 13U4 are all connected to the output terminal +5V; the node of resistor 13R22 and resistor 13R21 is connected to pin 7 of chip 13U2, pin 7 of chip 13U2 is connected to pin 1 of chip 13U3, and the node of chip 13U2 is connected to pin 7 of chip 13U2. Pin 5 is grounded through resistor 13R24, pin 5 of chip 13U2 is connected to pin 13 of optocoupler 13U1, pin 2, pin 3 and pin 4 of chip 13U2 are grounded; pin 3 of chip 13U3 is grounded through resistor 13R25, pin 5 of chip 13U3 is grounded The pin is the clock output terminal CLK of the beacon relay slave module circuit, and the clock output terminal CLK of the beacon relay slave module circuit is connected to the input terminal of the constant current source 13D1; the base of the triode 13Q01 is connected to the 14 pin of the optocoupler 13U1, and the triode The emitter of 13Q01 is connected to the output terminal +5V, the collector of triode 13Q01 is the signal output terminal CFHn of the beacon relay slave module circuit, and the first beacon relay slave module circuit The signal output terminal CFHn of the circuit is connected to the signal input terminal of the beacon relay slave module circuit of the second slave terminal;

Pins 18 to 11 of the chip 2U7 of the IO expansion bus communication circuit in the data interaction intelligent host terminal are respectively connected to the first data bus DWKZ0 to the eighth data bus DWKZ7 of the data bus; the IO in the data interaction intelligent host terminal Pin 8 and pin 11 of 2U6 of the expansion bus communication circuit are respectively connected to the ninth data bus WKWRZ and the tenth data bus WKOEZ of the data bus.

The slave isolation card includes a slave AI isolation card circuit and a slave AO isolation card circuit, the slave AI isolation card circuit has the same structure as the AI isolation card circuit, and the slave AO isolation card circuit and the AO isolation card circuit The same structure; the slave AI isolation card circuit is connected to the analog signal port to be measured, the output of the slave AI isolation card circuit is connected to the corresponding input terminal of the slave core control unit, and the output terminal of the slave core control unit is connected to The corresponding input end of the slave AO isolation card circuit, the output end of the slave AO isolation card circuit is connected to the analog control signal port; the corresponding output end of the slave power management unit is respectively connected to the slave AI isolation card circuit, the slave The power input terminal of the AO isolation card circuit.

The slave isolation card includes a slave DIDO isolation card circuit, and the slave DIDO isolation card circuit has the same structure as the DIDO isolation card circuit; the slave DIDO isolation card circuit is bidirectionally connected with the slave core control unit; the slave DIDO The isolation card circuit is bidirectionally connected to the switch signal port; the corresponding output terminal of the slave power management unit is connected to the power input end of the slave DIDO isolation card circuit.

The present invention also relates to a communication method using an assembled data interactive intelligent terminal system, which utilizes the communication between the beacon relay master module and the beacon relay slave module, and the specific steps are as follows:

(1) Initialize the core processing unit, make the pin of the selection signal input terminal FH of the beacon relay main module be low level, and the pin of the clock signal input terminal CLK of the beacon relay main module be high level;

(2) The embedded chip 1U1 sends a selection signal to the pin of the selection signal input terminal FH of the beacon relay main module, that is, sends a high level;

(3) The embedded chip 1U1 sends a clock signal of one cycle to the pin of the clock signal input terminal CLK of the beacon relay main module, that is, high level-low level-high level;

(4) The embedded chip 1U1 sends a clear signal to the pin of the selection signal input terminal FH of the beacon relay main module, that is, low level, and clears the slave address i;

(5) The embedded chip 1U1 sends a clock signal of one cycle to the pin of the clock signal input terminal CLK of the beacon relay master module, and increments the slave address i by 1;

(6) The embedded chip 1U1 detects whether the slave address i is greater than the limit number m of the slave, if yes, then executes step (7), otherwise executes step (8);

(7) When the beacon relay slave module is abnormal, output an abnormal notification;

(8) The embedded chip 1U1 judges whether the termination signal is received, and the pin of the feedback signal output terminal FHFK of the beacon relay main module sends the selection signal to a low level. If not received, execute step (9), otherwise execute step (10);

(9) The embedded chip 1U1 outputs the read and write data notification, and then jumps to step (5);

(10) The embedded chip 1U1 judges whether the slave address i exceeds the number n of data interaction intelligent slave terminals detected by the beacon relay master module, if yes, jump to step (2), otherwise execute step (11) step;

(11) Embedded chip 1U1 outputs the notification that the slave terminal goes online and offline;

(12) Reset the number n of data interaction intelligent slave terminals to i-1, and jump to step (2);

In the above steps, i is the slave address; n is the number of slave terminals; m is the limit number of slave terminals; wherein, the value range of i is 1~100, the value range of n is 1~100, and the value of m is The value range is 1~100.

The working principle of this embodiment is as follows: the circuit principle of the relevant control unit: what this circuit adopts is the multiplexing mode of the address bus and the data bus, the output terminals of 1U2 and 1U3 and the low 16-bit address input terminals (A0~A15) of 1U4 Connect, 1U1 first outputs the read and write address, and controls 1U2 and 1U3 to latch the lower 16-bit address (IO0~1O15) through /ADV (pin 137), and then transmits the data to be read and written to 1U4 on IO0~1O15. The strobe is controlled by 1U1, and 1U4, 1U5, and 1U7 cannot be used at the same time. Since UART4 and UART5 of 1U1 share the operating pins of the SD card, in order to facilitate the secondary development, this circuit introduces an analog switch for gating, and can choose which mode to use during secondary development; the key is to provide a keyboard-like function , can be named as button 1, button 2, and so on. The specific function is determined by the secondary development, just as the Windows system is only responsible for passing the keyboard code value to the application program in the system. As for what the application program is used for, it is different from Windows System has nothing to do.

The technical problem to be solved by the present invention is the resource waste problem mentioned above, which uses a flexible assembled intelligent terminal to meet various demands of industrial sites. The invention takes the interface for realizing the transmission and collection of various signals as the basic unit, separates the core processing unit and the hardware processing units of various signals into independent components, and then selectively assembles them according to different requirements. The invention includes a data interaction host terminal and a data interaction extension slave terminal. AI interface, AO interface, DIDO interface, power interface, and co-processing unit are integrated on the motherboard of the data interaction host terminal; among them, the human-computer interaction unit, core processing unit, AI isolation card, AO isolation card, DIDO isolation card, power isolation card, The serial port expansion card, integrated communication interface card, PWM/counter isolation card, and IO expansion card are connected to the main board in a pluggable way. Except for the IO expansion card, secondary development can be carried out according to the needs. The main board is the main board of each interface board, and like a computer main board, it integrates a variety of interfaces for carrying various modules. It integrates AI interface, AO interface, DI interface, DO interface, power interface and co-processing unit. Among them, the co-processing unit is mainly used for the detection and transmission of internal signals, and the human-computer interaction unit is used for interacting with users. The core processing unit is a programmable MCU minimum system board, which is connected to the main board in a pluggable manner. And it is equipped with a completely open source .NET Micro Framework embedded system, and the driver used has been optimized to handle real-time tasks, which is very convenient for users to use C#.Net/VB.NET programming language for application development. The AI isolation card, AO isolation card, and DIDO isolation card are used to isolate external signals, which can be developed by secondary development users according to their own wishes. The power isolation card is also the power management unit, which is used to provide the required isolated DC power for the host. The serial expansion card is used to provide a multi-functional serial interface, which can be developed by secondary development users according to their own wishes. The integrated communication interface card is used to provide RS232 interface, CAN interface, Ethernet port, wireless communication interface to the outside world, and can also be developed by secondary development users according to their own wishes. The PWM/counter isolation card is used to provide PWM signal or count the input digital signal. The IO expansion card is used to interact with the data to expand the slave terminal connection.

Each data interaction expansion slave terminal contains a Beacon relay slave module, which can control the bus controller, and then control the connection between the data interaction slave terminal and the data bus, and each Beacon relay module is passed through Dedicated line communication is used to transmit strobe signals, so as to ensure that each data interaction slave terminal can access the data bus according to the wishes of the data interaction master terminal, and then realize data interaction with it. Each beacon relay module shares the clock line, and the module selection signal line is cascaded level by level. Just like a relay race, the gating signal is like a baton. The main module of the peak fire relay is only responsible for passing the baton to the first beacon relay The slave module, after processing the data of the first slave terminal, sends a transmission signal instruction, and the first beacon relay slave module passes the baton to the next beacon relay slave module, and so on. After the baton is passed to the last module, or the baton fails to be passed to the next module, the clock bus will generate a termination signal, and the main module can detect the termination signal. Determine from the number of modules whether the polling system is functioning properly.

The data interaction expansion slave terminal is composed of slave main board, AI isolation card, AO isolation card, DIDO isolation card, bus controller, and beacon relay slave module. The mainboard of the slave machine integrates the AI interface, AO interface, DI interface, DO interface, data bus interface, beacon relay slave module input interface and output interface; the AI isolation card, AO isolation card, DIDO isolation card interact with the data in the host terminal the substance of the same name as mentioned;

The bus controller is used to cut off or connect the channel of the data interaction expansion slave terminal and the data bus. The simplest implementation is to control the power supply of the data interaction expansion slave terminal data bus interface chip (only when the chip is powered off The pins connected to the bus are in a high-impedance state).

Claims (10)

1. A data interactive intelligent host terminal is characterized in that it includes a core control unit, a DIDO isolation card circuit, an AI isolation card circuit, an AO isolation card circuit, a co-processing unit interface circuit, a serial port isolation card circuit, an integrated communication card circuit, Human-computer interaction circuit, PWM counter isolation board circuit, IO expansion card circuit and power management unit; The core control unit is bidirectionally connected with the corresponding port of the serial port isolation card circuit, and the serial port isolation card circuit is connected with the serial port signal to be tested The port is bidirectionally connected; the core control unit is bidirectionally connected with the corresponding port of the integrated communication card circuit, and the integrated communication card circuit is bidirectionally connected with the serial digital signal port; the core control unit is connected with the IO expansion card circuit The corresponding ports are bidirectionally connected, and the IO expansion card circuit is bidirectionally connected with the multifunctional data interaction intelligent slave terminal port; the core control unit is bidirectionally connected with the corresponding ports of the co-processing unit interface circuit, and the co-processing unit interface circuit The first input terminal of the co-processing unit interface circuit is connected to the intrusion detection and interrupt input signal port, the first output terminal of the co-processing unit interface circuit is connected to the corresponding input terminal of the human-computer interaction circuit, and the second output terminal of the co-processing unit interface circuit is connected to the The corresponding input terminal of the PWM counter isolation board circuit; the human-computer interaction circuit is bidirectionally connected with the corresponding port of the core control unit; the core control unit is bidirectionally connected with the corresponding port of the PWM counter isolation board circuit, to be tested The pulse signal port of the pulse signal port is bidirectionally connected to the corresponding port of the PWM counter isolation board circuit; the output terminal of the core control unit is connected to the corresponding port input terminal of the AO isolation card circuit, and the output terminal of the AO isolation card circuit is connected to Analog control signal port; the input end of the AI isolation card circuit receives the analog signal port of measurement, and the output terminal of the AI isolation card circuit is connected to the corresponding input end of the core control unit; the DIDO isolation card circuit is connected to the core control unit The corresponding ports of the unit are bidirectionally connected, and the DIDO isolation card circuit is bidirectionally connected with the corresponding port of the switch signal port; the output terminals of the power management unit are respectively connected to the core control unit, DIDO isolation card circuit, AI isolation card circuit, AO Isolation card circuit, co-processing unit interface circuit, serial port isolation card circuit, integrated communication card circuit, human-computer interaction circuit, PWM counter isolation board circuit, corresponding power port of IO expansion card circuit, the input terminal of the power management unit is connected to the external power supply . 2. A data interaction intelligent host terminal according to claim 1, characterized in that: it also includes a main board and the first to tenth circuit boards; the co-processing unit interface circuit is arranged on the main board; the core control unit Set on the first circuit board; the DIDO isolation card circuit is set on the second circuit board; the AI isolation card circuit is set on the third circuit board; the AO isolation card circuit is set on the fourth circuit board; the serial port isolation card circuit It is set on the fifth circuit board; the integrated communication card circuit is set on the sixth circuit board; the human-computer interaction circuit is set on the seventh circuit board; the PWM counter isolation board circuit is set on the eighth circuit board; the IO expansion card circuit is set on On the ninth circuit board; the power management unit is arranged on the tenth circuit board; the first to tenth circuit boards are connected to the main board in a plug-in manner. 3. A data interaction intelligent host terminal according to claim 2, characterized in that: the power management unit consists of chip U1, chip U5, chip U8, diode D101, inductor L101, capacitor C101-capacitor C105, resistor R101 - composed of resistor R104; the model of the chip U1 is MP2403, the model of the chip U5 is APL117-3.3, the model of the chip U8 is DC1212, and the model of the diode D101 is SS14; The input pin 2 of the chip U1 is connected to the external power supply WB; the output pin 3 of the chip U1 is connected to one end of the inductor L101, and the other end of the inductor L101 is the output terminal +5V; the capacitor C101 is connected to the input pin 2 of the chip U1 Between the ground and the ground, the diode D101 is connected between the output pin 3 of the chip U1 and the ground, the capacitor C102 is connected between the 1 pin and the 3 pin of the chip U1, the 4 pin of the chip U1 is grounded, and the 5 pin of the chip U1 is connected by a resistor R102 is connected to the output terminal +5V, resistor R101 is connected between pin 5 of chip U1 and ground, capacitor C104 is connected in series with resistor R103 between pin 6 of chip U1 and ground, and capacitor C105 is connected to output terminal + Between 5V and ground, resistor R104 is connected between pin 7 and pin 2 of chip U1, and capacitor C103 is connected between pin 8 of chip U1 and ground; The input terminal Vin of the chip U5 is connected to the output terminal +5V, the output terminal Vout of the chip U5 is the output terminal +3.3V, and the ground terminal of the chip U5 is grounded; The input pin 2 of the chip U8 is connected to the external power supply WB, the 1 pin and the 3 pin of the chip U8 are grounded, and the 4 pin of the chip U8 is the output terminal +12V; The core control unit includes an embedded chip 1U1 and its peripheral components switch 1S2, crystal oscillator 1Y101-1Y102, resistors 1R101-1R103, capacitors 1C101-1C107, data latches 1U2-1U3 and inverter chip 1U8; The type chip 1U1 is an embedded chip of the type STM32F103ZET6 implanted with the .Net Micro Framwork microframe, and the reset circuit composed of the switch 1S2, the resistor 1R103 and the capacitor 1C105 is connected between pin 25 of the embedded chip 1U1 and the ground. The first crystal oscillator circuit composed of the crystal oscillator 1Y102, resistor 1R102 and capacitor 1C103-1C104 is connected between pin 23 and pin 24 of the embedded chip 1U1, and the second crystal oscillator circuit composed of the crystal oscillator 1Y101, resistor 1R101 and capacitor 1C101-1C102 The circuit is connected between pins 8 and 9 of the embedded chip 1U1; the model of the data latch 1U2-1U3 is 74HC573, and the input pins 2-9 of the data latch 1U2 are respectively connected to the embedded 86-85 pins, 114-115 pins, 58-60 pins, 63 pins of the chip 1U1, 10 pins of the data latch 1U2 are grounded, and 20 pins of the data latch 1U2 are connected to the output terminal +3.3 V; the input pins 2-9 pins of the data latch 1U3 are respectively connected to the 64-68 pins and 77-79 pins of the embedded chip 1U1, and the 10 pins of the data latch 1U3 are grounded, and the data lock Pin 20 of the memory 1U3 is connected to the output terminal +3.3V; the model of the inverter chip 1U8 is 74LVC2G04, and pin 1 of the inverter chip 1U8 is connected to pin 137 of the embedded chip 1U1. Pin 3 of the inverter chip 1U8 is connected to pin 110 of the embedded chip 1U1, and pin 6 of the inverter chip 1U8 is connected to pin 11 of the data latch 1U2 and pin 11 of the data latch 1U3, inverting Pin 2 of the inverter chip 1U8 is grounded, and pin 5 of the inverter chip 1U8 is connected to the output terminal +3.3V; The core control unit also includes a chip 1U4, a chip 1U5, and a chip 1U7; The model of the chip 1U4 is an externally expanded SRAM chip SRAM-IS62WV51216BLL, and the 7-pin-10 pin, 13-pin-16 pin, 29-pin-32 pin, and 35-pin-38 pin of the chip 1U4 are respectively connected to the embedded chip 86-85 pins, 114-115 pins, 58-60 pins, 63-68 pins, 77-79 pins of 1U1; 5-1 pins, 44-42 pins, 27 pins of the chip 1U4 Pin-24 pins, 22 pins-19 pins are respectively connected to the output pins 19-12 pins of the data latch 1U2, and the output pins 19-12 pins of the data latch 1U3; the 18 pins, Pins 23 and 28 are respectively connected to pins 80-82 of the embedded chip 1U1; pins 6, 17, 39-41 of the chip 1U4 are respectively connected to pins 123 and 119 of the embedded chip 1U1 , 41 pins-42 pins, 118 pins; the 11 pins and 33 pins of the power supply end of the chip 1U4 are connected to the output terminal +3.3V, the capacitor 1C401 is connected between the 11 pins of the chip 1U4 and the ground, and the capacitor 1C402 is connected to the chip 1U4 Between pin 33 and ground, resistor 1R401 is connected between pin 6 of chip 1U4 and the output terminal +3.3V; The model of the chip 1U5 is the external expansion FLASH chip MX29LV320, and the 29 pins, 31 pins, 33 pins, 35 pins, 38 pins, 40 pins, 42 pins, 44 pins, 30 pins, 32 pins, and 34 pins of the chip 1U5 , 36 pins, 39 pins, 41 pins, 43 pins, and 45 pins are respectively connected to 86 pins-85 pins, 114 pins-115 pins, 58 pins-60 pins, 63 pins-68 pins, and 77 pins of the embedded chip 1U1 -79 pins; 25 pins-18 pins and 8 pins-1 pins of the chip 1U5 are respectively connected to the output pins 19-12 pins of the data latch 1U2, and the output pins 19-12 pins of the data latch 1U3 Pins; 48 pins, 17 pins-16 pins, 9 pins-10 pins of the chip 1U5 are respectively connected to 80 pins-82 pins, 2 pins-3 pins of the embedded chip 1U1; 11 pins, 2 pins-3 pins of the chip 1U5 12 pins, 15 pins, 28 pins, and 26 pins are respectively connected to 119 pins, 25 pins, 122 pins, 118 pins, and 125 pins of the embedded chip 1U1; 14 pins of the chip 1U5 are connected to the output terminal through a resistor 1R502 +3.3V, the 15 pins of the chip 1U5 are connected to the output terminal +3.3V through the resistor 1R501, the 37 pins of the chip 1U5 are connected to the output terminal +3.3V, and the filter capacitor 1C501 is connected to the 37 pins of the chip 1U5 and Between the ground; The chip 1U7 is an external expansion memory MT29F1G08, and the 29 pins-32 pins, 41 pins-44 pins, 26 pins-28 pins, 33 pins, 40 pins, 45 pins-47 pins of the chip 1U7 are respectively connected to the embedded 86-pin-85 pin, 114-pin-115 pin, 58-pin-60 pin, 63-pin-68 pin, 77-pin-79 pin of chip 1U1; 7-pin, 8-pin, 9-pin, 18-pin of chip 1U7 respectively Connect the 122 pins, 118 pins, 124 pins, and 119 pins of the embedded chip 1U1; the 16 pins-17 pins of the chip 1U7 are respectively connected to the 81 pins-80 pins of the embedded chip 1U1; Pin 19 is connected to pin 14 of the chip 1U5; pins 12, 34, 37, and 39 of the chip 1U7 are all connected to the output terminal +3.3V, and the capacitor 1C701 is connected between pin 12 of the chip 1U7 and the ground . 4. A data interaction intelligent host terminal according to claim 3, characterized in that: The IO expansion card circuit includes an IO expansion bus communication circuit and a beacon relay main module circuit; The IO expansion card circuit includes an IO expansion bus communication circuit and a beacon relay main module circuit; the IO expansion bus communication circuit consists of optocoupler 2U5, NAND gate 2U6, optocoupler 2U1 to 2U4, chips 2U7 to 2U8, and resistance 2RP101 to 2RP104 and resistors 2R501 to 2R506; the model of the optocoupler 2U5 is TLP281-2, the model of the NAND gate 2U6 is 74HC00, the model of the optocoupler 2U1 to 2U4 is TLP281-4, and the model of the chip 2U7 to 2U8 is 74HC245 ; The beacon relay main module circuit consists of chip 12U4, amplifier 12U3, optocoupler 12U1, chip 12U2, chip 12U5, constant current source 12U6, triode 12Q01-transistor 12Q03, potentiometer 12RJ01, resistor 12R11-resistance 12R15, resistor 12R31-resistance 12R35 , resistor 12R22-resistor 12R27 and capacitor 12C31-capacitor 12C33; the model of the chip 12U4 is 74HC74, the model of the amplifier 12U3 is LM358, the model of the optocoupler 12U1 is TLP281-4, the model of the chip 12U2 is LM393, and the model of the chip 12U5 The model is CN5710, and the model of the constant current source 12U6 is E-102T; The serial port isolation card circuit includes first to fourth serial port isolation card circuits; the first to fourth serial port isolation card circuits have the same structure; wherein the first serial port isolation card circuit is composed of chip 10U1 to chip 10U7, digital transistor 10Q3 to digital Transistor 10Q5, diode 10D1, resistors 10R51 to 10R59, and capacitors 10C11 to 10C21 are composed; the model of the chip 10U1 is MAX232, the model of the chip 10U2 is MAX485, the model of the chip 10U3 is SN75179B, and the model of the chip 10U4 is XC6401. The model of 10U5 is TLP281-2, the model of chip 10U6 is ADUM1201ARZ, and the model of chip 10U7 is DC-DC05; the transistor 10Q3 and transistor 10Q4 are PNP digital transistors, and the transistor 10Q5 is an NPN digital transistor; diode 10D1 is a common cathode type diode; the second serial port isolation card circuit consists of chip 2-10U1 to chip 2-10U7, digital transistor 2-10Q3 to digital transistor 2-10Q5, diode 2-10D1, resistor 2-10R51 to resistor 2-10R59 and Composed of capacitor 2-10C11 to capacitor 2-10C21; the third serial port isolation card circuit consists of chip 3-10U1 to chip 3-10U7, digital transistor 3-10Q3 to digital transistor 3-10Q5, diode 3-10D1, resistor 3 -10R51 to resistor 3-10R59 and capacitor 3-10C11 to capacitor 3-10C21; the fourth serial port isolation card circuit consists of chip 4-10U1 to chip 4-10U7, digital triode 4-10Q3 to digital triode 4-10Q5 , diode 4-10D1, resistor 4-10R51 to resistor 4-10R59 and capacitor 4-10C11 to capacitor 4-10C21; The AI isolation card circuit includes a first AI isolation circuit and a second AI isolation circuit; the first AI isolation circuit is composed of amplifier 4U1, amplifier 4U2, resistance 4R11-4R18, resistance 4R21-resistance 4R28, resistance 4R31-resistance 4R38, Composed of capacitors 4C11-4C12 and exclusion resistors 4RP511-4RP512; the models of the amplifier 4U1 and amplifier 4U2 are both LM324; The AO isolation card circuit is composed of an amplifier 5U1, transistors 5Q1-5Q2, resistors 5R1-5R12 and capacitors 5C1-5C2; the model of the amplifier 5U1 is LM324; The co-processing unit circuit is composed of a parallel-to-serial conversion input circuit and a serial-to-parallel conversion output circuit; the parallel-to-serial conversion input circuit consists of chip 6U1, chip 6U5 to chip 6U7, chip 6UA to chip 6UB, triode 6Q701-6Q702, triode 6Q602 , resistors 6R701-6R708, resistors 6R601-6R603, capacitors 6C701-6C702, and capacitors 6C601-6C605; the model of the chip 6U1 is TLP281-2, the model of the chips 6U5 to 6U6 is 74HC165, and the model of the chip 6U7 is BL1551, the model of the chip 6UA is 74HC165, and the model of the chip 6UB is 74HC86; The serial-to-parallel conversion output circuit is composed of chips 7U1 to 7U5, chips 7U8 to 7U9, capacitors 7C701 to 7C705, and capacitors 7C708 to 7C709; the models of chips 7U1 to 7U5 and chip 7U9 are 74HC594. The model of chip 7U8 is 74HC139; The 2 pins and 4 pins of the optocoupler 2U5 of the IO expansion bus communication circuit are grounded, the 6 pins and 8 pins of the optocoupler 2U5 are connected to the output terminal +5V, and the 5 pins and 7 pins of the optocoupler 2U5 are respectively connected to the resistor 2R504 , resistance 2R503 is grounded; pins 1, 5, 10, 13-14 of the NAND gate 2U6 are connected to the output +5V, pins 3 and 12 of the NAND gate 2U6 are connected, and the NAND gate 2U6 The 6 pins of the NAND gate 2U6 are connected to the 9 pins, the 2 pins of the NAND gate 2U6 are connected to the 7 pins of the optocoupler 2U5, and the 4 pins of the NAND gate 2U6 are connected to the 5 pins of the optocoupler 2U5; Optocouplers 2U1 to 2U2, chip 2U7, and exclusion 2RP101 to 2RP102 form a signal output circuit; one end of the exclusion 2RP101 to 2RP102 is connected to pins 93, 10-15, and 132 of the embedded chip 1U1. The other end of resistance 2RP101 to 2RP102 is sequentially connected to pin 1, pin 3, pin 5, and pin 7 of the optocoupler 2U1, pin 1, pin 3, pin 5, and pin 7 of the optocoupler 2U2; pin 2 of the optocoupler 2U1 pins, 4 pins, 6 pins, 8 pins, 2 pins, 4 pins, 6 pins, 8 pins of 2U2 are grounded; 16 pins, 14 pins, 12 pins, 10 pins of the optocoupler 2U1, 16 pins of 2U2, Pins 14, 12, and 10 are all connected to the output terminal +3.3V; pins 15, 13, 11, and 9 of the optocoupler 2U1, and pins 15, 13, 11, and 9 of 2U2 are in order Connect pins 2-9 of the chip 2U7; pins 1 and 20 of the chip 2U7 are connected to the output terminal +3.3V, and pin 19 of the chip 2U7 is connected to pin 6 of the NAND gate 2U6; Optocouplers 2U3 to 2U4, chip 2U8, and exclusion 2RP103 to 2RP06 form a signal input circuit; one end of the exclusion 2RP103 to 2RP104 is sequentially connected to pins 18-11 of the chip 2U7, and the other end of the exclusion 2RP103 to 2RP104 is in turn Connect pins 1, 3, 5, and 7 of the optocoupler 2U3, pins 1, 3, 5, and 7 of the optocoupler 2U4; pins 2, 4, and 6 of the optocoupler 2U3 8 pins, 2 pins, 4 pins, 6 pins, and 8 pins of 2U4 are all grounded; 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 2U3, 16 pins, 14 pins, 12 pins, and 10 pins of 2U4 Both are connected to the output terminal +3.3V; the 15 pins, 13 pins, 11 pins, and 9 pins of the optocoupler 2U3, and the 15 pins, 13 pins, 11 pins, and 9 pins of the 2U4 are sequentially connected to the 2 pins-9 of the chip 2U8 pin; pin 1 and pin 20 of the chip 2U8 are all connected to the output terminal +3.3V, and pin 19 of the chip 2U8 is connected to pin 4 of the chip 7U9 of the serial-to-parallel conversion output circuit of the co-processing unit interface circuit; pin 18 of the chip 2U8 Pins-11 are sequentially connected to pins 93, 10-15, and 132 of the embedded chip 1U1, and pins 2-9 of the chip 2U8 are grounded through exclusion 2RP105 and 2RP106; The 12 pins of the chip 12U4 are connected to the 49 pins of the embedded chip 1U1, the 11 pins of the chip 12U4 are connected to the 50 pins of the embedded chip 1U1, the 5 pins of the chip 12U4 are the feedback signal FHFK of the beacon relay main module circuit, and the 1 pins of the chip 12U4 are Pin, pin 4, pin 10, pin 13, and pin 14 are connected to the output terminal +3.3V, pin 2 of the chip 12U4 is grounded through a resistor 12R14, pin 3 of the chip 12U4 is connected to the collector of the triode 12Q03; the triode 12Q03 The collector is connected to the output terminal +3.3V through the resistor 12R34, the base is connected to the pin 7 of the amplifier 12U3 through the resistor 12R33, the emitter of the triode 12Q03 is grounded, and the capacitor 12C32 is connected between the base of the triode 12Q03 and the ground ; Pin 1 of the amplifier 12U3 is connected to pin 6 of the optocoupler 12U1, resistor 12R31 and resistor 12R32 are connected in series between the output terminal +3.3V and ground, pin 2 and pin 6 of the amplifier 12U3 are connected The node of resistor 12R31 and resistor 12R32, pin 7 of the amplifier 12U3 is connected to pin 7 of the optocoupler 12U1; pin 3 of the amplifier 12U3 is connected to pin 12 of the chip 12U4, pin 5 of the amplifier 12U3 is connected to pin 11 of the chip 12U4 ; Pin 3 of the optocoupler 12U1 is connected to pin 9 of the chip 12U4, pin 1 of the optocoupler 12U1 is connected to the collector of the triode 12Q02 through the potentiometer 12RJ01, and the resistor 12R25 and resistor 12R24 are connected in series to the 12U2 Between pin 7 and the ground, the base of the triode 12Q02 is connected to the node of the resistor 12R25 and the resistor 12R24, the emitter of the triode 12Q02 is grounded, pin 2 of the optocoupler 12U1 is grounded through the constant current source 12U6, pin 4 of the optocoupler 12U1 is connected to the optocoupler The 5 pins of the optocoupler 12U1 are connected, the 8 pins of the optocoupler 12U1 are grounded through the resistor 12R15, the 9 pins of the optocoupler 12U1 are grounded through the resistor 12R13, the 11 pins of the optocoupler 12U1 are grounded through the resistor 12R12, the 10 pins and 16 pins of the optocoupler 12U1 are grounded Connect to +5V, pin 15 of the optocoupler 12U1 is connected to pin 2 of the chip 12U4; pin 5 of the chip 12U2 is connected to pin 11 of the optocoupler 12U1, pin 7 of the chip 12U2 is connected to the output terminal + through a resistor 12R26 5V, pin 1 of the chip 12U2 is connected to the output terminal +5V through the resistor 12R23, pin 6 of the chip 12U2 is connected to pin 2, pin 3 of the chip 12U2 is connected to pin 9 of the optocoupler 12U1; pin 1 of the chip 12U5 The pin is connected to pin 1 of the chip 12U2, the pin 3 of the chip 12U5 is grounded through the resistor 12R27, the pin 5 of the chip 12U5 is connected to the collector of the triode 12Q02, and the pin 5 of the chip 12U5 is the clock output port FHCLK of the beacon relay main module circuit ; The base of the triode 12Q01 is connected to the 12 pins of the optocoupler 12U1, the resistor 12R21 and the resistor 12R22 are connected in series between the output terminal +5V and the ground, and the 2 pins of the chip 12U2 are connected to The node of resistor 12R21 and resistor 12R22, the collector of triode 12Q01 is the signal sending port FHn of the beacon relay main module circuit; Pin 2 of the chip 10U7 of the first serial port isolation card circuit is connected to the output terminal +5V, pin 1 of the chip 10U7 of the first serial port isolation card circuit is grounded, and pin 3 of the chip 10U7 of the first serial port isolation card circuit is output In isolation, pin 4 of the chip 10U7 of the first serial port isolation card circuit is an output isolated power supply, pin 2 of the chip 10U4 is connected to pin 4 of the chip 10U7, pin 1 of the chip 10U4 is connected to the chip 10U7 via a resistor 10R59 The collector of digital transistor 10Q5 is connected to pin 1 of chip 10U4, the base of transistor 10Q5 is connected to pin 3 of chip 10U4, the emitter of transistor 10Q5 is connected to pin 3 of chip 10U7, and the capacitor 10C21 is connected to the collector of transistor 10Q5 Between pin 3 of chip 10U7; pin 6 of chip 10U4 is the first output terminal VCC1, pin 4 of chip 10U4 is the second output terminal VCC2, pin 5 of chip 10U4 is connected to pin 3 of chip 10U7, and pin 4 of chip 10U4 is connected to pin 3 of chip 10U4. Pin 6 is connected to the first anode of the diode 10D1, pin 4 of the chip 10U4 is connected to the second anode of the diode 10D1, the cathode of the diode 10D1 is the output terminal VCC0, and the capacitor 10C19 is connected to pin 6 of the chip 10U4 and pin 3 of the chip 10U7. Between pins, capacitor 10C20 is connected between pin 4 of chip 10U4 and pin 3 of chip 10U7; Pin 2 of the chip 10U6 is connected to pin 101 of the embedded chip 1U1, pin 3 of the chip 10U6 is connected to pin 102 of the embedded chip 1U1, pin 1 of the chip 10U6 is connected to the output terminal +5V, and the resistor 10R57 is connected to Between pin 2 and pin 7 of chip 10U6, resistor 10R58 is connected between pin 3 and pin 6 of chip 10U6, pin 8 of chip 10U6 is connected to the output terminal VCC0, and capacitor 10C18 is connected between pin 1 and pin 10U6 of chip 10U6. Between the 3 pins of 10U7, the capacitor 10C17 is connected between the 8 pins of the chip 10U6 and the 3 pins of the chip 10U7; the emitter of the triode 10Q3 is connected to the output terminal VCC0, and the base of the triode 10Q3 is connected to the chip 10U5 8 pins, the collector of the triode 10Q3 is connected to the 3 pin of the chip 10U7 through the resistor 10R53, the emitter of the triode 10Q4 is connected to the output terminal VCC0, the base of the triode 10Q4 is connected to the 6 pin of the chip 10U5, and the collector of the triode 10Q4 The electrode is connected to pin 3 of chip 10U7 via resistor 10R54, the collector of triode 10Q4 is connected to pin 3 of chip 10U4; pin 1 of chip 10U5 is connected to pin 1 of 7U9 via resistor 10R55, and pin 3 of chip 10U5 is connected to pin 3 of chip 10U5 via resistor 10R56 Pin 15 of 7U1, the collector of triode 10Q3 is connected to pin 15 of 7U9 through resistor 10R51, the collector of triode 10Q4 is connected to pin 15 of 7U1 through resistor 10R52, and pins 2, 4, 5 and 7 of chip 10U5 are all connected to the chip Pin 3 of 10U7; pin 1 of the chip 10U2 is connected to pin 7 of the chip 10U6; pin 2 and pin 3 of the chip 10U2 are connected to the collector of the triode 10Q3; pin 4 of the chip 10U2 is connected to pin 6 of the chip 10U6 , pin 8 of the chip 10U2 is connected to the output terminal VCC2, and a capacitor 10C16 is connected between pin 8 of the chip 10U2 and pin 3 of the chip 10U7; pin 1 of the chip 10U3 is connected to the output terminal VCC2, and pin 2 of the chip 10U3 Connect pin 1 of chip 10U2, pin 3 of chip 10U3 connect pin 4 of chip 10U2, pin 7 of chip 10U3 connect pin 7 of chip 10U2, pin 8 of chip 10U3 connect pin 6 of chip 10U2; pin 11 of chip 10U1 Connect to pin 3 of chip 10U3, pin 12 of chip 10U1 to pin 2 of chip 10U3, pin 13 of chip 10U1 to pin 7 of chip 10U3, pin 14 of chip 10U1 to pin 8 of chip 10U3, capacitor 10C13 to pin 10U1 Between pin 1 and pin 3, capacitor 10C15 is connected between pin 4 and pin 5 of chip 10U1, pin 16 of chip 10U1 is connected to the output terminal VCC1, capacitor 10C11 is connected between pin 16 of chip 10U1 and pin 3 of chip 10U7 between pin 2 of chip 10U1 and pin 3 of chip 10U7, and capacitor 10C14 is connected between pin 6 of chip 10U1 and pin 3 of chip 10U7; The 2 pins of the chip 2-10U6 of the second serial port isolation card circuit are connected to the 37 pins of the embedded chip 1U1, the 3 pins of the chip 2-10U6 are connected to the 36 pins of the embedded chip 1U1, and the 36 pins of the chip 2-10U5 are connected to the embedded chip 1U1. Pin 3 is connected to pin 2 of 7U1, pin 1 of chip 2-10U5 is connected to pin 1 of 7U9; pin 2 of chip 3-10U6 of the third serial port isolation card circuit is connected to pin 70 of embedded chip 1U1, Pin 3 of the chip 3-10U6 is connected to pin 69 of the embedded chip 1U1, pin 3 of the chip 3-10U5 is connected to pin 4 of the 7U1, pin 1 of the chip 3-10U5 is connected to pin 2 of the 7U9; Pin 2 of the chip 4-10U6 of the fourth serial port isolation card circuit is connected to pin 112 of the embedded chip 1U1, pin 3 of the chip 4-10U6 is connected to pin 111 of the embedded chip 1U1, and pin 3 of the chip 4-10U5 Connect pin 6 of 7U1, pin 1 of chip 4-10U5 connect pin 3 of 7U9; The DIDO isolation card circuit includes a DIDO isolation circuit, a DI isolation circuit, a DO isolation circuit and a DO drive circuit; The DO drive circuit includes eight drive circuits with the same structure, which are the first DO drive circuit to the eighth DO drive circuit; Composed of R3; the collector of the triode Q1 is connected to the external drive power WV through the resistor R3 and the resistor R2 in turn, the collector of the triode Q1 is the output pin O+, connected to the switch signal port, and the emitter of the triode Q1 is the output of the first DO drive circuit. Pin O-, the base of the triode Q1 is connected to the collector of the triode Q2; the emitter of the triode Q2 is connected to the external drive power WV through the resistor R2, and the base of the triode Q2 is the input pin OC+ of the first DO drive circuit; The diode D2 is connected between the external driving power supply WV and the output pin O+, and the light emitting diode DS1 is connected between the emitter of the triode Q2 and the input pin OC+; The second DO drive circuit is composed of triodes 2-Q1 to 2-Q2, light emitting diodes 2-DS1, diodes 2-D2, and resistors 2-R2 to 2-R3; the collector of the triode 2-Q1 is the output pin O+, Connect the switch signal port, the emitter of the triode 2-Q1 is the output pin O- of the second DO drive circuit, the base of the triode 2-Q2 is the input pin OC+ of the second DO drive circuit; the third DO drive circuit consists of the triode 3 -Q1 to 3-Q2, light-emitting diode 3-DS1, diode 3-D2, resistors 3-R2 to 3-R3; the collector of the triode 3-Q1 is the output pin O+, connected to the switch signal port, and the triode 3-Q1 The emitter is the output pin O- of the third DO drive circuit, the base of the triode 3-Q2 is the input pin OC+ of the third DO drive circuit; -DS1, diode 4-D2, and resistors 4-R2 to 4-R3; the collector of the triode 4-Q1 is the output pin O+, connected to the switch signal port, and the emitter of the triode 4-Q1 is the output pin of the fourth DO drive circuit O-, the base of the triode 4-Q2 is the input pin OC+ of the fourth DO drive circuit; the fifth DO drive circuit consists of triodes 5-Q1 to 5-Q2, light emitting diode 5-DS1, diode 5-D2, resistor 5 -R2 to 5-R3; the collector of the triode 5-Q1 is the output pin O+, connected to the switch signal port, the emitter of the triode 5-Q1 is the output pin O- of the fifth DO drive circuit, and the base of the triode 5-Q2 is The input pin OC+ of the fifth DO drive circuit; the sixth DO drive circuit is composed of transistors 6-Q1 to 6-Q2, light emitting diodes 6-DS1, diodes 6-D2, and resistors 6-R2 to 6-R3; the transistor 6 The collector of -Q1 is the output pin O+, connected to the switch signal port, the emitter of the triode 6-Q1 is the output pin O- of the sixth DO drive circuit, and the base of the triode 6-Q2 is the input pin OC+ of the sixth DO drive circuit; The seventh DO drive circuit is composed of triodes 7-Q1 to 7-Q2, light-emitting diodes 7-DS1, diodes 7-D2, and resistors 7-R2 to 7-R3; the collector of the triode 7-Q1 is the output pin O+, Connect the switch signal port, the emitter of the triode 7-Q1 is the output pin O- of the seventh DO drive circuit, the base of the triode 7-Q2 is the input pin OC+ of the seventh DO drive circuit; the eighth DO drive circuit is composed of the transistor 8 -Q1 to 8-Q2, light-emitting diode 8-DS1, diode 8-D2, resistors 8-R2 to 8-R3; the collector of the triode 8-Q1 is the output pin O+, connected to the switch signal port, and the triode 8-Q1 The emitter is the output pin O- of the eighth DO drive circuit, and the base of the transistor 8-Q2 is the input pin OC+ of the eighth DO drive circuit; The DO isolation circuit includes a first DO isolation circuit and a second DO isolation circuit; the structure of the second DO isolation circuit is the same as that of the first DO isolation circuit; , Light-emitting diodes 3DO1-3DO4; the 2 pins, 4 pins, 6 pins, and 8 pins of the optocoupler 3U1 are connected to the ground, and the 1 pins, 3 pins, 5 pins, and 7 pins of the optocoupler 3U1 are respectively connected to the light-emitting diodes 3DO1-3DO4 One end of the exclusion 3RP1, the other end of the exclusion 3RP1 is the input terminal 3MDKI0~3MDKI3 of the first DO isolation circuit, and the 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 3U1 are respectively connected to the first DO drive circuit to the fourth The input pin OC+ of the DO drive circuit, and the 15 pins, 13 pins, 11 pins, and 9 pins of the optocoupler 3U1 are respectively connected to the output pin O- of the first DO drive circuit to the fourth DO drive circuit; The second DO isolation circuit is composed of optocoupler 2-3U1, exclusion 2-3RP1, and light-emitting diodes 2-3DO1 to 2-3DO4; pins 1, 3, 5, and 7 of optocoupler 2-3U1 are respectively The light-emitting diodes 2-3DO1 to 2-3DO4 are connected to one end of the resistance exclusion 2-3RP1, and the other end of the exclusion resistance 2-3RP1 is the input terminal 3MDKI0~3MDKI3 of the second DO isolation circuit. The 16 pins of the optocoupler 2-3U1, Pins 14, 12, and 10 are respectively connected to the input pin OC+ of the fifth DO drive circuit to the eighth DO drive circuit, and pins 15, 13, 11, and 9 of the optocoupler 2-3U1 are respectively connected to the fifth DO drive circuit. To the output pin O- of the eighth DO drive circuit; The DI isolation circuit includes a first DI isolation circuit and a second DI isolation circuit; the second DI isolation circuit has the same structure as the first DI isolation circuit; -3RP4, light-emitting diode 3DI1-3DI4; the 2 pins, 4 pins, 6 pins, and 8 pins of the optocoupler 3U5 are connected to the common end of the switch signal, and the 1 pin, 3 pins, 5 pins, and 7 pins of the optocoupler 3U5 are respectively Connect the 4-way switch signal ports with 3RP4 and light-emitting diodes 3D11-3D14 through resistance exclusion, connect pins 10, 12, 14, and 16 of the optocoupler 3U5, and then connect the output terminal +3.3V, and connect pins 15 and 16 of the optocoupler 3U5. Pins 13, 11, and 9 are grounded through the exclusion 3RP3, and pins 15, 13, 11, and 9 of the optocoupler 3U5 are respectively the signal output terminals 3MDKO0~3MDKO3 of the first DI isolation circuit; the second DI The isolation circuit is composed of optocoupler 2-3U5, exclusion 2-3RP3 to 2-3RP4, light emitting diode 2-3DI1 to 2-3DI4; the 15 pins, 13 pins, 11 pins and 9 pins of the optocoupler 2-3U5, They are the signal output terminals 3MDKO0~3MDKO3 of the second DI isolation circuit; The DIDO isolation circuit is composed of chips 3U2-3U3, digital transistor 3Q1, resistor 3R1, and capacitor 3C1-3C2. The 20 pins of the chips 3U2-3U3 are all connected to the output terminal +3.3V, and the 10 pins of the chips 3U2-3U3 are all grounded. , the 19 pins of the chip 3U2 are connected to the 11 pins of the chip 7U8, the 18 pins-11 pins of the chip 3U2 are connected to the 2 pins-9 pins of the chip 3U3, and the 18 pins-11 pins of the chip 3U2 are respectively connected to the 56-pins of the embedded chip 1U1 57 pins, 87-92 pins, pin 1 of the chip 3U2 is connected to pin 5 of the chip 7U9, pins 2-5 of the chip 3U2 are connected to the signal output terminal 3MDKO0~3MDKO3 of the first DI isolation circuit, pins 6-9 of the chip 3U2 Connect to the signal output terminal 3MDKO0~3MDKO3 of the second DI isolation circuit; pin 1 of the chip 3U3 is connected to pin 3 of the chip 7U5, pin 11 is connected to the collector of the digital transistor 3Q1, pins 19-16 of the chip 3U3 are connected to the first DO isolation circuit The input terminal 3MDKI0~3MDKI3 of the chip 3U3 is connected to the input terminal 3MDKI0~3MDKI3 of the second DO isolation circuit, the base of the digital triode 3Q1 is connected to the 1 pin of the chip 3U2, and the emitter of the digital triode 3Q1 is connected to the chip 3U2 The resistor 3R1 is connected between the 11th pin of the chip 3U3 and the ground, the capacitor 3C1 is connected between the 20th pin of the chip 3U2 and the ground, and the capacitor 3C2 is connected between the 20th pin of the chip 3U3 and the ground; The models of the amplifier 4U1 and the amplifier 4U2 of the first AI isolation circuit are both LM324, the same-direction input terminal 3 of the amplifier 4U1 is an analog signal port to be measured, and the same-direction input terminal 3 of the amplifier 4U1 is grounded through a resistor 4R31 , pin 2 of the reverse input terminal of the amplifier 4U1 is grounded through a resistor 4R12, pin 1 of the output terminal of the amplifier 4U1 is connected to pin 2 of the reverse input terminal of the amplifier 4U1 through a feedback resistor 4R11; pin 5 of the same input terminal of the amplifier 4U1 is used for measurement The analog signal port of the amplifier 4U1, the 5 pins of the same input end of the amplifier 4U1 are grounded through the resistor 4R32, the 6 pins of the reverse input end of the amplifier 4U1 are grounded through the resistor 4R14, the 7 pins of the output end of the amplifier 4U1 are connected to the reverse direction of the amplifier U1 through the feedback resistor 4R13 The 6-pin input terminal; the 10-pin input terminal of the amplifier 4U1 receives the analog signal port for measurement, the 10-pin input terminal of the amplifier 4U1 is grounded through the resistor 4R33, and the 9-pin reverse input terminal of the amplifier 4U1 is grounded through the resistor 4R16 , the output terminal 8 pins of the amplifier 4U1 are connected to the reverse input terminal 9 pins of the amplifier 4U1 through the feedback resistor 4R15; Grounded through resistor 4R34, the reverse input terminal 13 of the amplifier 4U1 is grounded through the resistor 4R18, the output terminal 14 of the amplifier 4U1 is connected to the reverse input terminal 13 of the amplifier 4U1 through the resistor 4R17; the 4 pin of the amplifier 4U1 is connected to the The output terminal is +5V, and the capacitor 4C11 is connected between pin 4 of the amplifier 4U1 and the ground; The 3 pins of the same input end of the amplifier 4U2 receive the analog signal port for measurement, the 3 pins of the same input end of the amplifier 4U2 are grounded through the resistor 4R35, the 2 pins of the reverse input end of the amplifier 4U2 are grounded through the resistor 4R22, and the output of the amplifier 4U2 Pin 1 of the terminal is connected to pin 2 of the reverse input terminal of the amplifier 4U2 through the feedback resistor 4R21; pin 5 of the same input terminal of the amplifier 4U2 receives the analog signal port for measurement, and pin 5 of the same input terminal of the amplifier 4U2 is grounded through the resistor 4R36. The 6 pins of the reverse input terminal of the amplifier 4U2 are grounded through the resistor 4R24, the 7 pins of the output terminal of the amplifier 4U2 are connected to the 6 pins of the reverse input terminal of the amplifier 4U2 through the feedback resistor 4R23; the 10 pins of the same input terminal of the amplifier 4U2 are used for measurement Analog signal port, the 10 pins of the same input end of the amplifier 4U2 are grounded through the resistor 4R37, the 9 pins of the reverse input end of the amplifier 4U2 are grounded through the resistor 4R26, the 8 pins of the output end of the amplifier 4U2 are connected to the reverse input of the amplifier 4U2 through the feedback resistor 4R25 Terminal 9 pins; the 12 pins of the same-directional input end of the amplifier 4U2 receive the analog signal port for measurement, the 12 pins of the same-directional input end of the amplifier 4U2 are grounded through the resistor 4R38, and the 13 pins of the reverse input end of the amplifier 4U2 are grounded through the resistor 4R28, The output terminal 14 of the amplifier 4U2 is connected to the reverse input terminal 13 of the amplifier 4U2 via the feedback resistor 4R27; the 4 pin of the amplifier 4U2 is connected to the output terminal +5V, and the capacitor 4C12 is connected to the 4 pin of the amplifier 4U2 and the ground between; The output terminals 1 pins, 7 pins, 8 pins and 14 pins of the amplifier 4U1 are respectively connected to the 34 pins, 35 pins, 42 pins and 43 pins of the embedded chip 1U1 through the exclusion 4RP511; the output terminals of the amplifier 4U2 Pin 1, pin 7, pin 8, and pin 14 are respectively connected to pin 46, pin 47, pin 26, and pin 27 of the embedded chip 1U1 through the exclusion 4RP512; The second AI isolation circuit has the same structure as the first AI isolation circuit, consisting of amplifier 2-4U1, amplifier 2-4U2, resistors 2-4R11 to 2-4R18, resistor 2-4R21 to resistor 2-4R28, resistor 2-4R31 to resistor 2-4R38, capacitor 2-4C11 to 2-4C12, and exclusion 2-4RP511 to 2-4RP512; the output pins 1, 7, 8, and 14 of the amplifier 2-4U1 are respectively subjected to exclusion 2-4RP511 is connected to the 28 pins, 29 pins, 44 pins, and 45 pins of the embedded chip 1U1; the 1 pins, 7 pins, 8 pins, and 14 pins of the output terminals of the amplifier 2-4U2 are respectively blocked by 2-4RP512 Connect the 18 pins, 19 pins, 20 pins, and 21 pins of the embedded chip 1U1; the 3 pins, 5 pins, 10 pins, and 12 pins of the same input terminals of the amplifiers 2-4U1 and 2-4U2 respectively receive the measured analog signals port; The resistor 5R4 of the AO isolation card circuit is connected in series with the resistor 5R11 and then connected between the input terminal 5 of the amplifier 5U1 and the ground, and the resistor 5R1 and the resistor 5R12 are connected in series and connected to the input terminal 10 of the amplifier 5U1 and the ground, the node of the resistor 5R4 and the resistor 5R11 is connected to pin 41 of the embedded chip 1U1, and the node of the resistor 5R1 and resistor 5R12 is connected to the pin 40 of the embedded chip 1U1; the node of the amplifier 5U1 Pin 1 and pin 2 are connected to pin 5 of the amplifier 5U1 via resistor 5R2, pin 7 of the amplifier 5U1 is connected to the base of the triode 5Q2, pin 6 of the amplifier 5U1 is connected to the emitter of the triode 5Q2 via resistor 5R5, and resistor 5R7 Connected between pin 6 of the amplifier 5U1 and the ground, capacitor 5C1 is connected between pin 7 of the amplifier 5U1 and the ground; the collector of the triode 5Q2 is connected to the output terminal +12V, and its emitter is connected through the resistor 5R10 Pin 3 of the amplifier 5U1; pin 13 of the amplifier 5U1 is connected to pin 14 of the amplifier 5U1 and connected to pin 10 of the amplifier 5U1 through a resistor 5R3; pin 8 of the amplifier 5U1 is connected to the base of the triode 5Q6; pin 9 of the amplifier 5U1 is connected to the base of the transistor 5Q6 The resistor 5R6 is connected to the emitter of the triode 5Q1, the resistor 5R8 is connected between pin 9 of the amplifier 5U1 and the ground, and the capacitor 5C2 is connected between the pin 8 of the amplifier 5U1 and the ground; the collector of the triode 5Q1 is connected to the output terminal + 12V, its emitter is connected to pin 12 of amplifier 5U1 through resistor 5R9; Pin 1 and pin 4 of the chip 6U1 of the parallel-to-serial conversion input circuit are respectively connected to intrusion detection and interrupt input signals through resistor 6R702 and resistor 6R701, and pin 6 and pin 8 of the chip 6U1 are connected to the input signal through resistor 6R703 and resistor 6R704 respectively. Connect the output terminal +3.3V, the 5 pin of the chip 6U1 is grounded through the resistor 6R708, the capacitor 6C701 is connected in parallel with the resistor 6R708, the 7 pin of the chip 6U1 is grounded through the resistor 6R707, the capacitor 6C702 is connected in parallel with the resistor 6R702, the triode The base of 6Q701 is connected to pin 5 of chip 6U1, the emitter of triode 6Q701 is grounded, the collector of triode 6Q701 is connected to the output terminal +3.3V through resistor 6R706, the base of triode 6Q702 is connected to pin 7 of chip 6U1, and the triode The emitter of 6Q702 is grounded, the collector of triode 6Q702 is connected to the output terminal +3.3V through resistor 6R705, and the collector of triode 6Q702 is connected to pin 7 of the embedded chip 1U1; the chip 6U5 to chip 6U6, chip 6UA Both pins 2 are connected to pin 133 of the embedded chip 1U1, the collector of the triode 6Q602 is connected to the output terminal +3.3V through a resistor 6R601, the base of the triode 6Q602 is connected to pin 6 of the chip 6U7 through a resistor 6R602, and the triode 6Q602 The emitter of the chip is grounded, the resistor 6R603 and the capacitor 6C601 are connected in parallel and then connected between the base of the triode 6Q602 and the ground; the chips 6U5 to 6U6, and pin 1 of the chip 6UA are all connected to the collector of the triode 6Q602, and pin 3 of the chip 6U6 Connect the collector of the triode 6Q701, the 14 pins of the chip 6U6 are connected to the 5 pins of the chip 12U4; the 4 pins of the chip 6U7 are connected to the 134 pins of the embedded chip 1U1, and the 1 pins of the chip 6UB are connected to the chip 3 pins of 6U6, 2 pins of the chip 6UB are connected to 4 pins of the chip 6U6, 4 pins and 5 pins of the chip 6UB are respectively connected to 13 pins and 12 pins of the chip 6U5, and 11 pins of the chip 6UB are connected to the Pin 54 of the embedded chip 1U1, pin 3 of the chip 6UB is connected to pin 13 of the chip 6UB, pin 6 of the chip 6UB is connected to pin 12 of the chip 6UB; The 11 pins of the chip 7U1 to the chip 7U5 of the serial-to-parallel conversion output circuit are all connected to the 133 pins of the embedded chip 1U1; the 14 pins of the chip 7U1 are connected to the 135 pins of the embedded chip 1U1, and the 15 pins of the chip 7U1 The pins, 2 pins, 4 pins, and 6 pins are respectively connected to the 3 pins of the chip 10U6 of the first serial port isolation card circuit, the 3 pins of the chip 2-10U6 of the second serial port isolation card circuit, and the chip 3-10U6 of the third serial port isolation card circuit. Pin 3 of 10U6, pin 3 of chip 4-10U6 of the fourth serial port isolation card circuit; The 14 pins of the chip 7U5 are connected to the 9 pins of the chip 7U2, the 14 pins of the chip 7U3 are connected to the 9 pins of the chip 7U5; the 14 pins of the chip 7U4 are connected to the 9 pins of the chip 7U3; The 15 pins of the chip 7U8 are connected to the 15 pins of the chip 7U5, the 1-3 pins of the chip 7U8 are respectively connected to the 110 pins, 55 pins, and 126 pins of the embedded chip 1U1, and the 4 pins of the chip 7U8 are connected to the chips 7U1 to 7U5. 12 pins, 6 pins of chip 6U7; Pins 6-7 of the chip 7U9 are connected to pins 14-13 of the chip 7U8, pins 11-12 and 14 of the chip 7U9 are connected to pins 75, 76, and 74 of the embedded chip 1U1, and the chip 7U9 15 pins, 1 pin - 3 pins of the chip 10U5 of the first serial port isolation card circuit, 1 pin of the chip 2-10U5 of the second serial port isolation card circuit, and 3-10U5 of the chip 3-10U5 of the third serial port isolation card circuit Pin 1, pin 1 of chip 4-10U5 of the fourth serial port isolation card circuit; pin 3 of chip 7U5 is connected to pin 1 of the optocoupler 2U5 through resistor 2R501, pin 4 of chip 7U9 is connected to pin 3 of optocoupler 2U5 through resistor 2R502 foot. 5. A data interaction intelligent host terminal according to claim 4, characterized in that the PWM counter isolation board circuit consists of chips 8U4-8U7, optocouplers 8U2-8U3, transistors 8Q201-8Q204, transistors 8Q301-8Q308, row Resistance 8RP101, exclusion 8RP201, exclusion 8RP202, light emitting diode 8D301-8D304, light emitting diode 8D201-8D204 and resistance 8R301-8R304; the model of the chip 8U4-8U7 is analog electronic switch BL1551, and the model of optocoupler 8U3 is TLP521 -4, the model of the optocoupler 8U4 is TLP281-4; the input pins 4 of the chip 8U4-8U7 are respectively connected to the 96 pins, 97 pins, 100 pins, and 136 pins of the embedded chip 1U1; the chip 8U4- Input pin 6 of 8U7 is respectively connected to pins 2-5 of 7U2 in the serial-to-parallel conversion output circuit, and output pin 3 of chips 8U4-8U7 is respectively connected to optocoupler 8U3 through exclusion 8RP101 and light-emitting diode 8D301-8D304 The input pins 1, 3, 5, and 7 are grounded, and the 2, 4, 6, and 8 pins of the optocoupler 8U3 are grounded; The 9-16 pins of the optocoupler 8U3 are connected to four pulse output circuits with the same structure; the first pulse output circuit is composed of transistor 8Q301, transistor 8Q305 and resistor 8R301; the 16 pins of the optocoupler 8U3 are connected to the pulse signal The corresponding port of the port, the 16-pin of the optocoupler 8U3 is connected to the collector of the transistor 8Q301, the emitter of the transistor 8Q301 is connected to one end of the resistor 8R301, the emitter of the transistor 8Q305 is connected to the 15-pin of the optocoupler 8U3, and the collector of the transistor 8Q305 is connected to the transistor 8Q301 The base of transistor 8Q305 is connected to the other end of resistor 8R301; the second pulse output circuit is composed of transistor 8Q302, transistor 8Q306 and resistor 8R302; the collector of transistor 8Q302 is connected to pin 14 of optocoupler 8U3, Pin 14 of optocoupler 8U3 is connected to the corresponding port of the pulse signal port, and the emitter of transistor 8Q306 is connected to pin 13 of optocoupler 8U3; the third pulse output circuit is composed of transistor 8Q303, transistor 8Q307 and resistor 8R303; the transistor 8Q303 The collector is connected to the 12 pins of the optocoupler 8U3, the 12 pins of the optocoupler 8U3 are connected to the corresponding port of the pulse signal port, the emitter of the transistor 8Q307 is connected to the 11 pins of the optocoupler 8U3; the fourth pulse output circuit is composed of transistors 8Q304, Composed of transistor 8Q308 and resistor 8R304; the collector of the transistor 8Q304 is connected to pin 10 of the optocoupler 8U3, pin 10 of the optocoupler 8U3 is connected to the corresponding port of the pulse signal port, and the emitter of the transistor 8Q308 is connected to pin 9 of the optocoupler 8U3; The PWM counter isolation board circuit pulse input circuit composed of the optocoupler 8U2, digital transistors 8Q201-8Q204, exclusion 8RP201, exclusion 8RP202, and light-emitting diodes 8D201-8D204; the anodes of the light-emitting diodes 8D201-8D204 are respectively transistors 8Q301-8Q304 The emitters of the light-emitting diodes 8D201-8D204 are respectively connected to pins 1, 3, 5, and 7 of the optocoupler 8U2, and pins 2, 4, 6, and 8 of the optocoupler 8U2 are respectively connected to The resistance exclusion 8RP201 is connected to the 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 8U3, and the 16 pins, 14 pins, 12 pins, and 10 pins of the optocoupler 8U2 are respectively connected to the bases of the transistors 8Q201-8Q204. The 15 pins, 13 pins, 11 pins and 9 pins of the coupling 8U2 are all grounded; the collectors of the transistors 8Q201-8Q204 are respectively grounded through the resistance 8RP202, and the collectors of the transistors 8Q201-8Q204 are respectively connected to the 1 pin of the chip 8U4, the chip 8U5 pin 1 of the chip 8U6, pin 1 of the chip 8U7, and the emitters of the transistors 8Q201-8Q204 are connected to the output terminal +3.3V; The human-computer interaction circuit includes a first human-computer interaction circuit and a second human-computer interaction circuit; The first human-computer interaction circuit is composed of resistors 9R1-9R8 and light-emitting diodes 9D1-9D8; the resistor 9R1 is connected in series with the light-emitting diode 9D1 and then connected to pin 3 of the chip 7U4 in the serial-to-parallel conversion output circuit and ground The resistor 9R2 is connected in series with the light emitting diode 9D2 and then connected between pin 2 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground; the resistor 9R3 is connected in series with the light emitting diode 9D3 and then connected to the Between pin 1 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; the resistor 9R4 is connected in series with the light-emitting diode 9D4 and connected between pin 15 of the chip 7U4 in the serial-parallel conversion output circuit and the ground; The resistor 9R5 is connected in series with the light emitting diode 9D5 and then connected between pin 5 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground; the resistor 9R6 is connected in series with the light-emitting diode 9D6 and then connected to the serial-parallel conversion output Between pin 4 of the chip 7U4 in the circuit and the ground; the resistor 9R7 is connected in series with the light-emitting diode 9D7 and connected between pin 7 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground; the resistor 9R8 and the ground The light-emitting diode 9D8 is connected in series between pin 6 of the chip 7U4 in the serial-to-parallel conversion output circuit and the ground; The second human-computer interaction circuit is composed of resistors 9R11-9R18, switches 9S1-9S8 and capacitors 9C1-9C8; the resistor 9R11 is connected in series with the switch 9S1 and connected between the output terminal +3.3V and ground, and the The node of the resistor 9R11 and the switch 9S1 is connected to pin 11 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R12 is connected in series with the switch 9S2 between the output terminal +3.3V and ground, and the resistor 9R12 The node connected with the switch 9S2 is connected to pin 12 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R13 is connected in series with the switch 9S3 and then connected between the output terminal +3.3V and ground, and the resistor 9R13 is connected to the switch The node of 9S3 is connected to pin 13 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R14 is connected in series with the switch 9S4 and then connected between the output terminal +3.3V and ground, and the resistor 9R14 is connected to the switch 9S4 The node is connected to pin 14 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R15 is connected in series with the switch 9S5 between the output terminal +3.3V and ground, and the node of the resistor 9R15 is connected to the switch 9S5 Pin 3 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R16 is connected in series with the switch 9S6 between the output terminal +3.3V and ground, and the node of the resistor 9R16 and the switch 9S6 is connected to the Pin 4 of the chip 6UA in the parallel-to-serial conversion input circuit; the resistor 9R17 is connected in series with the switch 9S7 between the output terminal +3.3V and ground, and the node of the resistor 9R17 and the switch 9S7 is connected to the parallel string Convert pin 5 of the chip 6UA in the input circuit; the resistor 9R18 is connected in series with the switch 9S8 between the output terminal +3.3V and ground, and the node of the resistor 9R18 and the switch 9S8 is connected to the parallel-serial conversion input The 6 pins of the chip 6UA in the circuit; the capacitors 9C1-9C8 are respectively connected in parallel with the switches 9S1-9S8; The integrated communication card circuit includes a serial port circuit and a CAN bus circuit; the serial port circuit is made up of a serial port chip 11U11, resistors 11R1-11R2 and capacitors 11C1-11C5; the model of the serial port chip 11U11 is MAX232, and the serial port chip 11U11 The 11 pins and 12 pins of the embedded chip 1U1 are respectively connected to the 113 pins and 116 pins of the embedded chip 1U1, the 11 pins and 12 pins of the serial port chip 11U11 are respectively connected to the corresponding external serial port signals, and the resistor 11R1 is connected to the 10 pins and 12 pins of the serial port chip 11U11. Between pins, resistor 11R2 is connected between pin 9 and pin 11 of serial chip 11U11, capacitor 11C3 is connected between pin 4 and pin 5 of serial chip 11U11, capacitor 11C5 is connected between pin 1 and pin 3 of serial chip 11U11 In between, capacitor 11C1 is connected between pin 16 of serial port chip 11U11 and the ground, pin 16 of serial port chip 11U11 is connected to the output +5V, capacitor 11C2 is connected between pin 2 of serial chip 11U11 and ground, capacitor 11C4 is connected to Between pin 6 of serial port chip 11U11 and ground; Described CAN bus circuit is made up of isolating chip 11U21 and capacitor hair 11C6-11C7; The model of described isolating chip 11U21 is ISO1050; 1 pin of described isolating chip 11U21 is connected to described output +5V, and its 2 pins are connected to described Pin 140 of the embedded chip 1U1, pin 3 of the isolation chip 11U21 are connected to pin 139 of the embedded chip 1U1, pins 4 and 5 of the isolation chip 11U21 are grounded, pins 6 and 7 of the isolation chip 11U21 are CAN control bus At the output end, pin 8 of the isolation chip 11U21 is connected to the output +5V, capacitor 11C6 is connected between pin 1 of the isolation chip 11U21 and the ground, and capacitor 11C7 is connected between pin 8 of the isolation chip 11U21 and the ground. 6. An assembled data interactive intelligent terminal system, characterized in that: it includes a data interactive intelligent host terminal, a data bus, the first slave terminal to the Nth slave terminal, wherein N is an integer greater than 1; the first The structure from the slave terminal to the Nth slave terminal is the same, and the expansion form of the first slave terminal to the Nth slave terminal is a cascading type; the data interaction intelligent host terminal passes through the first slave terminal, the 2 Slave terminals, ..., the N-1th slave terminal are connected to the Nth slave terminal; the data interaction intelligent master terminal, the first slave terminal to the Nth slave terminal are respectively connected to the data bus. 7. An assembled data interactive intelligent terminal system according to claim 6, wherein the data bus includes the first data bus DWKZ0 to the eighth data bus DWKZ7, the ninth data bus WKWRZ, the tenth data bus WKOEZ, data bus power wire and data bus ground wire; data bus power wire is connected to +5V power supply, data bus ground wire is grounded; The first slave terminal includes a slave core control unit, a slave isolation card, a slave power management unit, a first bus controller and a first beacon relay slave module circuit; The slave core control unit has the same structure as the core control unit of the data interaction intelligent host terminal; the slave power management unit has the same structure as the data interaction intelligent host terminal power management unit; The slave isolation card, the first bus controller and the first Beacon relay slave module circuit are respectively connected to the corresponding ports of the slave core control unit; The external power supply supplies power to the core control unit of the slave, the isolation card of the slave, the first bus controller and the first beacon relay slave module circuit through the slave power management unit; The first bus controller is composed of a chip 13U7 and a resistor 13R1; the model of the chip 13U7 is 74HC245, and pin 1 of the chip 13U7 is connected to the ninth data bus WKWRZ of the data bus; pins 2-9 of the chip 13U7 are respectively Connect the 93 pins, 10 pins to 15 pins and 132 pins of the embedded chip 1U1; the 10 pins of the chip 13U7 are grounded; the 18 pins to the 11 pins of the chip 13U7 are respectively connected to the first data bus DWKZ0 to the eighth data bus of the data bus On line DWKZ7; pin 20 of chip 13U7 is connected to +5V power supply; the resistor 13R1 is connected between pin 19 and pin 20 of chip 13U7; The first beacon relay module circuit consists of optocoupler 13U1, chip 13U2, chip 13U3, chip 13U4, constant current source 13D1-13D2, transistor 13Q01, potentiometer 13RJ01, resistor 13R11-13R13, resistor 13R21-13R25 and capacitor 13C11- 13C14; the model of the optocoupler 13U1 is TLP281-4, the model of the chip 13U2 is LM393, the model of the chip 13U3 is CN5710, the model of the chip 13U4 is 74HB74, the model of the constant current source 13D1-13D2 is S-102T, the triode The model of 13Q1 is 8550; pin 5 of the optocoupler 13U1 is the signal input terminal FHn-1 of the first beacon relay slave module circuit through the constant current source 13D2, and pin 7 of the optocoupler 13U1 is connected to the constant current source 13D1 through the potentiometer 13RJ01 The input terminal of the constant current source 13D1 is the clock input terminal CLK of the first beacon relay slave module circuit, and the clock input terminal CLK of the first beacon relay slave module circuit is connected to the clock output of the beacon relay master module circuit Port FHCLK; pin 1 of optocoupler 13U1 is connected to pin 5 of the chip 13U4 via resistor 13R13, pin 2 of optocoupler 13U1 is connected to pin 3, pin 4, pin 6 and pin 8 of optocoupler 13U1 are grounded, and pin 13U1 of optocoupler The 9 pins of the optocoupler 13U1 are grounded through the resistor 13R11, the 11 pins of the optocoupler 13U1 are grounded through the resistor 13R12, the 10 pins and 12 pins of the optocoupler 13U1 are connected to the output terminal +5V, and the capacitor 13C12 is connected between the 9 pins and the 12 pins of the optocoupler 13U1 Between, capacitor 13C11 is connected between pin 11 and pin 12 of optocoupler 13U1, pin 15 and pin 16 of optocoupler 13U1 are respectively connected to pin 13 and pin 14 of optocoupler 12U1 in the beacon relay main module circuit; The 15 pins of the coupling 13U1 are connected to the 10 pins of the chip 13U7, and the 16 pins of the optocoupler 13U1 are connected to the 19 pins of the chip 13U7; Pin 1, pin 4, and pin 14 of 13U4 are all connected to the output terminal +5V; the node of resistor 13R22 and resistor 13R21 is connected to pin 7 of chip 13U2, pin 7 of chip 13U2 is connected to pin 1 of chip 13U3, and the node of chip 13U2 is connected to pin 7 of chip 13U2. Pin 5 is grounded through resistor 13R24, pin 5 of chip 13U2 is connected to pin 13 of optocoupler 13U1, pin 2, pin 3 and pin 4 of chip 13U2 are grounded; pin 3 of chip 13U3 is grounded through resistor 13R25, pin 5 of chip 13U3 is grounded The pin is the clock output terminal CLK of the beacon relay slave module circuit, and the clock output terminal CLK of the beacon relay slave module circuit is connected to the input terminal of the constant current source 13D1; the base of the triode 13Q01 is connected to the 14 pin of the optocoupler 13U1, and the triode The emitter of 13Q01 is connected to the output terminal +5V, the collector of triode 13Q01 is the signal output terminal CFHn of the beacon relay slave module circuit, and the first beacon relay slave module circuit The signal output terminal CFHn of the circuit is connected to the signal input terminal of the beacon relay slave module circuit of the second slave terminal; Pins 18 to 11 of the chip 2U7 of the IO expansion bus communication circuit in the data interaction intelligent host terminal are respectively connected to the first data bus DWKZ0 to the eighth data bus DWKZ7 of the data bus; the IO in the data interaction intelligent host terminal Pin 8 and pin 11 of 2U6 of the expansion bus communication circuit are respectively connected to the ninth data bus WKWRZ and the tenth data bus WKOEZ of the data bus. 8. An assembled data interactive intelligent terminal system according to claim 7, characterized in that: the slave isolation card includes a slave AI isolation card circuit and a slave AO isolation card circuit, and the slave AI isolation The card circuit has the same structure as the AI isolation card circuit, and the slave AO isolation card circuit has the same structure as the AO isolation card circuit; the slave AI isolation card circuit is connected to the analog signal port to be measured, and the slave AI isolation card circuit The output of the slave machine is connected to the corresponding input terminal of the core control unit of the slave machine, the output terminal of the slave machine core control unit is connected to the corresponding input terminal of the AO isolation card circuit of the slave machine, and the output terminal of the AO isolation card circuit of the slave machine is connected to the analog control signal port ; The corresponding output terminals of the slave power management unit are respectively connected to the power input terminals of the slave AI isolation card circuit and the slave AO isolation card circuit. 9. An assembled data interactive intelligent terminal system according to claim 7, characterized in that: the slave isolation card includes a slave DIDO isolation card circuit, and the slave DIDO isolation card circuit and the DIDO isolation card circuit The structure is the same; the slave DIDO isolation card circuit is bidirectionally connected to the slave core control unit; the slave DIDO isolation card circuit is bidirectionally connected to the switch signal port; the corresponding output terminal of the slave power management unit is connected to the slave DIDO Isolate the power input terminal of the circuit of the card. 10. The method for communicating using the assembled data interactive intelligent terminal system according to claim 7, characterized in that the communication between the beacon relay master module and the beacon relay slave module is carried out, and the specific steps are as follows: (1) Initialize the core processing unit so that the pin of the selection signal input terminal FH of the beacon relay main module is at a low level, and the pin of the clock signal input terminal CLK of the beacon relay main module is at a high level; (2) The embedded chip 1U1 sends a selection signal to the pin of the selection signal input terminal FH of the beacon relay main module, that is, sends a high level; (3) The embedded chip 1U1 sends a clock signal of one cycle to the pin of the clock signal input terminal CLK of the beacon relay main module, that is, high level-low level-high level; (4) The embedded chip 1U1 sends a clear signal to the pin of the selection signal input terminal FH of the beacon relay main module, that is, low level, and clears the slave address i; (5) The embedded chip 1U1 sends a clock signal of one cycle to the pin of the clock signal input terminal CLK of the beacon relay master module, and increments the slave address i by 1; (6) The embedded chip 1U1 detects whether the slave address i is greater than the limit number m of the slave, if yes, then executes step (7), otherwise executes step (8); (7) When the beacon relay slave module is abnormal, output an abnormal notification; (8) The embedded chip 1U1 judges whether the termination signal is received, and the pin of the feedback signal output terminal FHFK of the beacon relay main module sends the selection signal to a low level. If not received, execute step (9), otherwise execute step (10); (9) The embedded chip 1U1 outputs the read and write data notification, and then jumps to step (5); (10) The embedded chip 1U1 judges whether the slave address i exceeds the number n of data interaction intelligent slave terminals detected by the beacon relay master module, if yes, jump to step (2), otherwise execute step (11) step; (11) Embedded chip 1U1 outputs the notification that the slave terminal goes online and offline; (12) Reset the number n of data interaction intelligent slave terminals to i-1, and jump to step (2); In the above steps, i is the slave address; n is the number of slave terminals; m is the limit number of slave terminals; wherein, the value range of i is 1~100, the value range of n is 1~100, and the value of m is The value range is 1~100.