CN108431788B - A single board, electronic equipment and method for gating - Google Patents

Abstract

A single board, electronic equipment and a gating method are provided, wherein the single board comprises: a joint test action group JTAG module (11), a storage module (14), a channel selection module (12) and a storage interface (13); the channel selection module (12) is electrically connected with the JTAG module (11), the channel selection module (12) is electrically connected with the storage interface (13), the storage module (14), and the channel selection module (12) is electrically connected with the storage module (14); the channel selection module (12) is used for communicating the storage interface (13) with the JTAG module (11) when the JTAG test equipment is electrically connected with the storage interface (13); and communicating the storage interface (13) with the storage module (14) when the storage device is electrically connected with the storage interface (13). The efficiency of later JTAG test, the integration level and the aesthetic property of electronic equipment can be improved.

Description

A single board, electronic equipment and method for gating

technical field

The invention relates to the field of electronic technology, and in particular, to a single board, an electronic device and a gating method.

Background technique

At present, electronic equipment is becoming more and more intelligent, miniaturized and highly integrated, and there are more and more functional interfaces inside electronic equipment. The functional interface of the internal functional circuit is shown in Figure 1-1. The joint test working group (JTAG, Joint TestAction Group) circuit in the main control chip and the internal circuit of the Secure Digital Memory Card (SD, Secure Digital Memory Card) are independent, respectively. JTAG circuit and SD internal circuit lead to independent JTAG interface and SD interface. Testers can connect external JTAG test equipment and SD device through these two exported JTAG interface and SD interface, and perform corresponding test, read/write and so on. Because the circuit boards of current electronic equipment are generally small and the external interface design is compact, in order to improve portability and aesthetics, the internal electronic equipment for testing, debugging and other functional interfaces are generally not externally introduced, so that in the later period of electronic equipment It brings inconvenience to the fault diagnosis and debugging. During the fault diagnosis or debugging, it is necessary to disassemble the casing of the electronic equipment and fly wires on the internal circuit board of the electronic equipment. etc. cause damage.

In the existing mechanism, other functions are generally realized by multiplexing the existing interface externally introduced by the electronic device, so that the function of the electronic device can also be increased and the integration degree of the electronic device can be improved without adding an additional interface. As shown in Figure 1-2, the input/output (I/O, Input/Output) interface of the main control chip is multiplexed inside the main control chip, and the function of the JTAG interface is realized by multiplexing the SD interface. It is necessary to use a special adapter board to connect the SD interface and the JTAG test equipment. The tester sends specific instructions to the main control chip through the debugging software in the JTAG test equipment, so that the main control chip can recognize the JTAG test equipment, so as to achieve Switch between JTAG function and SD function. Since the SD function and JTAG function are realized by multiplexing the I/O interface of the main control chip, the function switching can only be completed when the main control chip is working normally, and a special adapter board and special debugging software are required to realize SD. function and JTAG function switching. And when the main control chip cannot work normally, the JTAG test cannot be performed, that is, the JTAG test cannot be performed for the single chip of the JTAG circuit.

SUMMARY OF THE INVENTION

The present application provides a single board, an electronic device and a JTAG test method, which can solve the problem of low JTAG test efficiency in the prior art.

A first aspect of the present application provides a veneer, the veneer comprising:

Joint test action group JTAG module, storage module, channel selection module and storage interface;

The channel selection module is electrically connected to the JTAG module, the channel selection module is electrically connected to the storage interface, and the channel selection module is electrically connected to the storage module;

The channel selection module is used for connecting the storage interface and the JTAG module when the JTAG test device is electrically connected to the storage interface;

and when the storage device is electrically connected to the storage interface, the storage interface and the storage module are communicated. Through the channel selection module multiplexing the storage interface, switching between the JTAG mode and the storage mode is realized. The storage interface is an SD interface.

In some possible designs, the channel selection module is further configured to, when connecting the storage interface and the JTAG module, that is, when the JTAG testing device and the JTAG module form a channel, select a channel from the JTAG testing device. The JTAG test signal is input to the JTAG module;

The JTAG module is configured to execute the test item corresponding to the JTAG test signal according to the JTAG test signal received from the channel selection module, and transmit the first test data obtained by the test to the channel selection module;

The channel selection module is further configured to transmit the first test data from the JTAG module to the JTAG test device through the storage interface. After the multiplexing storage interface of the channel selection module is connected to the JTAG module on the single board, the JTAG test function and the output of test data are realized.

In some possible designs, the channel selection module is further configured to select the storage from the storage device when the storage interface and the storage module are connected, that is, the storage device and the storage module form a channel. the test signal is output to the storage module;

The storage module is configured to execute the test item corresponding to the storage test signal according to the storage test signal received from the channel selection module, and output the second test data obtained by testing to the channel selection module;

The channel selection module is further configured to transmit the second test data from the storage module to the storage device through the storage interface. After the storage module connected to the single board is selected by the channel selection module, functions such as storage, data reading, input and output are realized.

In some possible designs, the channel selection module includes a first gate terminal, a second gate terminal, a common terminal and a gate control pin, and the first gate terminal is electrically connected to the interface terminal of the JTAG module. connected, the second gate terminal is electrically connected to the interface terminal of the storage module, and the common terminal is electrically connected to the storage interface. Optionally, the channel selection module includes a multiplexer switch, wherein the multiplexer switch is an analog switch that implements a gating function, and may include a multiplexer, a multiplexer, a multiplex analog switch, and a data selection switch. converters, multiplexing analog converters, multiplexing switches, multiplexing switches, multiplexing switches, etc.

In some possible designs, the channel selection module further includes a gate control pin, and the gate control pin is used to control the connection between the common terminal and the first gate terminal, and to control the common terminal communicated with the second gate terminal.

In some possible designs, the interface end of the JTAG module includes: a test mode selection pin, a test clock pin, a test data input pin, and a test data output pin, and optionally, a test reset pin foot;

The first gate terminal includes: a first channel pin corresponding to the test mode selection pin, a second channel pin corresponding to the test clock pin, and a test data input pin corresponding to the A third channel pin and a fourth channel pin corresponding to the test data output pin, correspondingly, may also include a fifth channel pin corresponding to the test reset pin;

When the signal input to the gating control pin is at the first level, the first channel pin, the second channel pin, the third channel pin and the third channel pin in the channel selection module. Four-channel pin gating, optionally, when the gating control pin includes a fifth channel pin, the fifth channel pin is also gating. Signal transmission is realized by setting the gate control pin in the channel selection module to gate the pin electrically connected to the JTAG module.

In some possible designs, the interface end of the memory module includes: an instruction pin, a clock pin, a first test data pin, a second test data pin, a third test data pin, and a fourth test data pin foot;

The second gate terminal includes: a sixth channel pin corresponding to the command pin, a seventh channel pin corresponding to the clock pin, and an eighth channel pin corresponding to the first test data pin. A channel pin, a ninth channel pin corresponding to the second test data pin, a tenth channel pin corresponding to the third test data pin, and a Eleventh channel pin;

When the signal input to the gating control pin is the second level, the sixth channel pin, the seventh channel pin, the eighth channel pin, the The nine-channel pin, the tenth-channel pin, and the eleventh-channel pin are gated.

In some possible designs, the storage interface includes a storage device detection pin, and the storage device detection pin is electrically connected to the gating control pin;

The storage device detection pin is used to trigger the signal input to the gating control pin to be the first level when the JTAG test device is electrically connected to the storage interface; when the storage device is connected to the storage interface When electrically connected, the signal that triggers the input to the gate control pin is the second level. The storage device detection pin on the storage module triggers the corresponding level signal to the gating control pin, so that the gating control pin selects the corresponding pin of the device inserted into the storage interface according to the level of the signal.

A second aspect of the present invention provides an electronic device, where the electronic device includes the single board described in any one of the first aspect and the possible designs of the first aspect.

A third aspect of the present invention provides a gating method, the method is applied to a single board, and the method includes:

When the joint test action group JTAG test equipment is electrically connected to the storage interface in the single board, the channel selection module in the single board communicates the storage interface and the JTAG module in the single board;

When the storage device is electrically connected to the storage interface in the single board, the channel selection module communicates the storage interface with the storage module in the single board.

In a possible design, the channel selection module includes a first gate terminal, a second gate terminal, a common terminal and a gate control pin, the first gate terminal is electrically connected to the interface terminal of the JTAG module, so The second gate terminal is electrically connected with the interface terminal of the storage module, and the common terminal is electrically connected with the storage interface in the single board; the storage interface includes a storage device detection pin, and the storage device detection lead is electrically connected. The pin is electrically connected to the gating control pin;

When the joint test action group JTAG test device is electrically connected to the storage interface in the single board, the channel selection module in the single board communicates the storage interface with the JTAG module in the single board. The module includes:

When the JTAG test device is electrically connected to the storage interface in the single board, the signal input from the storage device detection pin to the gating control pin in the channel selection module is the first level, so Described gating control pin gating described first gating terminal, so that described JTAG test equipment and described JTAG module communication connection;

When the storage device is electrically connected to the storage interface in the single board, the channel selection module communicates the storage interface with the storage module in the single board, including:

When the storage device is electrically connected to the storage interface in the single board, the signal input from the storage device detection pin to the gating control pin in the channel selection module is the second level, and the The gating control pin selects the second gating terminal to connect the storage device and the storage module in communication; the second level is different from the first level.

In the embodiment of the present invention, by using the channel selection module to electrically connect the JTAG module and the storage interface, when the JTAG test device is electrically connected to the storage interface, a channel is formed with the JTAG module, thereby realizing multiplexing of the storage interface for JTAG For testing, it is possible to reuse the storage interface for JTAG testing without the need for external adapter boards, special debugging software, disassemble the machine, and reduce the integration of the single board, effectively reducing JTAG testing operations and test tools, and improving the later stage. Efficiency of JTAG testing, integration and aesthetics of electronic devices.

Description of drawings

Figure 1-1 is a schematic structural diagram of a JTAG test system in the existing mechanism;

Figure 1-2 is another structural schematic diagram of the JTAG test system in the existing mechanism;

2 is a schematic structural diagram of a single board in an embodiment of the present invention;

FIG. 2-1 is a schematic structural diagram of a JTAG test system in an embodiment of the present invention;

3 is a schematic diagram of a logic circuit of a single board in an embodiment of the present invention;

4 is a schematic diagram of a circuit principle of a single board in an embodiment of the present invention;

5 is a schematic structural diagram of an electronic device in an embodiment of the present invention;

FIG. 6 is a schematic flowchart of a method for JTAG testing in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. The embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative efforts, fall within the protection scope of the present invention.

The terms "first", "second" and the like in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It is to be understood that data so used may be interchanged under appropriate circumstances so that the embodiments described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or modules is not necessarily limited to those expressly listed Those steps or modules, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products or devices, the division of modules presented herein is only a logical division, In practical applications, there may be other divisions in implementation, for example, multiple modules may be combined or integrated in another system, or some features may be ignored, or not implemented, in addition, the coupling shown or discussed with each other Or direct coupling or communication connection may be through some interfaces, and indirect coupling or communication connection between modules may be electrical or other similar forms, which are not limited herein. In addition, the modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may not be divided into multiple circuit modules, and some of them or sub-modules may be selected according to actual needs. All modules are used to achieve the purpose of the embodiments of the present invention.

The embodiments of the present invention provide a single board, an electronic device and a JTAG test method, which are used in the field of electronic technology and can improve the JTAG test efficiency. The terminology in this article is explained in detail below.

The JTAG module herein may be referred to as a JTAG circuit, and the storage module may be referred to as an SD module or an SD circuit or a memory chip, or the like. As shown in Figure 3, the JTAG module is provided with a JTAG interface that is electrically connected to the channel selection module. Generally, the JTAG interface includes 4 pins: Test Mode Select (TMS, Test Module Select), Test Clock (TCK, Test Clock), Test data input (TDI, Test Data Input), test data output (TDO, Test Data Output), and may also include test reset (TRST, Test Reset). The SD module is provided with an SD interface electrically connected to the channel selection module. The SD interface includes 6 pins: command (CMD, Command), clock (CLK, Clock), data (DATA0, DATA1, DATA2 and DATA3). Correspondingly, the channel selection module is provided with 5 channel pins corresponding to the 5 pins of the JTAG interface, and 6 channel pins corresponding to the 6 pins of the SD interface.

Chips with a JTAG interface include a microprocessor (MPU, Microprocessor Unit), a microcontroller (MCU, Microprogrammed Control Unit), a central processing unit (CPU, Central Processing Unit), a digital signal processor (DSP, Digital Signal Processor), Complex Programmable Logic Device (CPLD, Complex Programmable Logic Device), Field Programmable Gate Array (FPGA, Field Programmable Gate Array) or other chips that conform to the 1149.1 standard of the Institute of Electrical and Electronics Engineers (IEEE, Institute of Electrical and Electronics Engineers).

The JTAG tests in this article include JTAG debugging, JTAG boundary scan and JTAG vector emulation tests. JTAG test is mainly used to test the electrical characteristics and debugging of the chip, such as the fault detection of electronic equipment in the production process and the fault detection of electronic equipment for repair. For users, the electronic equipment only needs to lead out the storage interface, so that the user can pass the storage interface The functions of data reading, data editing, data input and data output are performed on the built-in storage module of the electronic device.

Among them, JTAG debugging refers to in-circuit programming (ISP, In-SystemProgrammable) for devices fixed on the circuit board, such as programming for cameras (Camera), flash memory (FLASH) and other devices.

JTAG boundary scan refers to hardware fault detection on the placement process and soldering status of components on the circuit board.

The JTAG vector simulation test refers to the test of each functional module in the main control chip and the observation and control of the working state of each functional module. For example, the single chip is tested through the input/output signals of the chip.

The electronic equipment in this paper mainly has at least one of the following characteristics: small size, no JTAG interface drawn out separately, electronic equipment that is not easy to disassemble, multiplexing of SD interface and JTAG interface, etc.

In the existing mechanism, under the premise of pursuing the miniaturization of electronic equipment, JTAG testing of electronic equipment requires a dedicated external adapter board or dedicated debugging software to reuse the existing SD interface, and when the main control chip fails, it cannot be used. Carry out JTAG test, in order to solve this technical problem, the present invention provides following scheme:

1. The channel selection module is used to connect the main control chip and storage interface inside the board.

The main control chip includes a JTAG module and a storage module, and the channel selection module is electrically connected to the JTAG module and the storage module, respectively.

2. When the JTAG test equipment is connected to the storage interface, the channel selection module is connected to the JTAG module in the main chip, so that the JTAG module, the channel selection module, the storage interface and the JTAG test equipment form a path, and it is not necessary to set the JTAG interface and the JTAG test equipment for the JTAG module. Under the premise of not disassembling the machine, the function of JTAG test can be realized by reusing the existing storage interface. In addition, the existing storage interface can be reused without the need of an external adapter board or special debugging software, which reduces the operation steps and test tools, and improves the integration degree of the electronic equipment.

2 and 2-1, a single board 1 is provided for the present invention, and the single board 1 includes:

Joint test action group JTAG module 11, channel selection module 12 and storage interface 13;

The channel selection module 12 is electrically connected to the JTAG module 11, and the channel selection module 12 is electrically connected to the storage interface 13;

The channel selection module 12 is used for connecting the storage interface and the JTAG module when the JTAG test device is electrically connected to the storage interface 13 , so that the JTAG test device and the JTAG module 11 form a channel. Optionally, since most electronic devices currently have a built-in storage circuit, a storage interface 13 is drawn out of the housing of the electronic device, so that the user can read/write the storage device connected to the storage interface 13 through the built-in storage circuit. In the case of multiplexing the existing storage interface to realize JTAG test in the above-mentioned FIG. 2 , when the JTAG test is not performed, the user can still normally use the above-mentioned storage interface 13 to perform memory-related operations through the built-in storage circuit of the electronic device. That is, the single board 1 further includes a storage module 14, and the channel selection module 12 is used to electrically connect a storage device to the storage module 14;

The channel selection module 12 is further configured to form a channel between the storage device and the storage module 14 when the storage device is electrically connected to the storage interface 13 . Through the channel selection module 12 multiplexing the storage interface 13, switching between the JTAG test mode and the storage mode is realized. The storage device may be a device for testing the storage module, or may be a memory with a single storage function, which is not specified in detail.

It can be understood that the above-mentioned storage interface 13 is used for the JTAG module 11 to communicate with the JTAG test device connected to the storage interface 13 , and the storage module 14 to communicate with the storage device connected to the storage interface 13 . . For example, the user can use the JTAG module 11 to perform functions such as JTAG testing on the JTAG test device connected to the storage interface 13 , and use the storage module 14 to read/write the storage device connected to the storage interface 13 , etc. operate. The above-mentioned storage interface is an existing storage interface, such as an SD interface, for realizing functions such as reading/writing of the storage device connected to the storage interface 13 by the user through the storage module 14 .

In the embodiment of the present invention, by using the channel selection module 12 to connect the JTAG module 11 and the storage interface 13, when the JTAG test device is electrically connected to the storage interface 13, a channel is formed with the JTAG module 11, thereby realizing multiplexing of the JTAG module 11. The storage interface 13 is used for JTAG testing, which realizes the multiplexing of the storage interface 13 for JTAG testing without the need for an external adapter board, special debugging software, disassembly, or lowering the integration of the board 1, effectively reducing JTAG testing operations and costs. Test equipment can also improve the efficiency of post-JTAG testing, the integration and aesthetics of electronic equipment.

Optionally, in some inventive embodiments, when a tester needs to perform a JTAG test on an electronic device in the later stage, the tester only needs to insert the JTAG test device into the storage interface 13, and then the storage interface 13 can be reused, and the storage interface 13 can be reused through the channel. The selection module 12 enables the JTAG test equipment to form a path with the JTAG module 11 in the single board, thereby enabling the JTAG test mode, and the tester can perform the JTAG test through the JTAG test equipment. After starting the JTAG test mode, the signal flow of each module of the electronic device is as follows:

The channel selection module 12 is also used to input the JTAG test signal from the JTAG test device when the storage interface 13 and the JTAG module 11 are connected, that is, when the JTAG test device and the JTAG module 11 form a channel the JTAG module 11;

The JTAG module 11 is configured to execute the test item corresponding to the JTAG test signal according to the JTAG test signal received from the channel selection module 12, and transmit the first test data obtained by the test to the channel selection module 12;

The channel selection module 12 is further configured to transmit the first test data from the JTAG module to the JTAG test device through the storage interface 13 . After the multiplexed storage interface of the channel selection module 12 is connected to the JTAG module 11 on the single board, the JTAG test function is realized. It can improve the efficiency of maintenance analysis; alternatively, by performing the JTAG vector simulation test on the important electronic devices on the board 1, the faulty chip can be determined according to the working state of the chip, and the efficiency of fault analysis can be improved; Multiple functional devices on the assembled single board 1 are simultaneously programmed online, and corresponding programs are written, thereby effectively improving the processing progress of the single board 1 .

Optionally, in some inventive embodiments, after the tester completes the JTAG test on the electronic device, the tester can also insert the storage device into the storage interface 13; The channel selection module 12 forms a channel with the storage module 13 in the single board, thereby enabling the storage mode or storage test mode, and the tester can read/write and test the connected storage device.

1. After starting the storage test mode, the signal flow of each module of the electronic device is as follows:

The channel selection module 12 is further configured to output the storage test signal from the storage device to the storage device when the storage interface 13 and the storage module 14 are connected, that is, the storage device and the storage module 14 form a channel. the storage module 14;

The storage module 14 is configured to execute the test item corresponding to the storage test signal according to the storage test signal received from the channel selection module 12, and output the second test data obtained by the test to the channel selection module 12;

The channel selection module 12 is further configured to transmit the second test data from the storage module 14 to the storage device through the storage interface 13 . After the channel selection module 12 selects the storage module 14 connected to the single board, the storage test is implemented.

2. After starting the storage mode, the signal flow of each module of the electronic device is as follows:

The channel selection module 12 is further configured to output the binary signal sent from the storage device to the storage device when the storage interface 13 and the storage module 14 are connected, that is, the storage device and the storage module 14 form a channel. the storage module 14;

The storage module 14 is configured to perform an operation of inputting/outputting data according to the binary signal received from the channel selection module 12. The specific process of inputting/outputting data is similar to the existing mechanism, which will not be repeated herein. When inputting data, the storage module 14 stores the data from the storage device; when outputting data, the output data of the storage module 14 will be input to the channel selection module 12;

The channel selection module 12 is further configured to transmit the output data from the storage module 14 to the storage device through the storage interface 13 . After the channel selection module 12 selects the storage module 14 connected to the single board, functions such as data reading, input, and output are realized.

Optionally, as shown in FIG. 2-1, the channel selection module 12 herein includes a first gate terminal 121, a second gate terminal 122 and a common terminal 123, and the first gate terminal 121 is connected to the JTAG terminal 121. The interface terminal of the module 11 is electrically connected, the second gate terminal 122 is electrically connected to the interface terminal of the storage module 14 , and the common terminal 123 is electrically connected to the storage interface 13 . The channel selection module 12 can be a multiplexer switch, and the multiplexer switch includes a gate terminal, a common terminal, etc. As shown in Figures 3 and 4, the first gate terminal includes NO1-NO6, and the second gate terminal includes NC1- NC6, the common terminal includes COM1-COM6, the first gate terminal of the multiplexer switch is electrically connected to the interface terminal of the JTAG module 11, and the second gate terminal of the multiplexer switch is electrically connected to the storage The interface end of the module 14 is electrically connected. Optionally, the multiplexer switch is an analog switch that implements the gating function, and may include multiplexers, multiplexers, multiplexed analog switches, data selectors, multiplexed analog converters, and multiplexed switches. , multi-channel switch, multi-channel switch, etc., for example, a multi-channel analog switch model TS3A27518E can be used.

For example, the internal logic circuit for connecting the JTAG module 11 and the storage interface 13 through the multiplexer switch, or connecting the storage module 14 and the storage interface 13 through the multiplexer switch is shown in FIG. 3 . The gating function, in this embodiment of the present invention, the multiplexing switch further includes a gating control pin, and the gating control pin is used to control the communication connection between the common terminal and the first gating terminal, that is, to connect the storage interface. 13 and the JTAG module 11 , and control the communication connection between the common terminal and the second gate terminal, that is, the storage interface 13 and the storage module 14 are connected. In practical application, for example, a multiplexer switch can be used to control the switching of the communication connection, that is, a gate control pin IN is set in the multiplexer switch, and the gate control pin IN is used to control the common terminal. Connecting with the first gate terminal, that is, the communication connection between the storage interface 13 and the JTAG module 11, and controlling the common terminal to communicate with the second gate terminal, that is, the communication between the storage interface 13 and the storage module 14 connect. That is, by setting the gating control pin IN in the multiplexing switch, when the JTAG testing device is electrically connected to the storage interface 13, the pin electrically connected to the JTAG module 11 can be gated, thereby realizing signal transmission.

Optionally, the gating control pin IN is used to realize the function of controlling the gating control pin of the multiplexer switch, so the gating control pin IN can also be used as a prohibition terminal, an enable terminal, a control terminal, and a control terminal. The signal terminal or the like can be replaced, as long as the gate of the pin can be controlled by inputting the high and low levels of the gate control pin IN, and the specific type is not limited.

Optionally, the number of the above gate control pins IN can be one or more, which can be selected according to the model of the chip and the design of the single board. For example, the same gate control pin IN can be used in the JTAG test. To switch between mode and storage mode, you can also use a gating control pin IN1 to control several pins on the multiplexer switch corresponding to the JTAG module or storage module, and use the gating control pin IN2 to control the multiplexing The gating of other pins on the switch corresponding to the JTAG module or the storage module. The number of the specific gating control pins is not limited in this paper. As shown in Figure 3 and Figure 4, for using IN1 and IN2 to control the gating control pins The logic circuit diagram, that is, the above gate control pin IN includes a first gate control pin IN1 and a second gate control pin IN2, wherein the first gate control pin IN1 is used to control the COM1 pin to connect all Described NC1 pin, or communicates NO1 pin, controls COM2 pin to communicate described NC2 pin, or communicates NO2 pin, COM3 pin communicates described NC3 pin, or communicates NO3 pin; The pin IN2 is used to control the COM4 pin to communicate with the NC4 pin, or to communicate with the NO4 pin, and to control the COM5 pin to communicate with the NC5 pin, or to communicate with the NO5 pin, and the COM6 pin to communicate with the NC6 pin.

The connection relationship between the devices in Figure 3 is described as follows:

1. For the JTAG module:

The interface end of the JTAG module 11 includes: a test mode selection TMS pin, a test clock TCK pin, a test data input TDI pin, a test data output TDO pin, and optionally, a test reset TRST pin;

The first gate terminal of the multiplex selection switch includes: the first channel NO1 pin corresponding to the test mode selection TMS pin, the second channel NO2 pin corresponding to the test clock TCK pin, and the The third channel NO3 pin corresponding to the described test data input TDI pin, the fourth channel NO4 pin corresponding to the described test data output TDO pin, optionally, can also be set to the test reset TRST pin Corresponding fifth channel NO5 pin.

Among them, the TMS pin is electrically connected to the NO1 pin of the first channel, the TCK pin is electrically connected to the NO2 pin of the second channel, the TDI pin is electrically connected to the NO3 pin of the third channel, and the TDO pin is electrically connected to the NO4 pin of the fourth channel. The pin is electrically connected, and the TRST pin is electrically connected with the NO5 pin of the fifth channel.

2. For the storage module:

The interface end of the described storage module 14 includes: the instruction CMD pin, the clock CLK pin, the first test data DATA0 pin, the second test data DATA1 pin, the third test data DATA2 pin and the fourth test data DATA3 pin. foot;

The second gate end of the multiplexer switch includes: the sixth channel NC1 pin corresponding to the CMD pin, the seventh channel NC2 pin corresponding to the clock pin, and the first test pin. The eighth channel NC3 pin corresponding to the data DATA0 pin, the ninth channel NC4 pin corresponding to the second test data DATA1 pin, and the tenth channel NC5 pin corresponding to the third test data DATA2 pin , and the eleventh channel NC6 pin corresponding to the fourth test data DATA3 pin.

Wherein, the CMD pin is electrically connected to the sixth channel NC1 pin, the CLK pin is electrically connected to the seventh channel NC2 pin, the first test data DATA0 pin is electrically connected to the eighth channel NC3 pin, and the second test data DATA1 The pin is electrically connected to the NC4 pin of the ninth channel, the third test data DATA2 pin is electrically connected to the tenth channel NC5 pin, and the fourth test data DATA3 pin is electrically connected to the tenth channel NC5 pin.

For example, for realizing that the gating control pin IN controls the gating of the pins in the multiplexer switch, the signal input to the gating control pin IN can be defined to realize control, specifically:

The storage interface 13 includes a storage device detection pin (SD-DET, Storage Card-Detector) 131, and the storage device detection pin 131 is electrically connected to the gating control pin IN, as shown in Figure 2-1 and Figure 2. 4 shown;

The storage device detection pin 131 is used to trigger the signal input to the gating control pin IN to be the first level when the JTAG test device is electrically connected to the storage interface 13; When the interface 13 is electrically connected, the signal input to the gate control pin IN is triggered to be at the second level. Through the storage device detection pin 131 on the storage interface 13, the corresponding high and low level signals are triggered to the gating control pin IN according to the type of the device connected to the storage interface 13, so that the gating control pin IN is high or low according to the level of the signal The strobe corresponds to the pin corresponding to the device inserted into the storage interface 13 . The second level is different from the first level. For example, the first level can be set to be a high level (H, High Level), and the second level can be set to a low level (L, Low Level). ), the specific value is not limited in this paper.

For example, when the storage device detection pin 131 triggers the signal input to the gate control pin IN to be high level H/low level L, as shown in FIG. 3 and Table 1, the gate There are mainly two situations in which the control pin IN selects the multiplexer switch as follows:

a. When the signal input to the gating control pin IN (including IN1 and IN2) is H, the first channel pin NO1, the second channel pin NO2, the The third channel pin NO3, the fourth channel pin NO4 and the fifth channel pin NO5 are gated;

b. When the signal input to the gating control pin IN (including IN1 and IN2) is L, the sixth channel pin NC1, the seventh channel pin NC2, the The eighth channel pin NC3, the ninth channel pin NC4, the tenth channel pin NC5, and the eleventh channel pin NC6 are gated.

Table 1

Referring to FIG. 5 , the present invention further provides an electronic device 2 , the electronic device 2 includes the single board 1 described in any one of the above-mentioned FIGS. 2-4 .

The structure of a single board 1 and an electronic device 2 is described in detail above. The following describes the gating of the channel of the single board 1 or the electronic device 2 by using a JTAG test equipment. Referring to FIG. 6, an embodiment of the present invention include:

101. When the joint test action group JTAG test equipment is electrically connected to the storage interface in the single board, the channel selection module in the single board communicates the storage interface and the JTAG module in the single board;

102. When the storage device is electrically connected to the storage interface in the single board, the channel selection module communicates the storage interface with the storage module in the single board.

Since the channel selection module includes a first gate terminal, a second gate terminal, a common terminal and a gate control pin, the first gate terminal is electrically connected to the interface terminal of the JTAG module, and the second gate terminal is electrically connected to the interface terminal of the JTAG module. The terminal is electrically connected to the interface terminal of the storage module, and the common terminal is electrically connected to the storage interface in the single board; the storage interface includes a storage device detection pin, and the storage device detection pin is connected to the selection pin. Electrically connected through the control pins. Then the specific situation of the channel gating module gating the JTAG module or the storage module is as follows:

1. When the JTAG test device is electrically connected to the storage interface in the single board, the signal of the storage device detection pin input to the gating control pin in the channel selection module is the first level, and the selection The first gate terminal is gated through the control pin, so that the JTAG test device is connected to the JTAG module in communication.

2. When the storage device is electrically connected to the storage interface in the single board, the signal of the storage device detection pin input to the gating control pin in the channel selection module is the second level, and the The gating control pin selects the second gating terminal, so as to connect the storage device and the storage module in communication.

Wherein, the second level is different from the first level, so that when the signal input to the gating control pin is at a different specific level, the corresponding gating terminal is selected to realize the multiplexing storage interface.

In the embodiment of the present invention, a JTAG test device is electrically connected to the storage interface, and the channel selection module communicates with the storage interface and the JTAG module, so that the JTAG test device is connected to the JTAG module through both the storage interface and the channel selection module. module for communication; when the storage device is electrically connected to the storage interface, the channel selection module communicates the storage interface and the storage module, so that no external adapter board, special debugging software, no disassembly and no lowering are required. On the premise of the integration of the single board, the existing storage interface is reused for JTAG testing and function switching, which effectively reduces JTAG testing operations and testing tools, and can also improve the efficiency of JTAG testing in the later stage, and the integration and aesthetics of electronic equipment.

The present invention also provides a computer storage medium, the medium stores a program, and when the program is executed, it includes some or all of the steps in the above-mentioned gating method.

The present invention also provides a computer storage medium, the medium stores a program, and when the program is executed, the program includes part or all of the steps in the above-mentioned single board or electronic device to perform a gating method.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which is not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: U disk, removable hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes.

A single board, an electronic device and a gating method provided by the present invention have been described in detail above. The principles and implementations of the present invention are described with specific examples in this paper. The descriptions of the above embodiments are only used to help Understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification does not It should be understood as a limitation of the present invention.

Claims (6)

1. A single board, comprising:

the joint test action group JTAG module, the storage module, the channel selection module and the storage interface;

the channel selection module is electrically connected with the JTAG module, the channel selection module is electrically connected with the storage interface, and the channel selection module is electrically connected with the storage module;

the channel selection module is used for communicating the storage interface and the JTAG module when the JTAG test equipment is electrically connected with the storage interface;

when the storage equipment is electrically connected with the storage interface, the storage interface is communicated with the storage module;

the channel selection module comprises a first gating end, a second gating end, a public end and a gating control pin, wherein the first gating end is electrically connected with an interface end of the JTAG module, the second gating end is electrically connected with an interface end of the storage module, and the public end is electrically connected with the storage interface;

the gating control pin is used for controlling the connection between the common terminal and the first gating terminal and controlling the communication connection between the common terminal and the second gating terminal;

the interface end of the memory module includes: the device comprises an instruction pin, a clock pin, a first test data pin, a second test data pin, a third test data pin and a fourth test data pin;

the second gate terminal includes: a sixth channel pin corresponding to the instruction pin, a seventh channel pin corresponding to the clock pin, an eighth channel pin corresponding to the first test data pin, a ninth channel pin corresponding to the second test data pin, a tenth channel pin corresponding to the third test data pin, and an eleventh channel pin corresponding to the fourth test data pin;

when the signal input to the gating control pin is at a second level, the sixth channel pin, the seventh channel pin, the eighth channel pin, the ninth channel pin, the tenth channel pin, and the eleventh channel pin in the channel selection module are gated.

2. The veneer according to claim 1,

the interface end of the JTAG module comprises: a test mode selection pin, a test clock pin, a test data input pin and a test data output pin;

the first strobe terminal includes: a first channel pin corresponding to the test mode selection pin, a second channel pin corresponding to the test clock pin, a third channel pin corresponding to the test data input pin, and a fourth channel pin corresponding to the test data output pin;

when the signal input into the gating control pin is at a first level, the first channel pin, the second channel pin, the third channel pin and the fourth channel pin in the channel selection module are gated;

the first level is different from the second level.

3. The single board according to any of claims 1-2, wherein the storage interface comprises a storage device detection pin, the storage device detection pin being electrically connected to the gating control pin;

the storage device detection pin is used for triggering a signal input into the gating control pin to be a first level when the JTAG test device is electrically connected with the storage interface; and when the storage equipment is electrically connected with the storage interface, triggering the signal input into the gating control pin to be the second level.

4. The veneer according to claim 1,

the channel selection module is also used for inputting a JTAG test signal from the JTAG test equipment into the JTAG module when a passage is formed with the JTAG module;

the JTAG module is used for executing a test item corresponding to the JTAG test signal according to the JTAG test signal received from the channel selection module and transmitting first test data obtained by testing to the channel selection module;

the channel selection module is further configured to transmit the first test data from the JTAG module to the JTAG test device through the storage interface.

5. An electronic device, characterized in that the electronic device comprises:

the veneer according to any one of claims 1 to 4.

6. A gating method is applied to a single board, and is characterized in that the method comprises the following steps:

when Joint Test Action Group (JTAG) test equipment is electrically connected with a storage interface in the single board, a channel selection module in the single board is communicated with the storage interface and a JTAG module in the single board;

when the storage device is electrically connected with the storage interface in the single board, the channel selection module is communicated with the storage interface and the storage module in the single board;

the channel selection module comprises a first gating end, a second gating end, a public end and a gating control pin, wherein the first gating end is electrically connected with an interface end of the JTAG module, the second gating end is electrically connected with an interface end of the storage module, and the public end is electrically connected with a storage interface in the single board; the storage interface comprises a storage device detection pin which is electrically connected with the gating control pin;

when the joint test action group JTAG test equipment is electrically connected with the storage interface in the single board, the channel selection module in the single board is communicated with the storage interface and the JTAG module in the single board, and the joint test action group JTAG test equipment comprises the following components:

when the JTAG test equipment is electrically connected with a storage interface in the single board, the storage equipment detects that a signal input into a gating control pin in the channel selection module by the pin is a first level, and the gating control pin gates the first gating end so as to enable the JTAG test equipment to be in communication connection with the JTAG module;

when the storage device is electrically connected to the storage interface in the board, the channel selection module communicates the storage interface with the storage module in the board, including:

when the storage device is electrically connected with a storage interface in the single board, the storage device detects that a signal input by a pin to a gating control pin in the channel selection module is a second level, and the gating control pin gates the second gating end so that the storage device is in communication connection with the storage module; the second level is different from the first level.

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