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CN108336053A - The manufacturing method of packaging and packaging - Google Patents

The manufacturing method of packaging and packaging Download PDF

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Publication number
CN108336053A
CN108336053A CN201810231493.8A CN201810231493A CN108336053A CN 108336053 A CN108336053 A CN 108336053A CN 201810231493 A CN201810231493 A CN 201810231493A CN 108336053 A CN108336053 A CN 108336053A
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Prior art keywords
pad
chip
conductive film
substrate
packaged device
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CN201810231493.8A
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CN108336053B (en
Inventor
蔡苗
杨道国
杨张平
王磊
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Guilin University of Electronic Technology
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Guilin University of Electronic Technology
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The present invention provides the manufacturing method of a kind of packaging and packaging, packaging includes:Substrate, chip, conductive film and packaging body;The side of substrate is provided with the first pad;Chip includes the second pad;The side of conductive film fits with the first pad, and the other side of conductive film fits with the second pad, and the first pad is oppositely arranged with the second pad;Packaging body is at least coated on the outside of chip and conductive film.In the packaging body of packaging, the second pad of chip is bonded with the first pad of substrate by conductive film, and chip, conductive film is made to be combined with substrates into intimate by way of pressing, is set and is fixed to each other in packaging body encapsulation standing back.Due to not using lead and solder, first pad and the second pad need not be welded using solder, so the problems such as being not in that silk is rushed in bonding at the bonding of the first pad and the second pad, bonding fracture, deformation will not be generated, there is no foreign matter participation in process, and then ensures bonding face cleaning.

Description

封装器件和封装器件的制造方法Packaged device and method of manufacturing the packaged device

技术领域technical field

本发明涉及封装器件技术领域,具体而言,涉及一种封装器件和一种封装器件的制造方法。The present invention relates to the technical field of packaged devices, in particular to a packaged device and a method for manufacturing the packaged device.

背景技术Background technique

目前,在传统的封装技术中,键合的方式主要分为引线键合和倒装焊技术。虽然传统的引线键合以及倒装焊技术已经相当成熟,但依然存在诸多问题。首先成本方面而言,引线键合的工艺需要键合机,极细的金线,倒装焊需要对芯片预置焊点,这些都不可避免的复杂了工艺增加了设备、工序以及材料的成本。其次工艺方面,引线键合的键合间隙受制于契刀的尺寸,无法满足日益缩小的封装器件尺寸要求,特别是无法适用于新型封装技术,如扇出型晶元封装、系统级封装,并且键合丝封装时会产生冲丝,断裂形变等一系列问题。倒装焊技容易出现垂直方向的下坠和水平方向上的摇摆问题,特别对功率器件更是如此。最后可靠性方面而言,引线键合以及倒装焊在长期循环载荷的工作环境下,键合丝和预置焊点都会有相应的损伤,从而影响封装器件的可靠性。因此传统的键合形式无法满足封装器件日益提高的要求。为解决传统工艺技术的瓶颈和现有技术方案的不足,有必要开发一种加工流程简单、成品率高、成本低的工艺方法。At present, in traditional packaging technologies, bonding methods are mainly divided into wire bonding and flip-chip bonding technologies. Although the traditional wire bonding and flip-chip bonding technologies are quite mature, there are still many problems. First of all, in terms of cost, the wire bonding process requires a bonding machine, extremely thin gold wires, and flip-chip bonding requires pre-soldered solder joints on the chip. These inevitably complicate the process and increase the cost of equipment, processes, and materials. . Secondly, in terms of process, the bonding gap of wire bonding is limited by the size of the knife, which cannot meet the increasingly shrinking packaging device size requirements, especially cannot be applied to new packaging technologies, such as fan-out wafer packaging, system-in-package, and A series of problems such as wire punching and fracture deformation will occur when bonding wire is packaged. Flip-chip soldering technology is prone to vertical drop and horizontal swing, especially for power devices. Finally, in terms of reliability, wire bonding and flip-chip soldering will have corresponding damage to the bonding wire and preset solder joints under the long-term cyclic load working environment, which will affect the reliability of the packaged device. Therefore, the traditional bonding form cannot meet the increasing requirements of packaged devices. In order to solve the bottleneck of the traditional process technology and the deficiency of the existing technical solutions, it is necessary to develop a process method with simple processing flow, high yield and low cost.

发明内容Contents of the invention

本发明旨在至少解决现有技术或相关技术中存在的技术问题之一。The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

为此,本发明的第一方面提出一种封装器件。To this end, a first aspect of the present invention proposes a packaged device.

本发明的第二方面提出一种封装器件的制造方法。A second aspect of the present invention proposes a method of manufacturing a packaged device.

有鉴于此,本发明的第一方面提供了一种封装器件,包括:基板、芯片、导电膜和封装体;基板的一侧设置有第一焊盘;芯片包括第二焊盘;导电膜的一侧与第一焊盘相贴合,导电膜的另一侧与第二焊盘相贴合,第一焊盘与第二焊盘相对设置;封装体至少包覆于芯片与导电膜的外侧。In view of this, the first aspect of the present invention provides a packaged device, including: a substrate, a chip, a conductive film and a package body; a first pad is provided on one side of the substrate; the chip includes a second pad; the conductive film One side is attached to the first pad, the other side of the conductive film is attached to the second pad, and the first pad is opposite to the second pad; the package is at least coated on the outside of the chip and the conductive film .

本发明所提供的封装器件,芯片的第二焊盘与基板的第一焊盘通过导电膜键合,制造时将导电膜与基板需要安装芯片的一面相贴合,再将芯片与导电膜贴合,对芯片施予一定压力,通过压合的方式使芯片、导电膜与基板紧密相结合后封装,在封装体封装固化后,芯片、导电膜与基板的位置相互固定。该方法生产工艺简单,不需要昂贵的键合设备,减少了生产工序,可应用于微小型封装器件的生产。由于制造过程中不使用引线和焊料,不需要对第一焊盘和第二焊盘使用焊料焊接,所以第一焊盘和第二焊盘的键合处不会出现键合冲丝,也不会产生键合断裂、变形等问题,加工过程中没有异物参与,进而保证键合面清洁。同时通过压合的方式结合还能避免倒装焊技术处理时的高温处理步骤,芯片和基板都不会受热,避免了在热加载中产生大量热应力时芯片位置发生摇摆偏移的情况,并且在封装器件为功率器件时,避免了由于功率器件发热量较大,长时间使用导致封装体内积聚热量导致键合丝、焊点受损发生脱焊的情况。因此封装器件的良品率更高,使用中的可靠性也更好,同时生产工序简单,利于量产。In the packaging device provided by the present invention, the second pad of the chip is bonded to the first pad of the substrate through a conductive film, and the conductive film is bonded to the side of the substrate where the chip needs to be installed during manufacture, and then the chip and the conductive film are pasted together. Combine, apply a certain pressure to the chip, and package the chip, conductive film and substrate tightly by pressing. After the package is packaged and cured, the positions of the chip, conductive film and substrate are fixed to each other. The method has a simple production process, does not require expensive bonding equipment, reduces production procedures, and can be applied to the production of micro-miniature packaging devices. Since lead wires and solder are not used in the manufacturing process, there is no need to use solder welding for the first pad and the second pad, so there will be no bonding punch at the bonding place between the first pad and the second pad, and there will be no bonding wire. There will be problems such as bond fracture and deformation, and there will be no foreign matter involved in the processing process, thereby ensuring that the bonding surface is clean. At the same time, the combination by pressing can also avoid the high-temperature processing steps during the flip-chip welding process, and the chip and the substrate will not be heated, avoiding the situation where the chip position swings and shifts when a large amount of thermal stress is generated during thermal loading, and When the packaged device is a power device, it is avoided that due to the high heat generation of the power device, the heat accumulated in the package will cause the bonding wire and solder joints to be damaged and desoldering due to long-term use. Therefore, the yield rate of packaged devices is higher, and the reliability in use is also better. At the same time, the production process is simple, which is conducive to mass production.

另外,本发明提供的上述技术方案中的封装器件还可以具有如下附加技术特征:In addition, the packaged device in the above technical solution provided by the present invention may also have the following additional technical features:

在上述技术方案中,优选地,导电膜包括:绝缘载体和导电体;导电体沿绝缘载体的厚度方向延伸。In the above technical solution, preferably, the conductive film includes: an insulating carrier and a conductor; the conductor extends along the thickness direction of the insulating carrier.

在该技术方案中,在绝缘载体中沿绝缘载体的厚度间隔设置导电体来形成导电膜,使导电膜在厚度方向上通过导电体来导通电流,在芯片的第二焊盘与基板的第一焊盘分别贴合于导电膜的两侧时,实现芯片和基板的对应焊盘之间的电连接。In this technical solution, conductors are arranged at intervals along the thickness of the insulating carrier in the insulating carrier to form a conductive film, so that the conductive film passes through the conductors in the thickness direction to conduct current, and the second pad of the chip and the first pad of the substrate When a welding pad is attached to both sides of the conductive film, the electrical connection between the chip and the corresponding welding pad of the substrate is realized.

在上述任一技术方案中,优选地,多个导电体呈阵列式分布于绝缘载体上。In any of the above technical solutions, preferably, a plurality of conductors are distributed in an array on the insulating carrier.

在该技术方案中,以阵列的形式将多个导电体分布设置于绝缘载体上,单个导电体可为圆柱体或立方体等形状,保证导电膜在厚度方向上电导通且每个焊盘都至少与一个导电体接触,在同时有多个导电体与同一个焊盘接触的情况下,还可增加接触的总面积,提高电导率。In this technical solution, a plurality of electrical conductors are distributed on an insulating carrier in the form of an array, and a single electrical conductor can be in the shape of a cylinder or a cube to ensure that the conductive film is electrically conductive in the thickness direction and each pad has at least In contact with one conductor, in the case that multiple conductors are in contact with the same pad at the same time, the total contact area can be increased and the conductivity can be improved.

在上述任一技术方案中,优选地,第一焊盘为多个,第二焊盘的数量与第一焊盘的数量相等;导电体的横截面的任一宽度均小于相邻的第一焊盘之间的距离;和/或导电体的横截面的任一宽度均小于相邻的第二焊盘之间的距离。In any of the above technical solutions, preferably, there are multiple first pads, and the number of the second pads is equal to the number of the first pads; any width of the cross-section of the conductor is smaller than that of the adjacent first pads. The distance between the pads; and/or any width of the cross-section of the conductor is smaller than the distance between adjacent second pads.

在该技术方案中,预制基板的第一焊盘设置为多个,数量与芯片的第二焊盘的数量相等,保证封装后芯片的引脚/触点数量不变;导电体的横截面的任一宽度均小于相邻的第一焊盘之间的距离,即单一导电体不会同时接触任意方向上的任意两个相邻的第一焊盘,确保任意两个相邻的第一焊盘不会被短接;和/或导电体的横截面的任一宽度均小于相邻的第二焊盘之间的距离,即单一导电体同样不会同时接触任意方向上的任意两个相邻的第二焊盘,确保任意两个相邻的第二焊盘不会被短接。In this technical scheme, the number of first pads of the prefabricated substrate is set to be multiple, and the number is equal to the number of the second pads of the chip, so as to ensure that the number of pins/contacts of the chip after packaging remains unchanged; the cross-section of the conductor Any width is smaller than the distance between adjacent first pads, that is, a single conductor will not contact any two adjacent first pads in any direction at the same time, ensuring that any two adjacent first pads The pads will not be short-circuited; and/or any width of the cross-section of the conductor is smaller than the distance between the adjacent second pads, that is, a single conductor will also not contact any two phases in any direction at the same time. Adjacent second pads to ensure that any two adjacent second pads will not be short-circuited.

在上述任一技术方案中,优选地,第一焊盘与第二焊盘直接设置有一个或多个导电体。In any of the above technical solutions, preferably, one or more conductors are directly provided on the first pad and the second pad.

在该技术方案中,对应的第一焊盘与第二焊盘间通过一个或多个导电体实现电连接,保证电连接可靠性的基础上,更多的导电体能增加第一焊盘与第二焊盘之间导电体的总面积,降低阻抗。In this technical solution, the electrical connection between the corresponding first pad and the second pad is realized through one or more conductors, and on the basis of ensuring the reliability of the electrical connection, more conductors can increase the number of connections between the first pad and the second pad. The total area of the conductor between the two pads reduces the impedance.

在上述任一技术方案中,优选地,封装器件还包括:第三焊盘;第三焊盘设置在基板的另一侧,与第一焊盘相连接。In any of the above technical solutions, preferably, the packaged device further includes: a third pad; the third pad is disposed on the other side of the substrate and connected to the first pad.

在该技术方案中,在基板的另一侧设置与第一焊盘通过内置线路对应导通的第三焊盘,即实现芯片的第二焊盘与第三焊盘的间对应的电连接关系,保证芯片被封装为封装器件后的功能完整。In this technical solution, on the other side of the substrate, a third pad that is electrically connected to the first pad through a built-in circuit is provided, that is, the corresponding electrical connection relationship between the second pad and the third pad of the chip is realized. , to ensure that the function of the chip after being packaged as a packaged device is complete.

在上述任一技术方案中,优选地,封装器件还包括:焊料;焊料设置在第三焊盘上。In any of the above technical solutions, preferably, the packaging device further includes: solder; the solder is disposed on the third pad.

在该技术方案中,在第三焊盘上设置焊料,使封装器件的安装更加方便快捷。In this technical solution, solder is provided on the third pad, so that the installation of the packaged device is more convenient and quick.

在上述任一技术方案中,优选地,焊料为锡焊料或钎焊料。In any of the above technical solutions, preferably, the solder is tin solder or brazing material.

在该技术方案中,焊料为锡焊料或钎焊料,成本低廉且应用简单,方便量产。In this technical solution, the solder is tin solder or brazing material, which is low in cost, simple in application, and convenient for mass production.

在上述任一技术方案中,优选地,第一焊盘嵌于基板中,以使第一焊盘的表面与基板的表面平齐。In any of the above technical solutions, preferably, the first pad is embedded in the substrate, so that the surface of the first pad is flush with the surface of the substrate.

在该技术方案中,第一焊盘嵌于基板中,不易脱落;同时第一焊盘的表面与基板的表面平齐,使导电膜与基板压合时更加贴合,不易松动,进而增加可靠性。In this technical solution, the first pad is embedded in the substrate and is not easy to fall off; at the same time, the surface of the first pad is flush with the surface of the substrate, so that the conductive film and the substrate are more closely bonded and not easy to loosen, thereby increasing reliability. sex.

在上述任一技术方案中,优选地,基板为陶瓷基板或PCB板。In any of the above technical solutions, preferably, the substrate is a ceramic substrate or a PCB board.

在该技术方案中,基板选用陶瓷基板或PCB(印刷电路板)板,技术成熟,生产难度低,有利于成本控制。In this technical solution, the substrate is a ceramic substrate or a PCB (printed circuit board) board, which is mature in technology and low in production difficulty, which is beneficial to cost control.

本发明第二方面提供了一种封装器件的制造方法,包括:在基板上设置第一焊盘;在基板上设置导电膜,导电膜与第一焊盘相贴合;将芯片的第二焊盘贴合于导电膜上;封装芯片与导电膜,以形成封装器件。The second aspect of the present invention provides a method for manufacturing a packaged device, including: setting a first pad on a substrate; setting a conductive film on the substrate, and the conductive film is attached to the first pad; The disk is pasted on the conductive film; the chip and the conductive film are packaged to form a packaged device.

在该技术方案中,在基板上设置第一焊盘,用以连接芯片的第二焊盘;在基板上设置导电膜与第一焊盘相贴合,并将芯片的第二焊盘贴合于导电膜上,实现芯片的第二焊盘与基板上对应的第一焊盘间的电连接;封装芯片与导电膜,封装后的芯片与导电膜牢牢固定于基板上,以形成封装器件。该封装方法不使用引线和焊料,不需要对第一焊盘和第二焊盘使用焊料焊接,所以第一焊盘和第二焊盘的键合处不会出现键合丝损伤,也不会产生键合变形,加工过程中没有异物参与,进而保证键合面清洁。同时避免倒装焊技术处理时的高温处理步骤,芯片和基板都不会受热,避免了在热加载中产生大量热应力时芯片位置发生摇摆偏移的情况,并且在封装器件为功率器件时,避免了由于功率器件发热量较大,长时间使用导致封装体内积聚热量导致发生脱焊的情况。同时封装过程可为多个芯片与导电膜和对应的多个基板同时封装,以提升生产效率,在封装完成后,通过切割工序将多个封装好的封装器件分离成独立的封装器件,可进一步增加产能。In this technical solution, a first pad is provided on the substrate to connect to the second pad of the chip; a conductive film is provided on the substrate to be bonded to the first pad, and the second pad of the chip is bonded On the conductive film, realize the electrical connection between the second pad of the chip and the corresponding first pad on the substrate; package the chip and the conductive film, and the packaged chip and the conductive film are firmly fixed on the substrate to form a packaged device . This packaging method does not use wires and solder, and does not need to use solder welding for the first pad and the second pad, so there will be no damage to the bonding wire at the bonding of the first pad and the second pad, and there will be no damage to the bonding wire. Bonding deformation occurs, and there is no foreign matter involved in the processing process, thereby ensuring that the bonding surface is clean. At the same time, it avoids the high-temperature processing steps during flip-chip welding technology, and neither the chip nor the substrate is heated, which avoids the situation where the chip position swings and shifts when a large amount of thermal stress is generated during thermal loading, and when the packaged device is a power device, It avoids the situation that due to the large heat generation of the power device, the heat accumulated in the package will cause desoldering due to long-term use. At the same time, the packaging process can package multiple chips, conductive films and corresponding multiple substrates at the same time to improve production efficiency. After the packaging is completed, multiple packaged packaged devices are separated into independent packaged devices through the cutting process, which can be further processed. Increase production capacity.

在上述技术方案中,优选地,在将芯片的第二焊盘贴合于导电膜上,与封装芯片与导电膜,以形成封装器件之间,封装器件的制造方法还包括:向芯片施加第一预设压力,第一预设压力的方向与基板垂直。In the above technical solution, preferably, between attaching the second pad of the chip to the conductive film, and packaging the chip and the conductive film to form a packaged device, the manufacturing method of the packaged device further includes: applying the second bonding pad to the chip A preset pressure, the direction of the first preset pressure is perpendicular to the substrate.

在该技术方案中,向芯片施加垂直于基板的第一预设压力,第一预设压力小于会对芯片造成损伤的最小压力,保证芯片不会在封装过程中受损,同时使芯片的第二焊盘、导电膜与基板的第一焊盘间贴合更加紧密,保证芯片的第二焊盘、导电膜与基板的第一焊盘间电连接的可靠性。In this technical solution, a first preset pressure perpendicular to the substrate is applied to the chip, and the first preset pressure is less than the minimum pressure that will cause damage to the chip, so as to ensure that the chip will not be damaged during the packaging process, and at the same time, the first preset pressure of the chip will not be damaged. The bonding between the second pad, the conductive film and the first pad of the substrate is tighter, ensuring the reliability of the electrical connection between the second pad of the chip, the conductive film and the first pad of the substrate.

在上述技术方案中,优选地,在封装芯片与导电膜,以形成封装器件之后,封装器件的制造方法还包括:在基板上设置第三焊盘;在第三焊盘上设置焊料。In the above technical solution, preferably, after the chip and the conductive film are packaged to form the packaged device, the manufacturing method of the packaged device further includes: disposing a third pad on the substrate; and disposing solder on the third pad.

在该技术方案中,在基板上设置与第一焊盘对应连接的第三焊盘,实现芯片的第二焊盘与封装器件基板的第三焊盘间的电连接,并在第三焊盘上设置焊料,使封装器件的安装更加方便快捷。In this technical solution, a third pad correspondingly connected to the first pad is provided on the substrate to realize the electrical connection between the second pad of the chip and the third pad of the packaging device substrate, and the third pad Solder is set on the package to make the installation of the packaged device more convenient and quick.

在上述任一技术方案中,优选地,在封装芯片与导电膜,以形成封装器件之后,封装器件的制造方法还包括:修剪封装器件的毛边;清洗封装器件。In any of the above technical solutions, preferably, after the chip and the conductive film are packaged to form the packaged device, the manufacturing method of the packaged device further includes: trimming burrs of the packaged device; cleaning the packaged device.

在该技术方案中,在封装芯片与导电膜,封装体固化并分隔成独立的封装器件后,修剪封装器件的毛边并清洗封装器件,提升封装器件的做工品质,进一步提高用户对产品的满意度。In this technical solution, after packaging the chip and the conductive film, the package body is cured and separated into independent packaged devices, the burrs of the packaged devices are trimmed and the packaged devices are cleaned, so as to improve the workmanship quality of the packaged devices and further improve the user's satisfaction with the product .

本发明的附加方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

附图说明Description of drawings

本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解,其中:The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

图1示出了根据本发明的一个实施例的封装器件的结构示意图;FIG. 1 shows a schematic structural view of a packaged device according to an embodiment of the present invention;

图2示出了根据本发明的一个实施例的导电膜的结构示意图;Fig. 2 shows a schematic structural view of a conductive film according to an embodiment of the present invention;

图3示出了根据本发明的另一个实施例的导电膜的结构示意图;Figure 3 shows a schematic structural view of a conductive film according to another embodiment of the present invention;

图4示出了根据本发明的另一个实施例的封装器件的结构示意图;FIG. 4 shows a schematic structural diagram of a packaged device according to another embodiment of the present invention;

图5示出了根据本发明的再一个实施例的封装器件的结构示意图;FIG. 5 shows a schematic structural diagram of a packaged device according to yet another embodiment of the present invention;

图6示出了根据本发明的再一个实施例的封装器件的结构示意图;FIG. 6 shows a schematic structural diagram of a packaged device according to yet another embodiment of the present invention;

图7示出了根据本发明的再一个实施例的封装器件的结构示意图;FIG. 7 shows a schematic structural diagram of a packaged device according to yet another embodiment of the present invention;

图8示出了根据本发明的一个实施例的封装器件的制造方法的流程图;FIG. 8 shows a flowchart of a method for manufacturing a packaged device according to an embodiment of the present invention;

图9示出了根据本发明的另一个实施例的封装器件的制造方法的流程图;FIG. 9 shows a flowchart of a method for manufacturing a packaged device according to another embodiment of the present invention;

图10示出了根据本发明的再一个实施例的封装器件的制造方法的流程图;FIG. 10 shows a flowchart of a method for manufacturing a packaged device according to yet another embodiment of the present invention;

图11示出了根据本发明的再一个实施例的封装器件的制造方法的流程图;FIG. 11 shows a flow chart of a method for manufacturing a packaged device according to yet another embodiment of the present invention;

其中,图1至图7中的附图标记与部件名称之间的对应关系为:Wherein, the corresponding relationship between the reference numerals and the part names in Fig. 1 to Fig. 7 is:

1基板;2第一焊盘;3芯片;4第二焊盘;5导电膜;51绝缘载体;52导电体;6封装体;7第三焊盘;8焊料。1 substrate; 2 first pad; 3 chip; 4 second pad; 5 conductive film; 51 insulating carrier; 52 conductor; 6 package; 7 third pad; 8 solder.

具体实施方式Detailed ways

为了能够更清楚地理解本发明的上述目的、特征和优点,下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是,在不冲突的情况下,本申请的实施例及实施例中的特征可以相互组合。In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是,本发明还可以采用其他不同于在此描述的其他方式来实施,因此,本发明的保护范围并不受下面公开的具体实施例的限制。In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described here. Therefore, the protection scope of the present invention is not limited by the specific details disclosed below. EXAMPLE LIMITATIONS.

下面参照图1至图11描述根据本发明一些实施例所述封装器件和封装器件的制造方法。The packaged device and the manufacturing method of the packaged device according to some embodiments of the present invention will be described below with reference to FIGS. 1 to 11 .

如图1所示,在本发明第一方面的实施例中,本发明提供了一种封装器件,包括:基板1、芯片3、导电膜5和封装体6;基板1的一侧设置有第一焊盘2;芯片3包括第二焊盘4;导电膜5的一侧与第一焊盘2相贴合,导电膜5的另一侧与第二焊盘4相贴合,第一焊盘2与第二焊盘4相对设置;封装体6至少包覆于芯片3与导电膜5的外侧。As shown in Figure 1, in the embodiment of the first aspect of the present invention, the present invention provides a packaged device, comprising: a substrate 1, a chip 3, a conductive film 5 and a package body 6; one side of the substrate 1 is provided with a first A pad 2; the chip 3 includes a second pad 4; one side of the conductive film 5 is attached to the first pad 2, the other side of the conductive film 5 is attached to the second pad 4, and the first solder The pad 2 is opposite to the second pad 4 ; the package body 6 covers at least the outside of the chip 3 and the conductive film 5 .

在该实施例中,封装器件的封装体6内,芯片3的第二焊盘4与基板1的第一焊盘2通过导电膜5键合,制造时将导电膜5与基板1需要安装芯片3的一面相贴合,再将芯片3与导电膜5贴合,对芯片3施予一定压力,通过压合的方式使芯片3、导电膜5与基板1紧密相结合后封装,在封装体封装固化后,芯片3、导电膜5与基板1的位置相互固定。该方法生产工艺简单,不需要昂贵的键合设备,减少了生产工序,可应用于微小型封装器件的生产。由于制造过程中不使用引线和焊料,不需要对第一焊盘2和第二焊盘4使用焊料焊接,所以第一焊盘2和第二焊盘4的键合处不会出现键合冲丝,也不会产生键合断裂、变形等问题,加工过程中没有异物参与,进而保证键合面清洁。同时通过压合的方式结合还能避免倒装焊技术处理时的高温处理步骤,芯片3和基板1都不会受热,避免了在热加载中产生大量热应力时芯片3位置发生摇摆偏移的情况,并且在封装器件为功率器件时,避免了由于功率器件发热量较大,长时间使用导致封装体6内积聚热量导致键合丝、焊点受损发生脱焊的情况。因此封装器件的良品率更高,使用中的可靠性也更好,同时生产工序简单,利于量产。In this embodiment, in the package body 6 of the packaged device, the second pad 4 of the chip 3 and the first pad 2 of the substrate 1 are bonded through the conductive film 5, and the conductive film 5 and the substrate 1 need to be installed with the chip during manufacture. 3, then attach the chip 3 and the conductive film 5, apply a certain pressure on the chip 3, and then package the chip 3, the conductive film 5 and the substrate 1 tightly by pressing, and then package the chip 3 and the conductive film 5. After the package is cured, the positions of the chip 3 , the conductive film 5 and the substrate 1 are fixed to each other. The method has a simple production process, does not require expensive bonding equipment, reduces production procedures, and can be applied to the production of micro-miniature packaging devices. Since lead wire and solder are not used in the manufacturing process, there is no need to use solder welding to the first pad 2 and the second pad 4, so no bonding impact will occur at the bonding place of the first pad 2 and the second pad 4. There will be no problems such as bond breakage and deformation, and there will be no foreign matter involved in the processing process, thereby ensuring that the bonding surface is clean. At the same time, the combination by pressing can also avoid the high-temperature processing steps during the flip-chip welding process, and neither the chip 3 nor the substrate 1 will be heated, which avoids the position of the chip 3 swinging and shifting when a large amount of thermal stress is generated during thermal loading. situation, and when the packaged device is a power device, it is avoided that due to the high heat generation of the power device, the heat accumulated in the package body 6 after long-term use will cause the bonding wire and solder joints to be damaged and desoldering. Therefore, the yield rate of packaged devices is higher, and the reliability in use is also better. At the same time, the production process is simple, which is conducive to mass production.

在本发明的一个实施例中,优选地,如图2所示,导电膜5包括:绝缘载体51和导电体52;导电体52沿绝缘载体51的厚度方向延伸。In one embodiment of the present invention, preferably, as shown in FIG. 2 , the conductive film 5 includes: an insulating carrier 51 and a conductor 52 ; the conductor 52 extends along the thickness direction of the insulating carrier 51 .

在该实施例中,在绝缘载体51中沿绝缘载体51的厚度间隔设置导电体52来形成导电膜5,使导电膜5在厚度方向上通过导电体52来导通电流,在芯片3的第二焊盘4与基板1的第一焊盘2分别贴合于导电膜5的两侧时,实现芯片3和基板1的对应焊盘之间的电连接。In this embodiment, in the insulating carrier 51, conductors 52 are arranged at intervals along the thickness of the insulating carrier 51 to form the conductive film 5, so that the conductive film 5 conducts electric current through the conductors 52 in the thickness direction, and the first part of the chip 3 When the second pad 4 and the first pad 2 of the substrate 1 are attached to both sides of the conductive film 5 respectively, the electrical connection between the chip 3 and the corresponding pad of the substrate 1 is realized.

在本发明的一个实施例中,优选地,如图2所示,多个导电体52呈阵列式分布于绝缘载体51上。In one embodiment of the present invention, preferably, as shown in FIG. 2 , a plurality of conductors 52 are distributed in an array on the insulating carrier 51 .

在该实施例中,以阵列的形式将多个导电体52分布设置于绝缘载体51上,单个导电体52可为圆柱体或立方体等形状,保证导电膜5在厚度方向上电导通且每个焊盘都至少与一个导电体52接触,在同时有多个导电体52与同一个焊盘接触的情况下,还可增加接触的总面积,提高电导率。In this embodiment, a plurality of conductors 52 are distributed on the insulating carrier 51 in the form of an array, and a single conductor 52 can be in the shape of a cylinder or a cube to ensure that the conductive film 5 is electrically connected in the thickness direction and each All pads are in contact with at least one conductor 52 , and in the case that multiple conductors 52 are in contact with the same pad at the same time, the total contact area can be increased and the electrical conductivity can be improved.

在本发明的一个实施例中,优选地,如图3至图6所示,第一焊盘2为多个,第二焊盘4的数量与第一焊盘2的数量相等;导电体52的横截面的任一宽度均小于相邻的第一焊盘2之间的距离;和/或导电体52的横截面的任一宽度均小于相邻的第二焊盘4之间的距离。In one embodiment of the present invention, preferably, as shown in FIGS. Any width of the cross section of the conductor 52 is smaller than the distance between adjacent first pads 2 ; and/or any width of the cross section of the conductor 52 is smaller than the distance between adjacent second pads 4 .

在该实施例中,预制基板1的第一焊盘2设置为多个,数量与芯片3的第二焊盘4的数量相等,保证封装后芯片3的引脚/触点数量不变;导电体52的横截面的任一宽度均小于相邻的第一焊盘2之间的距离,即单一导电体52不会同时接触任意方向上的任意两个相邻的第一焊盘2,确保任意两个相邻的第一焊盘2不会被短接;和/或导电体52的横截面的任一宽度均小于相邻的第二焊盘4之间的距离,即单一导电体52同样不会同时接触任意方向上的任意两个相邻的第二焊盘4,确保任意两个相邻的第二焊盘4不会被短接。In this embodiment, the first pads 2 of the prefabricated substrate 1 are set in multiples, and the number is equal to the number of the second pads 4 of the chip 3, so as to ensure that the number of pins/contacts of the chip 3 after packaging remains unchanged; Any width of the cross-section of the body 52 is less than the distance between the adjacent first pads 2, that is, a single conductor 52 will not contact any two adjacent first pads 2 in any direction at the same time, ensuring Any two adjacent first pads 2 will not be short-circuited; and/or any width of the cross-section of the conductor 52 is smaller than the distance between the adjacent second pads 4, that is, a single conductor 52 Likewise, any two adjacent second pads 4 in any direction will not be contacted at the same time, ensuring that any two adjacent second pads 4 will not be short-circuited.

在本发明的一个实施例中,优选地,如图5和图6所示,第一焊盘2与第二焊盘4直接设置有一个或多个导电体52。In one embodiment of the present invention, preferably, as shown in FIG. 5 and FIG. 6 , the first pad 2 and the second pad 4 are directly provided with one or more conductors 52 .

在该实施例中,对应的第一焊盘2与第二焊盘4间通过一个或多个导电体52实现电连接,保证电连接可靠性的基础上,更多的导电体52能增加第一焊盘2与第二焊盘4之间导电体52的总面积,降低阻抗。In this embodiment, the corresponding first pad 2 and the second pad 4 are electrically connected through one or more conductors 52. On the basis of ensuring the reliability of the electrical connection, more conductors 52 can increase the The total area of the conductor 52 between the first pad 2 and the second pad 4 reduces the impedance.

在本发明的一个实施例中,优选地,如图1至图7所示,封装器件还包括:第三焊盘7;第三焊盘7设置在基板1的另一侧,与第一焊盘2相连接。In one embodiment of the present invention, preferably, as shown in FIG. 1 to FIG. 7 , the packaged device further includes: a third pad 7; Disk 2 is connected.

在该实施例中,在基板1的另一侧设置与第一焊盘2通过内置线路对应导通的第三焊盘7,即实现芯片3的第二焊盘4与第三焊盘7的间对应的电连接关系,保证芯片3被封装为封装器件后的功能完整。In this embodiment, on the other side of the substrate 1, a third pad 7 that is connected to the first pad 2 through a built-in circuit is provided, that is, the connection between the second pad 4 and the third pad 7 of the chip 3 is realized. The corresponding electrical connection relationship between them ensures that the function of the chip 3 after being packaged as a packaged device is complete.

在本发明的一个实施例中,优选地,如图1所示,封装器件还包括:焊料8;焊料8设置在第三焊盘7上。In one embodiment of the present invention, preferably, as shown in FIG. 1 , the packaged device further includes: solder 8 ; the solder 8 is disposed on the third pad 7 .

在该实施例中,在第三焊盘7上设置焊料8,焊料8呈球形或半球形,使封装器件的安装更加方便快捷。In this embodiment, the solder 8 is provided on the third pad 7, and the solder 8 is spherical or hemispherical, which makes the installation of the packaged device more convenient and quick.

在本发明的一个实施例中,优选地,焊料8为锡焊料8或钎焊料8。In one embodiment of the present invention, preferably, the solder 8 is tin solder 8 or solder 8 .

在该技术方案中,焊料8为锡焊料或钎焊料,成本低廉且应用简单,方便量产。In this technical solution, the solder 8 is tin solder or brazing material, which is low in cost, simple in application, and convenient for mass production.

在本发明的一个实施例中,优选地,如图1、图3至图7所示,第一焊盘2嵌于基板1中,以使第一焊盘2的表面与基板1的表面平齐。In one embodiment of the present invention, preferably, as shown in FIG. 1, FIG. 3 to FIG. together.

在该实施例中,第一焊盘2嵌于基板1中,不易脱落;同时第一焊盘2的表面与基板1的表面平齐,使导电膜5与基板1压合时更加贴合,不易松动,进而增加可靠性。In this embodiment, the first pad 2 is embedded in the substrate 1 and is not easy to fall off; at the same time, the surface of the first pad 2 is flush with the surface of the substrate 1, so that the conductive film 5 and the substrate 1 are more closely bonded, Not easy to loosen, thus increasing reliability.

在本发明的一个实施例中,优选地,基板1为陶瓷基板或PCB板。In one embodiment of the present invention, preferably, the substrate 1 is a ceramic substrate or a PCB board.

在该实施例中,基板1选用陶瓷基板或PCB板,技术成熟,生产难度低,有利于成本控制。In this embodiment, the substrate 1 is made of a ceramic substrate or a PCB board, which has mature technology and low production difficulty, which is beneficial to cost control.

如图8所示,本发明第二方面的实施例提供了一种封装器件的制造方法,包括:如图3和图4所示,S101,在基板1上设置第一焊盘2;如图5所示,S102,在基板1上设置导电膜5,导电膜5与第一焊盘2相贴合;如图6所示,S103,将芯片3的第二焊盘4贴合于导电膜5上;如图7所示,S104,封装芯片3与导电膜5,以形成封装器件。As shown in FIG. 8, the embodiment of the second aspect of the present invention provides a method for manufacturing a packaged device, including: as shown in FIG. 3 and FIG. 4, S101, setting the first pad 2 on the substrate 1; 5, S102, a conductive film 5 is provided on the substrate 1, and the conductive film 5 is attached to the first pad 2; as shown in FIG. 6, S103, the second pad 4 of the chip 3 is attached to the conductive film 5; as shown in FIG. 7, S104, package the chip 3 and the conductive film 5 to form a packaged device.

在该实施例中,在基板1上设置第一焊盘2,用以连接芯片3的第二焊盘4;在基板1上设置导电膜5与第一焊盘2相贴合,设置导电膜5的方法可以为放置、粘贴或喷涂等方法,并将芯片3的第二焊盘4贴合于设置好的导电膜5上,实现芯片3的第二焊盘4与基板1上对应的第一焊盘2间的电连接;封装芯片3与导电膜5,封装后的芯片3与导电膜5牢牢固定于基板1上,以形成封装器件。该封装方法不使用引线和焊料,不需要对第一焊盘2和第二焊盘4使用焊料焊接,所以第一焊盘2和第二焊盘4的键合处不会出现键合丝损伤,也不会产生键合变形,加工过程中没有异物参与,进而保证键合面清洁。同时避免倒装焊技术处理时的高温处理步骤,芯片3和基板1都不会受热,避免了在热加载中产生大量热应力时芯片3位置发生摇摆偏移的情况,并且在封装器件为功率器件时,避免了由于功率器件发热量较大,长时间使用导致封装体6内积聚热量导致发生脱焊的情况。封装过程可为将多个与芯片3和导电膜5结合后的基板1放置于对应模具中进行注塑封装,封装过程可同时封装多个器件,以提升生产效率,在封装完成后,通过切割工序切割分离成多个独立的封装器件,即经一次封装工序可同时得到多个成品封装器件,进而增加产能。In this embodiment, a first pad 2 is provided on the substrate 1 to connect to the second pad 4 of the chip 3; a conductive film 5 is provided on the substrate 1 to be bonded to the first pad 2, and the conductive film 5 is provided. The method of 5 can be methods such as placement, sticking or spraying, and the second pad 4 of the chip 3 is pasted on the conductive film 5 that has been set, so that the second pad 4 of the chip 3 and the corresponding first pad 4 on the substrate 1 can be realized. An electrical connection between the pads 2; packaging the chip 3 and the conductive film 5, and the packaged chip 3 and the conductive film 5 are firmly fixed on the substrate 1 to form a packaged device. This packaging method does not use wires and solder, and does not need to use solder to weld the first pad 2 and the second pad 4, so the bond between the first pad 2 and the second pad 4 will not be damaged by the bonding wire , There will be no bonding deformation, and there is no foreign matter involved in the processing process, thereby ensuring that the bonding surface is clean. At the same time avoid the high-temperature processing steps during the flip-chip welding process, the chip 3 and the substrate 1 will not be heated, avoiding the situation where the position of the chip 3 swings and shifts when a large amount of thermal stress is generated during thermal loading, and the packaged device is power When using the device, it is avoided that the power device generates a large amount of heat, and the situation of desoldering due to heat accumulation in the package body 6 caused by long-term use is avoided. The packaging process can be to place multiple substrates 1 combined with chips 3 and conductive films 5 in corresponding molds for injection molding packaging. The packaging process can simultaneously package multiple devices to improve production efficiency. After the packaging is completed, through the cutting process Cutting and separating into multiple independent packaged devices, that is, multiple finished packaged devices can be obtained at the same time through one packaging process, thereby increasing production capacity.

在本发明的一个实施例中,优选地,如图9所示,封装器件的制造方法包括:如图3和图4所示,S201,在基板1上设置第一焊盘2;如图5所示,S202,在基板1上设置导电膜5,导电膜5与第一焊盘2相贴合;如图6所示,S203,将芯片3的第二焊盘4贴合于导电膜5上;S204,向芯片3施加第一预设压力,第一预设压力的方向与基板1垂直;如图7所示,S205,封装芯片3与导电膜5,以形成封装器件。In one embodiment of the present invention, preferably, as shown in FIG. 9, the manufacturing method of the packaged device includes: as shown in FIG. 3 and FIG. 4, S201, setting the first pad 2 on the substrate 1; As shown, S202, a conductive film 5 is provided on the substrate 1, and the conductive film 5 is bonded to the first pad 2; as shown in FIG. 6, S203, the second pad 4 of the chip 3 is bonded to the conductive film 5 Above; S204, apply a first preset pressure to the chip 3, the direction of the first preset pressure is perpendicular to the substrate 1; as shown in FIG. 7, S205, package the chip 3 and the conductive film 5 to form a packaged device.

在该实施例中,在基板1上设置第一焊盘2,用以连接芯片3的第二焊盘4;在基板1上设置导电膜5与第一焊盘2相贴合,并将芯片3的第二焊盘4贴合于导电膜5上,实现芯片3的第二焊盘4与基板1上对应的第一焊盘2间的电连接;封装芯片3与导电膜5,封装后的芯片3与导电膜5牢牢固定于基板1上,以形成封装器件。该封装方法不使用引线和焊料,不需要对第一焊盘2和第二焊盘4使用焊料焊接,所以第一焊盘2和第二焊盘4的键合处不会出现键合丝损伤,也不会产生键合变形,加工过程中没有异物参与,进而保证键合面清洁。同时避免倒装焊技术处理时的高温处理步骤,芯片3和基板1都不会受热,避免了在热加载中产生大量热应力时芯片3位置发生摇摆偏移的情况,并且在封装器件为功率器件时,避免了由于功率器件发热量较大,长时间使用导致封装体6内积聚热量导致发生脱焊的情况。同时封装过程可为多个芯片3与导电膜5和对应的多个基板1同时封装,以提升生产效率,在封装完成后,通过切割工序将多个封装好的封装器件分离成独立的封装器件,可进一步增加产能。In this embodiment, the first pad 2 is provided on the substrate 1 to connect the second pad 4 of the chip 3; the conductive film 5 is provided on the substrate 1 to be attached to the first pad 2, and the chip The second pad 4 of 3 is pasted on the conductive film 5 to realize the electrical connection between the second pad 4 of the chip 3 and the corresponding first pad 2 on the substrate 1; the chip 3 and the conductive film 5 are packaged. The chip 3 and the conductive film 5 are firmly fixed on the substrate 1 to form a packaged device. This packaging method does not use wires and solder, and does not need to use solder to weld the first pad 2 and the second pad 4, so the bond between the first pad 2 and the second pad 4 will not be damaged by the bonding wire , There will be no bonding deformation, and there is no foreign matter involved in the processing process, thereby ensuring that the bonding surface is clean. At the same time avoid the high-temperature processing steps during the flip-chip welding process, the chip 3 and the substrate 1 will not be heated, avoiding the situation where the position of the chip 3 swings and shifts when a large amount of thermal stress is generated during thermal loading, and the packaged device is power When using the device, it is avoided that the power device generates a large amount of heat, and the situation of desoldering due to heat accumulation in the package body 6 caused by long-term use is avoided. At the same time, the packaging process can package multiple chips 3, conductive films 5 and corresponding multiple substrates 1 at the same time to improve production efficiency. After the packaging is completed, multiple packaged packaged devices are separated into independent packaged devices through a cutting process. , can further increase production capacity.

向芯片3施加垂直于基板1的第一预设压力,第一预设压力小于会对芯片3造成损伤的最小压力,保证芯片3不会在封装过程中受损,同时使芯片3的第二焊盘4、导电膜5与基板1的第一焊盘2间贴合更加紧密,保证芯片3的第二焊盘4、导电膜5与基板1的第一焊盘2间电连接的可靠性。Apply a first preset pressure perpendicular to the substrate 1 to the chip 3, the first preset pressure is less than the minimum pressure that will cause damage to the chip 3, so as to ensure that the chip 3 will not be damaged during the packaging process, and at the same time make the second pressure of the chip 3 The pad 4, the conductive film 5 and the first pad 2 of the substrate 1 are more closely bonded to ensure the reliability of the electrical connection between the second pad 4 of the chip 3, the conductive film 5 and the first pad 2 of the substrate 1 .

在本发明的一个实施例中,优选地,如图10所示,封装器件的制造方法包括:如图3和图4所示,S301,在基板1上设置第一焊盘2;如图5所示,S302,在基板1上设置导电膜5,导电膜5与第一焊盘2相贴合;如图6所示,S303,将芯片3的第二焊盘4贴合于导电膜5上;如图7所示,S304,封装芯片3与导电膜5,以形成封装器件,S305,在基板1上设置第三焊盘7;如图1所示,S306,在第三焊盘7上设置焊料8。In one embodiment of the present invention, preferably, as shown in FIG. 10 , the manufacturing method of the packaged device includes: as shown in FIG. 3 and FIG. 4 , S301, setting the first pad 2 on the substrate 1; As shown, S302, a conductive film 5 is provided on the substrate 1, and the conductive film 5 is attached to the first pad 2; as shown in FIG. 6, S303, the second pad 4 of the chip 3 is attached to the conductive film 5 on; as shown in FIG. 7, S304, package the chip 3 and the conductive film 5 to form a packaged device, S305, set the third pad 7 on the substrate 1; as shown in FIG. 1, S306, install the third pad 7 Set solder 8 on.

在该实施例中,在基板1上设置第一焊盘2,用以连接芯片3的第二焊盘4;在基板1上设置导电膜5与第一焊盘2相贴合,并将芯片3的第二焊盘4贴合于导电膜5上,实现芯片3的第二焊盘4与基板1上对应的第一焊盘2间的电连接;封装芯片3与导电膜5,封装后的芯片3与导电膜5牢牢固定于基板1上,以形成封装器件。该封装方法不使用引线和焊料,不需要对第一焊盘2和第二焊盘4使用焊料焊接,所以第一焊盘2和第二焊盘4的键合处不会出现键合丝损伤,也不会产生键合变形,加工过程中没有异物参与,进而保证键合面清洁。同时避免倒装焊技术处理时的高温处理步骤,芯片3和基板1都不会受热,避免了在热加载中产生大量热应力时芯片3位置发生摇摆偏移的情况,并且在封装器件为功率器件时,避免了由于功率器件发热量较大,长时间使用导致封装体6内积聚热量导致发生脱焊的情况。同时封装过程可为多个芯片3与导电膜5和对应的多个基板1同时封装,以提升生产效率,在封装完成后,通过切割工序将多个封装好的封装器件分离成独立的封装器件,可进一步增加产能。In this embodiment, the first pad 2 is provided on the substrate 1 to connect the second pad 4 of the chip 3; the conductive film 5 is provided on the substrate 1 to be attached to the first pad 2, and the chip The second pad 4 of 3 is pasted on the conductive film 5 to realize the electrical connection between the second pad 4 of the chip 3 and the corresponding first pad 2 on the substrate 1; the chip 3 and the conductive film 5 are packaged. The chip 3 and the conductive film 5 are firmly fixed on the substrate 1 to form a packaged device. This packaging method does not use wires and solder, and does not need to use solder to weld the first pad 2 and the second pad 4, so the bond between the first pad 2 and the second pad 4 will not be damaged by the bonding wire , There will be no bonding deformation, and there is no foreign matter involved in the processing process, thereby ensuring that the bonding surface is clean. At the same time avoid the high-temperature processing steps during the flip-chip welding process, the chip 3 and the substrate 1 will not be heated, avoiding the situation where the position of the chip 3 swings and shifts when a large amount of thermal stress is generated during thermal loading, and the packaged device is power When using the device, it is avoided that the power device generates a large amount of heat, and the situation of desoldering due to heat accumulation in the package body 6 caused by long-term use is avoided. At the same time, the packaging process can package multiple chips 3, conductive films 5 and corresponding multiple substrates 1 at the same time to improve production efficiency. After the packaging is completed, multiple packaged packaged devices are separated into independent packaged devices through a cutting process. , can further increase production capacity.

在基板1上设置与第一焊盘2对应连接的第三焊盘7,实现芯片3的第二焊盘4与封装器件基板1的第三焊盘7间的电连接,并在第三焊盘7上设置焊料8,使封装器件的安装更加方便快捷。The third pad 7 correspondingly connected to the first pad 2 is provided on the substrate 1 to realize the electrical connection between the second pad 4 of the chip 3 and the third pad 7 of the packaging device substrate 1, and the third pad The solder 8 is arranged on the plate 7, so that the installation of the packaged device is more convenient and quick.

在本发明的一个实施例中,优选地,如图11所示,封装器件的制造方法包括:如图3和图4所示,S401,在基板1上设置第一焊盘2;如图5所示,S402,在基板1上设置导电膜5,导电膜5与第一焊盘2相贴合;如图6所示,S403,将芯片3的第二焊盘4贴合于导电膜5上;如图7所示,S404,封装芯片3与导电膜5,以形成封装器件,S405,修剪封装器件的毛边;S406,清洗封装器件。In one embodiment of the present invention, preferably, as shown in FIG. 11 , the manufacturing method of the packaged device includes: as shown in FIG. 3 and FIG. 4 , S401, setting the first pad 2 on the substrate 1; As shown, S402, a conductive film 5 is provided on the substrate 1, and the conductive film 5 is attached to the first pad 2; as shown in FIG. 6, S403, the second pad 4 of the chip 3 is attached to the conductive film 5 As shown in FIG. 7, S404, package the chip 3 and the conductive film 5 to form a packaged device, S405, trim the burrs of the packaged device; S406, clean the packaged device.

在该实施例中,在基板1上设置第一焊盘2,用以连接芯片3的第二焊盘4;在基板1上设置导电膜5与第一焊盘2相贴合,并将芯片3的第二焊盘4贴合于导电膜5上,实现芯片3的第二焊盘4与基板1上对应的第一焊盘2间的电连接;封装芯片3与导电膜5,封装后的芯片3与导电膜5牢牢固定于基板1上,以形成封装器件。该封装方法不使用引线和焊料,不需要对第一焊盘2和第二焊盘4使用焊料焊接,所以第一焊盘2和第二焊盘4的键合处不会出现键合丝损伤,也不会产生键合变形,加工过程中没有异物参与,进而保证键合面清洁。同时避免倒装焊技术处理时的高温处理步骤,芯片3和基板1都不会受热,避免了在热加载中产生大量热应力时芯片3位置发生摇摆偏移的情况,并且在封装器件为功率器件时,避免了由于功率器件发热量较大,长时间使用导致封装体6内积聚热量导致发生脱焊的情况。同时封装过程可为多个芯片3与导电膜5和对应的多个基板1同时封装,以提升生产效率,在封装完成后,通过切割工序将多个封装好的封装器件分离成独立的封装器件,可进一步增加产能。In this embodiment, the first pad 2 is provided on the substrate 1 to connect the second pad 4 of the chip 3; the conductive film 5 is provided on the substrate 1 to be attached to the first pad 2, and the chip The second pad 4 of 3 is pasted on the conductive film 5 to realize the electrical connection between the second pad 4 of the chip 3 and the corresponding first pad 2 on the substrate 1; the chip 3 and the conductive film 5 are packaged. The chip 3 and the conductive film 5 are firmly fixed on the substrate 1 to form a packaged device. This packaging method does not use wires and solder, and does not need to use solder to weld the first pad 2 and the second pad 4, so the bond between the first pad 2 and the second pad 4 will not be damaged by the bonding wire , There will be no bonding deformation, and there is no foreign matter involved in the processing process, thereby ensuring that the bonding surface is clean. At the same time avoid the high-temperature processing steps during the flip-chip welding process, the chip 3 and the substrate 1 will not be heated, avoiding the situation where the position of the chip 3 swings and shifts when a large amount of thermal stress is generated during thermal loading, and the packaged device is power When using the device, it is avoided that the power device generates a large amount of heat, and the situation of desoldering due to heat accumulation in the package body 6 caused by long-term use is avoided. At the same time, the packaging process can package multiple chips 3, conductive films 5 and corresponding multiple substrates 1 at the same time to improve production efficiency. After the packaging is completed, multiple packaged packaged devices are separated into independent packaged devices through a cutting process. , can further increase production capacity.

在封装芯片3与导电膜5,封装体6固化并分隔成独立的封装器件后,修剪封装器件的毛边并清洗封装器件,提升封装器件的做工品质,进一步提高用户对产品的满意度。After packaging the chip 3, the conductive film 5, and the package body 6 are solidified and separated into independent packaged devices, the burrs of the packaged devices are trimmed and the packaged devices are cleaned to improve the workmanship quality of the packaged devices and further improve the user's satisfaction with the product.

在本发明的描述中,术语“多个”则指两个或两个以上,除非另有明确的限定,术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制;术语“连接”、“安装”、“固定”等均应做广义理解,例如,“连接”可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是直接相连,也可以通过中间媒介相连。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明中的具体含义。In the description of the present invention, the term "plurality" refers to two or more than two. Unless otherwise clearly defined, the orientation or positional relationship indicated by the terms "upper", "lower" and so on is based on the orientation shown in the accompanying drawings. Orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, but does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as limiting the present invention; The terms "connection", "installation" and "fixation" should be understood in a broad sense, for example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or through an intermediate Media connected. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

在本发明的描述中,术语“一个实施例”、“一些实施例”、“具体实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或特点包含于本发明的至少一个实施例或示例中。在本发明中,对上述术语的示意性表述不一定指的是相同的实施例或实例。而且,描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。In the description of the present invention, descriptions of the terms "one embodiment", "some embodiments", "specific embodiments" and the like mean that a specific feature, structure, material or characteristic described in connection with the embodiment or example is included in the present invention In at least one embodiment or example of . In the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (14)

1.一种封装器件,其特征在于,包括:1. A packaging device, characterized in that, comprising: 基板,所述基板的一侧设置有第一焊盘;a substrate, one side of the substrate is provided with a first pad; 芯片,所述芯片包括第二焊盘;a chip including a second pad; 导电膜,所述导电膜的一侧与所述第一焊盘相贴合,所述导电膜的另一侧与所述第二焊盘相贴合,所述第一焊盘与所述第二焊盘相对设置;A conductive film, one side of the conductive film is attached to the first pad, the other side of the conductive film is attached to the second pad, and the first pad is attached to the second pad. The two pads are set relative to each other; 封装体,所述封装体至少包覆于所述芯片与所述导电膜的外侧。A packaging body, the packaging body at least covers the outside of the chip and the conductive film. 2.根据权利要求1所述的封装器件,其特征在于,所述导电膜包括:2. The packaged device according to claim 1, wherein the conductive film comprises: 绝缘载体;insulating carrier; 导电体,所述导电体沿所述绝缘载体的厚度方向延伸。A conductor, the conductor extending along the thickness direction of the insulating carrier. 3.根据权利要求2所述的封装器件,其特征在于,3. The packaged device according to claim 2, characterized in that, 多个所述导电体呈阵列式分布于所述绝缘载体上。A plurality of the conductors are distributed in an array on the insulating carrier. 4.根据权利要求3所述的封装器件,其特征在于,4. The packaged device according to claim 3, characterized in that, 所述第一焊盘为多个,所述第二焊盘的数量与所述第一焊盘的数量相等;There are multiple first pads, and the number of the second pads is equal to the number of the first pads; 所述导电体的横截面的任一宽度均小于相邻的第一焊盘之间的距离;和/或Any width of the cross-section of the conductor is smaller than the distance between adjacent first pads; and/or 所述导电体的横截面的任一宽度均小于相邻的第二焊盘之间的距离。Any width of the cross-section of the conductor is smaller than the distance between adjacent second pads. 5.根据权利要求3所述的封装器件,其特征在于,5. The packaged device according to claim 3, characterized in that, 所述第一焊盘与所述第二焊盘直接设置有一个或多个所述导电体。The first pad and the second pad are directly provided with one or more conductors. 6.根据权利要求1所述的封装器件,其特征在于,还包括:6. The packaging device according to claim 1, further comprising: 第三焊盘,所述第三焊盘设置在所述基板的另一侧,与所述第一焊盘相连接。A third pad, the third pad is disposed on the other side of the substrate and connected to the first pad. 7.根据权利要求6所述的封装器件,其特征在于,还包括:7. The packaging device according to claim 6, further comprising: 焊料,所述焊料设置在所述第三焊盘上。solder, and the solder is disposed on the third pad. 8.根据权利要求7所述的封装器件,其特征在于,8. The packaged device according to claim 7, characterized in that, 所述焊料为锡焊料或钎焊料。The solder is tin solder or brazing material. 9.根据权利要求1至8中任一项所述的封装器件,其特征在于,9. The packaged device according to any one of claims 1 to 8, characterized in that, 所述第一焊盘嵌于所述基板中,以使所述第一焊盘的表面与所述基板的表面平齐。The first pad is embedded in the substrate, so that the surface of the first pad is flush with the surface of the substrate. 10.根据权利要求1至8中任一项所述的封装器件,其特征在于,10. The packaged device according to any one of claims 1 to 8, characterized in that, 所述基板为陶瓷基板或PCB板。The substrate is a ceramic substrate or a PCB. 11.一种封装器件的制造方法,其特征在于,包括:11. A method of manufacturing a packaged device, comprising: 在基板上设置第一焊盘;setting a first pad on the substrate; 在所述基板上设置导电膜,所述导电膜与所述第一焊盘相贴合;disposing a conductive film on the substrate, the conductive film is bonded to the first pad; 将芯片的第二焊盘贴合于所述导电膜上;Bonding the second pad of the chip on the conductive film; 封装所述芯片与所述导电膜,以形成封装器件。The chip and the conductive film are packaged to form a packaged device. 12.根据权利要求11所述的封装器件的制造方法,其特征在于,在所述将芯片的第二焊盘贴合于所述导电膜上,与所述封装所述芯片与所述导电膜,以形成封装器件之间,所述封装器件的制造方法还包括:12. The manufacturing method of a packaged device according to claim 11, characterized in that, in the bonding of the second pad of the chip on the conductive film, and the packaging of the chip and the conductive film , to form between packaged devices, the manufacturing method of said packaged device also includes: 向所述芯片施加第一预设压力,所述第一预设压力的方向与所述基板垂直。A first preset pressure is applied to the chip, and the direction of the first preset pressure is perpendicular to the substrate. 13.根据权利要求11所述的封装器件的制造方法,其特征在于,在所述封装所述芯片与所述导电膜,以形成封装器件之后,所述封装器件的制造方法还包括:13. The method for manufacturing a packaged device according to claim 11, characterized in that, after the packaging of the chip and the conductive film to form a packaged device, the method for manufacturing the packaged device further comprises: 在所述基板上设置第三焊盘;setting a third pad on the substrate; 在所述第三焊盘上设置焊料。Solder is provided on the third pad. 14.根据权利要求11至13中任一项所述的封装器件的制造方法,其特征在于,在所述封装所述芯片与所述导电膜,以形成封装器件之后,所述封装器件的制造方法还包括:14. The manufacturing method of a packaged device according to any one of claims 11 to 13, characterized in that, after said packaging said chip and said conductive film to form a packaged device, said packaged device is manufactured Methods also include: 修剪所述封装器件的毛边;trimming the burrs of the packaged device; 清洗所述封装器件。The packaged device is cleaned.
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