CN108269812B - An optimized chip-scale packaging process method - Google Patents
An optimized chip-scale packaging process method Download PDFInfo
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- CN108269812B CN108269812B CN201711388186.2A CN201711388186A CN108269812B CN 108269812 B CN108269812 B CN 108269812B CN 201711388186 A CN201711388186 A CN 201711388186A CN 108269812 B CN108269812 B CN 108269812B
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- wafer
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- trench structure
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- groove structure
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000012858 packaging process Methods 0.000 title claims abstract 5
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 238000001459 lithography Methods 0.000 claims description 20
- 238000005538 encapsulation Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims 4
- 238000000059 patterning Methods 0.000 claims 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005457 optimization Methods 0.000 description 5
- 238000005286 illumination Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
- H10F39/026—Wafer-level processing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/199—Back-illuminated image sensors
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- Solid State Image Pick-Up Elements (AREA)
Abstract
本发明提供了一种优化的芯片级封装工艺方法，其中，提供一第一晶圆，包括以下步骤：于第一晶圆表面形成第一沟槽结构；于第一晶圆表面形成第二沟槽结构；对第一沟槽结构和第二沟槽结构进行填充；对填充后的第一晶圆表面进行平坦化，至露出第一晶圆表面；于第一晶圆表面形成焊盘结构；将第一晶圆形成有焊盘结构的一面与一第二晶圆相键合；对第一晶圆减薄一预定厚度；于减薄后的第一晶圆表面引出金属线，进行后续封装工艺；有益效果：使用新的工艺后，可以完全屏蔽后续封装工艺金属引线对器件的影响，简化当前的工艺流程，从而减少多道工艺流程，提高产品的可靠性。
The present invention provides an optimized chip-level packaging process method, wherein a first wafer is provided, including the following steps: forming a first trench structure on the surface of the first wafer; forming a second trench on the surface of the first wafer groove structure; filling the first groove structure and the second groove structure; flattening the filled first wafer surface to expose the first wafer surface; forming a pad structure on the first wafer surface; Bonding the side of the first wafer with the pad structure to a second wafer; thinning the first wafer to a predetermined thickness; drawing out metal wires on the surface of the thinned first wafer for subsequent packaging Process; beneficial effect: After using the new process, the influence of the metal leads of the subsequent packaging process on the device can be completely shielded, and the current process flow is simplified, thereby reducing the multi-process process and improving the reliability of the product.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of wafer-level package processes of optimization.
Background technique
As former back-illuminated type (Back Side Illumination, BSI) sensor CSP (Chip Scale
Package, wafer-level package) packaging technology is to do metal wire pin from carrying silicon wafer face.Use pad made of prior art
Structural schematic diagram as illustrated in figs. 1A and ib, including silicon base 11, shallow trench 12, metal pad 13, oxide skin(coating) 14.To ensure
Metal wire can export completely, and deep hole can penetrate the pad (BSI BOND PAD) of device (device) chip and backside-illuminated sensor
And stop on top of the encapsulation material, because of the thickness that depth is isolated only less than the depth of 0.3um, after subsequent device is thinned in device trenches
Greater than 2um, much larger than the thickness of groove, this results in package metals lead that can contact Si, has potential shadow to device reliability
It rings, needs to be dedicated to process optimization to improve product quality；
In addition, stop on top of the encapsulation material because deep hole can penetrate the pad of device chip and backside-illuminated sensor,
The technique that device metal lead is exported and be connected to by backside-illuminated sensor just seems somewhat extra.
Summary of the invention
In view of the above-mentioned problems, the present invention provides a kind of wafer-level package processes of optimization, wherein provide one first
Wafer, comprising the following steps:
Step S1 forms first groove structure in first crystal column surface；
Step S2 forms second groove structure in first crystal column surface；
Step S3 is filled the first groove structure and the second groove structure；
Step S4 planarizes filled first crystal column surface, until exposing first crystal column surface；
Step S5 forms pad structure in first crystal column surface；
The one side that first wafer is formed with the pad structure is mutually bonded by step S6 with one second wafer；
A predetermined thickness is thinned to first wafer in step S7；
Step S8, first crystal column surface after being thinned draw metal wire.
Wherein, the step of forming the first groove in the step S1 are as follows:
Step S11 forms one first lithography layer in first crystal column surface, patterns first lithography layer, Yu Yi
Predetermined position formation process window；
Step S12 performs etching first wafer by first lithography layer, stays in first wafer
One first predetermined depth；
Step S13 removes first lithography layer, forms the first groove structure.
Wherein, the step of forming the second groove structure in the step S2 are as follows:
Step S21 forms one second lithography layer in first crystal column surface, patterns second lithography layer, Yu Yi
Predetermined position formation process window；
Step S22 performs etching first wafer by second lithography layer, stays in first wafer
One second predetermined depth；
Step S23 removes second lithography layer, forms the second groove structure.
Wherein, first predetermined depth is less than second predetermined depth.
Wherein, it is filled in the step 3 by depositing an oxide layer.
Wherein, the depth of the first groove structure is not more than 0.3 micron.
It wherein, further include carrying out subsequent encapsulation step after the step S8.
Wherein, the second groove structure is formed in the side of the first groove structure.
Wherein, the method is suitable for back side illumination image sensor.
The utility model has the advantages that influence of the subsequent encapsulating process metal lead wire to device can be shielded completely after using new technique,
Simplify current process flow and improves the reliability of product to reduce multiple tracks process flow.
Detailed description of the invention
The sectional view for the structure that Fig. 1 a prior art is formed；
The top view for the structure that Fig. 1 b prior art is formed；
Fig. 2 encapsulate in the prior art after structure sectional view；
The sectional view for the structure that Fig. 3 a present invention is formed；
The top view for the structure that Fig. 3 b present invention is formed；
Sectional view after the construction packages that Fig. 4 present invention is formed；
Fig. 5 general flow chart of the present invention；
The flow chart of Fig. 6 present invention formation first groove structure；
The flow chart of Fig. 7 present invention formation second groove structure.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
As shown in figure 5, proposing a kind of wafer-level package process of optimization, wherein provide one first wafer 31, packet
Include following steps:
Step S1 forms first groove structure 32 in 31 surface of the first wafer；
Step S2 forms second groove structure 33 in 31 surface of the first wafer；
Step S3 is filled the first groove structure 32 and the second groove structure 33；
Step S4 planarizes filled first wafer, 31 surface, until exposing 31 table of the first wafer
Face forms structure as shown in Figure 3a and Figure 3b shows；
Step S5 forms pad structure in 31 surface of the first wafer；
The one side that first wafer 31 is formed with the pad structure is mutually bonded by step S6 with one second wafer；
A predetermined thickness is thinned to first wafer 31 in step S7；
Metal wire is drawn on step S8,31 surface of the first wafer after being thinned.
Above-mentioned technical proposal can shield influence of the subsequent encapsulating process metal lead wire to device completely, simplify current work
Skill process improves the reliability of product to reduce multiple tracks process flow.
In a preferred embodiment, as shown in fig. 6, the step of forming first groove 32 in the step S1
Are as follows:
Step S11 forms one first lithography layer in 31 surface of the first wafer, patterns first lithography layer, in
One predetermined position formation process window；
Step S12 performs etching first wafer 31 by first lithography layer, stays in first wafer
One first predetermined depth in 1；
Step S13 removes first lithography layer, forms the first groove structure 32.
In a preferred embodiment, as shown in fig. 7, forming the step of the second groove structure 33 in the step S2
Suddenly are as follows:
Step S21 forms one second lithography layer in 31 surface of the first wafer, patterns second lithography layer, in
One predetermined position formation process window；
Step S22 performs etching first wafer 31 by second lithography layer, stays in first wafer
One second predetermined depth in 31；
Step S23 removes second lithography layer, forms the second groove structure 33.
In a preferred embodiment, the first predetermined depth is less than the second predetermined depth, i.e. first groove structure 32
Depth is less than the depth of second groove structure 33.
There are differences in height can guarantee preferably isolation effect between two kinds of groove structures in above-mentioned technical proposal.
In a preferred embodiment, it is filled in the step 3 by depositing an oxide layer.
In above-mentioned technical proposal, isolation effect can be better ensured that by being filled using an oxide layer.
In a preferred embodiment, the depth of the first groove structure is not more than 0.3 micron.
It in a preferred embodiment, further include carrying out subsequent encapsulation step after the step S8.
In above-mentioned technical proposal, subsequent encapsulation step is technological means commonly used in the art, therefore is not described here in detail.
In a preferred embodiment, the second groove structure is formed in the side of the first groove structure.
In above-mentioned technical proposal, there are differences in height can play better isolation effect with first groove for second groove.
In a preferred embodiment, the method is suitable for back side illumination image sensor.
In above-mentioned technical proposal, as shown in Figure 2 and Figure 4, the sensor sectional view after making, encapsulating according to the method for the present invention
Significant difference is had no with the sensor sectional view of prior art production, encapsulation.
In above-mentioned technical proposal, method of the invention reduces multiple steps on the basis of existing technology, is reaching phase
In the case where with purpose, manufacturing cost is greatly saved.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711388186.2A CN108269812B (en) | 2017-12-20 | 2017-12-20 | An optimized chip-scale packaging process method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711388186.2A CN108269812B (en) | 2017-12-20 | 2017-12-20 | An optimized chip-scale packaging process method |
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| Publication Number | Publication Date |
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| CN108269812A CN108269812A (en) | 2018-07-10 |
| CN108269812B true CN108269812B (en) | 2019-02-15 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100385621C (en) * | 2004-02-17 | 2008-04-30 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN101800233A (en) * | 2009-02-10 | 2010-08-11 | 索尼公司 | Solid-state imaging device, manufacturing method thereof, and electronic device |
| CN104658976A (en) * | 2013-11-15 | 2015-05-27 | 三星钻石工业股份有限公司 | Dividing method and dividing apparatus for wafer laminated body |
-
2017
- 2017-12-20 CN CN201711388186.2A patent/CN108269812B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100385621C (en) * | 2004-02-17 | 2008-04-30 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN101800233A (en) * | 2009-02-10 | 2010-08-11 | 索尼公司 | Solid-state imaging device, manufacturing method thereof, and electronic device |
| CN104658976A (en) * | 2013-11-15 | 2015-05-27 | 三星钻石工业股份有限公司 | Dividing method and dividing apparatus for wafer laminated body |
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| Publication number | Publication date |
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| CN108269812A (en) | 2018-07-10 |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |