CN108269802B - Carbon nano tube beam field effect transistor array and manufacturing method thereof - Google Patents

Abstract

The present invention provides a carbon nanotube bundle field effect transistor array and a manufacturing method thereof. The carbon nanotube bundle field effect transistor array comprises: a source material layer, a drain material layer, and a material connected to the source material layer and the drain material. A carbon nanotube bundle array between layers; the carbon nanotube bundle array includes several discretely arranged carbon nanotube bundle units, wherein the axial first end of the carbon nanotube bundle unit is connected to the source material layer, and the The second axial end of the carbon nanotube bundle unit is connected with the drain material layer; the carbon nanotube bundle unit is surrounded by the grid structure. The carbon nanotube bundle field effect transistor array of the present invention can withstand higher operating voltage and operating current, and can be applied to high-power devices. Moreover, the present invention adopts the gate-all-around structure, which can improve the control ability of the gate to the channel. The manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention has the characteristics of simple process steps, which is beneficial to reduce the production cost.

Description

A kind of carbon nanotube bundle field effect transistor array and its manufacturing method

technical field

The invention belongs to the technical field of integrated circuits, and relates to a carbon nanotube bundle field effect transistor array and a manufacturing method thereof.

Background technique

For carrier transport media, vacuum is inherently superior to solids because it allows ballistic transport, whereas in semiconductors, carriers suffer from optical and acoustic phonon scattering. The electron velocity in a vacuum is theoretically 3×10 ¹⁰ cm/s, but in a semiconductor, the electron velocity is only about 5×10 ⁷ cm/s. Some scientists believe that in vacuum transistors, it seems that only electrons can flow between electrodes, not holes. Unless we learn to deal with positrons, it will be impossible to do any complementary circuits, such as CMOS. Without complementary circuits, the power would be too high, most likely limiting the entry of vacuum transistors into the market segment. It is hard to imagine that any large digital circuit would use vacuum transistors.

There are currently four main types of vacuum transistors (Jin-Woo Han, Jae Sub Oh and M. Meyyappan, Vacuum Nanoelectronics: Back to the Future?-Gate insulated nanoscale vacuumchannel transistor, APL, 100, 213505 (2012)): (a) Vertical field emission type, (b) planar lateral field emission type, (c) MOSFET type, (d) insulated gate air channel transistor.

In recent years, reports have disclosed that the self-aligned gate size of carbon nanotube field effect transistors (CNTFETs) can be scaled down to 20 nanometers with ideal gate-around geometry (IBM created the first 9nm carbon nanotube transistors) , by Gareth Halfacree on January 30, 2012). The uniformity of the gate surrounding the carbon nanotube channel has been demonstrated, and the process does not damage the carbon nanotubes. In addition, using a suitable gate dielectric layer, an N-type transistor or a P-type transistor can be realized, wherein, an N-type transistor can be realized by using HfO ₂ as the gate dielectric layer, and a P-type transistor can be realized by using Al ₂ O ₃ as the gate dielectric layer ( Aaron D. Franklin, Carbon Nanotube Complementary Wrap-Gate Transistors, Nano Lett., 2013, 13(6), pp 2490–2495). These findings not only provide a promising platform for further research on gated carbon nanotube devices, but also demonstrate the realistic technological potential of large-scale digital switches employing carbon nanotubes.

However, there is still a need to exploit the potential and possibilities of CNTFETs for the fabrication of high-power devices with high operating voltages and high drive currents.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a carbon nanotube bundle field effect transistor array and a manufacturing method thereof, which are used to solve the problem that carbon nanotube field effect transistors in the prior art cannot be applied to high-power devices. question.

To achieve the above purpose and other related purposes, the present invention provides a carbon nanotube bundle field effect transistor array, comprising:

source material layer;

a drain material layer formed above the source material layer;

A carbon nanotube bundle array, connected between the source material layer and the drain material layer; the carbon nanotube bundle array includes a number of discretely arranged carbon nanotube bundle units, wherein the axial direction of the carbon nanotube bundle unit The first end is connected to the source material layer, and the axial second end of the carbon nanotube bundle unit is connected to the drain material layer;

A gate structure is formed between each carbon nanotube bundle unit in the carbon nanotube bundle array, and the gate structure is isolated from the source material layer by a first insulating layer, and the gate structure is connected to the source material layer. The drain material layers are separated by a second insulating layer; wherein, the gate structure includes a gate dielectric layer and a gate material layer, and the gate dielectric layer surrounds the outer side surface of the carbon nanotube bundle unit, so The gate material layer surrounds the outer side surface of the gate material layer.

Optionally, the carbon nanotube bundle field effect transistor array further includes a substrate and a third insulating layer formed on the substrate, and the source material layer is formed on the third insulating layer.

Optionally, the angle between the axial direction of the carbon nanotube bundle unit and the plane where the source material layer is located is 80°˜100°.

Optionally, the height of the carbon nanotube bundle unit is greater than 100 μm.

Optionally, the gate dielectric layer adopts a high-K dielectric, and the gate material layer includes a metal material.

Optionally, both the source material layer and the drain material layer include metal materials.

The present invention also provides a method for manufacturing a carbon nanotube bundle field effect transistor array, comprising the following steps:

S1: providing a substrate, and sequentially forming a third insulating layer, a source material layer and a first insulating layer on the substrate;

S2: forming a through hole array in the first insulating layer; the through hole array includes a plurality of discrete through holes, and the through holes expose the upper surface of the source material layer;

S3: forming a carbon nanotube bundle array based on the through hole array; the carbon nanotube bundle array includes a plurality of carbon nanotube bundle units corresponding to the positions of the through holes, wherein the axial first end of the carbon nanotube bundle unit connected with the source material layer;

S4: forming a gate dielectric layer covering the outer side surface of the carbon nanotube bundle unit;

S5: forming a gate material layer covering the outer side surface of the gate dielectric layer;

S6: forming a second insulating layer and a drain material layer in sequence, wherein the axial second end of the carbon nanotube bundle unit is connected to the drain material layer, and the gate dielectric layer and the gate material layer are connected to the drain material layer. The drain material layers are isolated by a second insulating layer.

Optionally, in the step S3, in a protective atmosphere, the carbon nanotube bundle array is formed by a chemical vapor deposition method using a catalyst and a carbon source.

Optionally, the protective atmosphere includes one or more of N ₂ , H ₂ , and Ar, the catalyst includes one or more of Fe, Ni, and Co, and the growth of the carbon nanotube bundle array The temperature range is 500 to 740°C.

Optionally, firstly, the catalyst is formed on the upper surface of the source material layer based on the through hole array, and then the carbon nanotube bundle array is grown based on the catalyst.

Optionally, a solution containing catalyst ions is applied to the surface of the source material layer and annealed to increase the bonding strength of the catalyst ions and the source material layer.

Optionally, the temperature range of the annealing is 700˜900° C., and the annealing time is 30˜90 min.

Optionally, it also includes the step of removing excess catalyst ions on the surface of the second insulating layer.

Optionally, excess catalyst ions on the surface of the second insulating layer are removed by wet etching.

Optionally, the angle between the axial direction of the carbon nanotube bundle unit and the plane where the source material layer is located is 80°˜100°.

Optionally, the height of the carbon nanotube bundle unit is greater than 100 μm.

As mentioned above, the carbon nanotube bundle field effect transistor array of the present invention and the manufacturing method thereof have the following beneficial effects: the carbon nanotube bundle field effect transistor array of the present invention adopts carbon nanotube bundles as channel materials, wherein the carbon nanotube bundle unit has only external The carbon nanotubes are surrounded by the gate dielectric layer, and the inner carbon nanotubes are not surrounded by the gate dielectric layer, but due to the interaction between the carbon nanotubes in the carbon nanotube bundle, they are inside the carbon nanotube bundle unit. The carbon nanotubes can still play an effective role. The carbon nanotube bundle field effect transistor array of the present invention can withstand higher operating voltage and operating current, and can be applied to high-power devices. Moreover, the present invention adopts the gate-all-around structure, which can improve the control ability of the gate to the channel. The manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention has the characteristics of simple process steps, which is beneficial to reduce the production cost.

Description of drawings

FIG. 1 is a schematic diagram showing the structure of the carbon nanotube bundle field effect transistor array of the present invention.

FIG. 2 is a schematic diagram of sequentially forming a third insulating layer, a source material layer and a first insulating layer on the substrate according to the method for manufacturing a carbon nanotube bundle field effect transistor array of the present invention.

FIG. 3 is a schematic diagram illustrating the formation of a through hole array in the first insulating layer according to the manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention.

FIG. 4 is a schematic diagram showing the formation of the catalyst on the upper surface of the source material layer based on the through hole array in the manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention.

FIG. 5 shows a schematic diagram of growing the carbon nanotube bundle array based on the catalyst in the manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention.

FIG. 6 is a schematic diagram of forming a gate dielectric layer covering the outer side surface of the carbon nanotube bundle unit according to the manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention.

FIG. 7 is a schematic diagram of forming a gate material layer covering the outer side surface of the gate dielectric layer by the method for manufacturing a carbon nanotube bundle field effect transistor array of the present invention.

FIG. 8 is a schematic diagram of removing part of the gate dielectric layer and the gate material layer to expose the upper part of the carbon nanotube bundle array according to the manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention.

FIG. 9 is a schematic diagram illustrating the formation of the second insulating layer and the drain material layer in the method for manufacturing the carbon nanotube bundle field effect transistor array of the present invention.

Component label description

101 Substrate

102 The third insulating layer

103 Source material layer

104 first insulating layer

105 carbon nanotube bundle units

106 gate dielectric layer

107 Gate Material Layer

108 Second insulating layer

109 Drain material layer

110 through hole

111 Catalyst

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 to 9. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

Example 1

The present invention provides a carbon nanotube bundle field effect transistor array. Please refer to FIG. 1 , which is a schematic structural diagram of the carbon nanotube bundle field effect transistor array, including:

source material layer 103;

The drain material layer 109 is formed above the source material layer 103;

A carbon nanotube bundle array, connected between the source material layer 103 and the drain material layer 109; the carbon nanotube bundle array includes a number of discrete carbon nanotube bundle units 105, wherein the carbon nanotube bundle units The first axial end of 105 is connected to the source material layer 103, and the axial second end of the carbon nanotube bundle unit 105 is connected to the drain material layer 109;

The gate structure is formed between each carbon nanotube bundle unit 105 in the carbon nanotube bundle array, and the gate structure and the source material layer 103 are isolated by the first insulating layer 104, and the gate The structure is isolated from the drain material layer 109 by a second insulating layer 108; wherein, the gate structure includes a gate dielectric layer 106 and a gate material layer 107, and the gate dielectric layer 106 surrounds the carbon On the outer side of the nanotube bundle unit 105 , the gate material layer 107 surrounds the outer side of the gate material layer 107 .

In this embodiment, the carbon nanotube bundle field effect transistor array further includes a substrate 101 and a third insulating layer 102 formed on the substrate 101 , and the source material layer 103 is formed on the third insulating layer 102 .

Specifically, the substrate 101 includes but is not limited to conventional semiconductor substrate materials such as Si and Ge. The third insulating layer 102 can be made of silicon oxide or other insulating materials for isolating the source material layer 103 from the substrate 101 .

Specifically, each carbon nanotube bundle unit 105 is used as a channel material of a field effect transistor, and two axial ends thereof are respectively connected to the source material layer 103 and the drain material layer 109 . The source material layer 103 serves as the N+ type source electrode of the carbon nanotube bundle field effect transistor, and the drain material layer 109 serves as the N+ type drain electrode of the carbon nanotube bundle field effect transistor.

In this embodiment, the height of the carbon nanotube bundle unit 105 is greater than 100 μm. The angle between the axial direction of the carbon nanotube bundle unit 105 and the plane where the source material layer 103 is located is 80°˜100°, preferably 90°. In other words, the axial direction of the carbon nanotube bundle unit 105 is perpendicular to, or substantially perpendicular to, the plane where the source material layer 103 is located.

Specifically, the carbon nanotube bundle unit 105 is composed of a plurality of carbon nanotubes, wherein, only the carbon nanotubes located at the periphery of the carbon nanotube bundle are partially or completely surrounded by the gate dielectric layer 106, and are located inside the carbon nanotube bundle. The carbon nanotubes are not surrounded by the gate dielectric layer 106, but due to the interaction between the carbon nanotubes in the carbon nanotube bundle, the carbon nanotubes inside the carbon nanotube bundle unit 105 can still play an effective role. Compared with a single carbon nanotube as a channel, the present invention adopts a carbon nanotube bundle containing a plurality of carbon nanotubes as a channel material, so that the carbon nanotube bundle field effect transistor array can withstand higher operating voltage and operating current, thereby Can be applied to high power devices.

In the present invention, since the gate dielectric layer 106 surrounds the outer side of the carbon nanotube bundle unit 105, the gate material layer 107 surrounds the outer side of the gate material layer 107, so that the gate structure constitutes The gate-all-around structure can improve the control ability of the gate to the carbon nanotube bundle channel.

As an example, in the gate structure, the gate dielectric layer 106 adopts a high-K dielectric (a dielectric constant higher than 3.9 of silicon dioxide), such as hafnium-based oxide, HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO etc., or other dielectric materials. The gate material layer 107 adopts a metal gate, which includes a metal material, such as any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo or an alloy thereof. any of the .

As an example, both the source material layer 103 and the drain material layer 109 also include metal materials, such as any of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, and Mo. one or any of its alloys.

The carbon nanotube bundle field effect transistor array of the present invention adopts carbon nanotube bundles as channel materials and adopts a gate-all-around structure, which can not only be applied to high-power devices, but also has strong channel control capability.

Embodiment 2

The present invention also provides a method for manufacturing a carbon nanotube bundle field effect transistor array, comprising the following steps:

Referring first to FIG. 2 , step S1 is performed: a substrate 101 is provided, and a third insulating layer 102 , a source material layer 103 and a first insulating layer 104 are sequentially formed on the substrate 101 .

Specifically, the substrate 101 includes but is not limited to conventional semiconductor substrate materials such as Si and Ge. The third insulating layer 102 is made of silicon oxide or other insulating materials for isolating the source material layer 103 from the substrate 101 . The source material layer 103 includes a metal material, for example, any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo or any alloy thereof. The first insulating layer 104 is made of silicon oxide or other insulating materials.

The third insulating layer 102, the source material layer 103, and the first insulating layer 104 may be formed by physical vapor deposition or chemical vapor deposition.

Then referring to FIG. 3 , step S2 is performed: forming a via array in the first insulating layer 104 ; the via array includes a plurality of discrete vias 110 , and the vias 110 expose the source material Layer 103 upper surface.

Specifically, the through hole array is formed by photolithography, etching and other process steps. The shape of the through hole 110 includes, but is not limited to, a polygon, a circle, an ellipse, and the like.

Next, referring to FIGS. 4-5 , step S3 is performed: forming a carbon nanotube bundle array based on the through hole array; the carbon nanotube bundle array includes a plurality of carbon nanotube bundle units 105 corresponding to the positions of the through holes 110 , wherein , the axial first end of the carbon nanotube bundle unit 105 is connected to the source material layer 103 .

Specifically, each through hole 110 corresponds to one carbon nanotube bundle unit 105, and each carbon nanotube bundle unit 105 serves as a channel material of a field effect transistor.

In this embodiment, in a protective atmosphere, the carbon nanotube bundle array is formed by chemical vapor deposition using a catalyst and a carbon source. The protective atmosphere includes one or more of N ₂ , H ₂ , and Ar, the carbon source includes but is not limited to carbon-containing gases such as methane and acetylene, and the catalyst includes one of Fe, Ni, and Co. Or more, the growth temperature range of the carbon nanotube bundle array is 500-740°C.

Specifically, as shown in FIG. 4 , the catalyst 111 is first formed on the upper surface of the source material layer 103 based on the through hole array. As an example, a solution containing catalyst ions is applied to the surface of the source material layer 103 to form the catalyst 111 . In this embodiment, the step of annealing is further included to increase the bonding strength of the catalyst ions and the source material layer 103 . The temperature range of the annealing is 700˜900° C., and the annealing time is 30˜90 min.

Further, after the annealing, the step of removing excess catalyst ions on the surface of the second insulating layer 104 is also included. As an example, excess catalyst ions on the surface of the second insulating layer 104 are removed by wet etching.

As shown in FIG. 5 , the carbon nanotube bundle array is then grown based on the catalyst 111 . In this embodiment, the angle between the axial direction of the carbon nanotube bundle unit 105 and the plane where the source material layer 103 is located is 80°˜100°, preferably 90°. In other words, the axial direction of the carbon nanotube bundle unit 105 is perpendicular to, or substantially perpendicular to, the plane where the source material layer 103 is located.

As an example, the treated substrate is placed in a reaction furnace, heated to 500°C to 740°C in a protective gas environment, and then a carbon source gas is introduced and reacted for about 5 to 30 minutes to grow a carbon nanotube bundle array with a height of greater than 100 microns. The carbon nanotube bundle array is a pure carbon nanotube bundle array formed by a plurality of carbon nanotubes grown parallel to each other and perpendicular to the substrate. The carbon nanotube bundle has substantially the same area as the through hole. By controlling the growth conditions above, the super-aligned carbon nanotube bundle array basically does not contain impurities such as amorphous carbon or residual catalyst metal particles.

Referring to FIG. 6 again, step S4 is performed: forming a gate dielectric layer 106 covering the outer side surface of the carbon nanotube bundle unit 105 .

Specifically, the gate dielectric layer 106 is formed by using a physical vapor deposition method or a chemical vapor deposition method. As an example, the gate dielectric layer 106 adopts a high-K dielectric (a dielectric constant higher than 3.9 of silicon dioxide), such as hafnium-based oxide, HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, etc., or other dielectric materials .

Referring to FIG. 7 again, step S5 is performed: forming a gate material layer 107 covering the outer side surface of the gate dielectric layer 106 .

Specifically, the gate material layer 107 is formed by using a physical vapor deposition method or a chemical vapor deposition method. As an example, the gate material layer 107 adopts a metal gate, which includes a metal material, such as any one of Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co, W, Mo, or any of its alloys.

Further, as shown in FIG. 8 , part of the gate material layer 107 and the gate dielectric layer 106 are removed to expose the upper part of the carbon nanotube bundle array. The removal method may be a suitable method such as wet etching or plasma etching.

Finally, referring to FIG. 9 , step S6 is performed: forming a second insulating layer 108 and a drain material layer 109 in sequence, wherein the axial second end of the carbon nanotube bundle unit 105 is connected to the drain material layer 109 , so The gate dielectric layer 106 and the gate material layer 107 are isolated from the drain material layer 109 by a second insulating layer 108 .

Specifically, the second insulating layer 108 is made of silicon oxide or other insulating materials, and the drain material layer 109 includes metal materials, such as Ti, Ta, Hf, Ni, Ru, Ir, Au, Pt, Al, Co , any one of W, Mo or any one of its alloys.

Specifically, the top of the carbon nanotube bundle unit 105 is embedded in the drain material layer 109 , which can increase the firmness of the connection between the carbon nanotube bundle unit 105 and the drain material layer 109 .

So far, the carbon nanotube bundle field effect transistor array of the present invention is completed. The manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention has the characteristics of simple process steps, which is beneficial to reduce the production cost.

To sum up, the carbon nanotube bundle field effect transistor array of the present invention uses carbon nanotube bundles as channel materials, wherein only the outer carbon nanotubes of the carbon nanotube bundle unit are surrounded by the gate dielectric layer, and the inner carbon nanotubes are not It is not surrounded by the gate dielectric layer, but due to the interaction between the carbon nanotubes in the carbon nanotube bundle, the carbon nanotubes inside the carbon nanotube bundle unit can still play an effective role. The carbon nanotube bundle field effect transistor array of the present invention can withstand higher operating voltage and operating current, and can be applied to high-power devices. Moreover, the present invention adopts the gate-all-around structure, which can improve the control ability of the gate to the channel. The manufacturing method of the carbon nanotube bundle field effect transistor array of the present invention has the characteristics of simple process steps, which is beneficial to reduce the production cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (16)

1. a carbon nanotube bundle field effect transistor array, is characterized in that, comprises: source material layer; a drain material layer formed above the source material layer; A carbon nanotube bundle array, connected between the source material layer and the drain material layer; the carbon nanotube bundle array includes a number of discretely arranged carbon nanotube bundle units, wherein the axial direction of the carbon nanotube bundle unit The first end is connected to the source material layer, and the axial second end of the carbon nanotube bundle unit is connected to the drain material layer; A gate structure is formed between each carbon nanotube bundle unit in the carbon nanotube bundle array, and the gate structure is isolated from the source material layer by a first insulating layer, and the gate structure is connected to the source material layer. The drain material layers are separated by a second insulating layer; wherein, the gate structure includes a gate dielectric layer and a gate material layer, and the gate dielectric layer surrounds the outer side surface of the carbon nanotube bundle unit, so the gate material layer surrounds the outer side surface of the gate dielectric layer; The carbon nanotube bundle unit is composed of a plurality of carbon nanotubes, wherein only the carbon nanotubes located on the periphery of the carbon nanotube bundle are partially or completely surrounded by the gate dielectric layer, and the carbon nanotubes located in the carbon nanotube bundle are not. surrounded by the gate dielectric layer. 2 . The carbon nanotube bundle field effect transistor array according to claim 1 , wherein the carbon nanotube bundle field effect transistor array further comprises a substrate and a third insulating layer formed on the substrate, the source electrode A material layer is formed on the third insulating layer. 3 . The carbon nanotube bundle field effect transistor array according to claim 1 , wherein the angle between the axial direction of the carbon nanotube bundle unit and the plane where the source material layer is located is 80°˜100°. 4 . 4 . The carbon nanotube bundle field effect transistor array according to claim 1 , wherein the height of the carbon nanotube bundle unit is greater than 100 μm. 5 . 5 . The carbon nanotube bundle field effect transistor array according to claim 1 , wherein the gate dielectric layer adopts a high-K dielectric, and the gate material layer comprises a metal material. 6 . 6 . The carbon nanotube bundle field effect transistor array of claim 1 , wherein the source material layer and the drain material layer both comprise metal materials. 7 . 7. a manufacturing method of carbon nanotube bundle field effect transistor array, is characterized in that, comprises the steps: S1: providing a substrate, and sequentially forming a third insulating layer, a source material layer and a first insulating layer on the substrate; S2: forming a through hole array in the first insulating layer; the through hole array includes a plurality of discrete through holes, and the through holes expose the upper surface of the source material layer; S3: forming a carbon nanotube bundle array based on the through hole array; the carbon nanotube bundle array includes a plurality of carbon nanotube bundle units corresponding to the positions of the through holes, wherein the axial first end of the carbon nanotube bundle unit connected with the source material layer; S4: forming a gate dielectric layer covering the outer side surface of the carbon nanotube bundle unit; S5: forming a gate material layer covering the outer side surface of the gate dielectric layer; S6: forming a second insulating layer and a drain material layer in sequence, wherein the axial second end of the carbon nanotube bundle unit is connected to the drain material layer, and the gate dielectric layer and the gate material layer are connected to the drain material layer. The drain material layers are isolated by a second insulating layer; The carbon nanotube bundle unit is composed of a plurality of carbon nanotubes, wherein only the carbon nanotubes located on the periphery of the carbon nanotube bundle are partially or completely surrounded by the gate dielectric layer, and the carbon nanotubes located in the carbon nanotube bundle are not. surrounded by the gate dielectric layer. 8 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 7 , wherein in the step S3 , under a protective atmosphere, the carbon nanotube bundle field effect transistor array is formed by chemical vapor deposition using a catalyst and a carbon source. 9 . Array of carbon nanotube bundles. 9 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 8 , wherein the protective atmosphere comprises one or more of N ₂ , H ₂ and Ar, and the catalyst comprises Fe. 10 . , one or more of Ni and Co, and the growth temperature range of the carbon nanotube bundle array is 500-740°C. 10 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 8 , wherein: firstly, the catalyst is formed on the upper surface of the source material layer based on the through hole array, and then the catalyst is formed based on the catalyst. 11 . The carbon nanotube bundle array is grown. 11 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 10 , wherein a solution containing catalyst ions is applied to the surface of the source material layer and annealed to increase the amount of catalyst ions and the The bonding strength of the source material layer. 12 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 11 , wherein the annealing temperature ranges from 700 to 900° C. and the annealing time ranges from 30 to 90 minutes. 13 . 13 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 11 , further comprising the step of removing excess catalyst ions on the surface of the second insulating layer. 14 . 14 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 13 , wherein the excess catalyst ions on the surface of the second insulating layer are removed by wet etching. 15 . 15 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 7 , wherein the angle between the axial direction of the carbon nanotube bundle unit and the plane where the source material layer is located is 80°˜80°. 16 . 100°. 16 . The method for manufacturing a carbon nanotube bundle field effect transistor array according to claim 7 , wherein the height of the carbon nanotube bundle unit is greater than 100 μm. 17 .

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