CN108230537B - Image data processing method, device, equipment and storage medium - Google Patents
Image data processing method, device, equipment and storage medium Download PDFInfo
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- G07D—HANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
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Abstract
The invention discloses a method, a device, equipment and a storage medium for processing image data, wherein the method comprises the following steps: collecting RGB image data, and respectively storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of an RAM (random access memory); writing the R, G and B component data stored in the RAM memory in parallel to a DDR SDRAM memory based on a DDR SDRAM base address; and reading the R, G and B component data written into the DDR SDRAM memory and performing corresponding image display. The embodiment of the invention solves the problems that the DDR bus is occupied by the time when the upper computer reads the image data, the DDR is operated for multiple times, and the process is complex, reduces the access frequency of the DDR bus, simplifies the process, and improves the processing capacity of the RGB image data.
Description
Technical Field
The embodiment of the invention relates to the technical field of financial machines and tools, in particular to a method, a device, equipment and a storage medium for processing image data.
Background
In the process of currency detection, an FPGA (Field-Programmable Gate Array) collects image data of the currency. In the prior art, an FPGA collects image Data of three colors of RGB of bills in a time-sharing manner, and respectively caches Data of R, G and B components in three different RAMs (Random-Access memories) in a chip, and meanwhile, an upper computer allocates base addresses of three DDRs to Data of R, G and B components in a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, also referred to as DDR for short) according to the image Data of each bill, and respectively stores the Data of R, G and B components in the DDR SDRAM Memory. The FPGA writes R, G and B component data into DDR SDRAM in sequence, namely, the R component data of the image is written based on the base address of the R component data; and after the R component data are completely written, writing the G component data based on the base address of the G component data, and finally writing the B component data based on the base address of the B component data. When the collected banknote image data is checked at the display terminal, the upper computer needs to operate the DDR SDRAM three times to complete the synthesis of one color map.
According to the existing RGB image data processing method, when a plurality of RGB images are continuously collected, the upper computer needs to operate the DDR SDRAM for many times, a DDR bus is occupied for a long time, data throughput is low, and the process is complex.
Disclosure of Invention
The invention provides a method, a device, equipment and a storage medium for processing image data, which reduce the access frequency to a data bus when an RGB image is acquired, simplify the flow and improve the processing efficiency of image pixel data.
In a first aspect, an embodiment of the present invention provides a method for processing image data, where the method includes:
collecting RGB image data, and respectively storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of an RAM (random access memory);
writing the R, G and B component data stored in the RAM memory in parallel to a DDR SDRAM memory based on a DDR SDRAM base address;
and reading the R, G and B component data written into the DDR SDRAM memory and performing corresponding image display.
In a second aspect, an embodiment of the present invention further provides an apparatus for processing image data, where the apparatus includes:
the component data caching module is used for acquiring RGB image data and storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of the RAM memory;
the DDR SDRAM storage module is used for writing the R, G and the B component data stored in the RAM memory into the DDR SDRAM memory in parallel based on a DDR SDRAM base address;
and the image synthesis module is used for reading the R, G and B component data written into the DDR SDRAM memory and performing corresponding image display.
In a third aspect, an embodiment of the present invention further provides an apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements a method for processing image data when executing the program.
In a fourth aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements a method of image data processing.
The invention provides a method, a device, equipment and a storage medium for processing image data, wherein R, G and B component data of the same pixel point of RGB image data are stored in three adjacent storage words of the same line of an RAM memory by acquiring the RGB image data; writing the R, G and B component data stored in the RAM memory in parallel to a DDR SDRAM memory based on a DDR SDRAM base address; the R, G and B component data written into the DDR SDRAM memory are read and corresponding image display is carried out, the access frequency to a DDR bus is reduced, the flow is simplified, and the data processing capacity is improved.
Drawings
FIG. 1a is a flowchart of a method for processing image data according to a first embodiment of the present invention;
FIG. 1b is a schematic diagram of a storage format of RGB image data in a RAM memory according to a first embodiment of the present invention;
FIG. 1c is a schematic diagram of a prior art storage format of RGB image data in a RAM memory according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for processing image data according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an apparatus for processing image data according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer device provided in the fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1a is a flowchart of a method for processing image data according to a first embodiment of the present invention, where the present embodiment is applicable to a case of acquiring RGB image data, and the method may be executed by an apparatus for processing image data, which is configured to be implemented in hardware and/or software, and specifically includes the following steps:
step S110, collecting RGB image data, and respectively storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of the RAM memory.
In the three primary color light mode, color lights of three primary colors of Red (Red), Green (Green), and Blue (Blue) are added at different ratios to generate various color lights, and in general, a color image may be an RGB image. A color image may be composed of a plurality of pixels, and a color pixel is composed of R, G and B component data. When the FPGA is used for collecting RGB image data, R, G data and B component data of the same pixel point of the GRB image data are stored in three adjacent storage words of the same row of the RAM, and the three storage words sequentially store R, G data and B component data of the same pixel point. All pixel points of the RGB image data are sequentially stored in the same RAM according to the sequence.
Illustratively, a GRB image has 1000 pixels, each of which has R, G and B component data. After the storage address of the RAM memory is determined, the three component data R1, G1 and B1 of the first pixel point are stored in three adjacent storage words of the same row of the RAM memory, and the three component data R2, G2 and B2 of the second pixel point are stored in three adjacent storage words of the next row of the same RAM memory.
And step S120, writing the R, G and B component data stored in the RAM memory into a DDR SDRAM memory in parallel based on the DDR SDRAM base address.
Because the RGB image data are stored in the same RAM in parallel and tightly, R, G and B components of the same pixel point of the RGB image data are stored in three adjacent storage words in the same line, different pixel points are arranged in the next line in sequence, and the same component data of different pixel points are stored in continuous storage words in the same column. Based on the storage format of the RGB image in the RAM memory, the upper computer allocates a base address in the DDR SDRAM, and based on the DDR SDRAM base address, the FPGA can write R, G of each pixel point of the RGB image data and B component data into the DDR SDRAM memory simultaneously in parallel.
And S130, reading the R, G and B component data written into the DDR SDRAM memory and performing corresponding image display.
And when the FPGA completely writes the RGB image data into the DDR SDRAM, the upper computer is informed to perform the next operation. Because only one base address is allocated when R, G and B component data are stored in DDR SDRAM, when the upper computer reads R, G and B component data, the upper computer only needs to read the image data in the DDR SDRAM memory at one time according to the base address, and the image data is stored locally for corresponding image display.
The working principle of the image data processing method is as follows: because the speed of collecting the image data by the FPGA is faster than the speed of processing the image data, a memory is required to be hung externally to be used as a cache to temporarily store the image data. The FPGA collects RGB image data, R, G and B component data of each pixel point of the RGB image are stored in the same RAM memory, R, G and B component data of the same pixel point are stored in three adjacent memory words on the same row, and data of the same component of all the pixel points are stored in continuous memory words on the same column of the RAM memory.
Referring to fig. 1b, fig. 1b is a schematic diagram illustrating a storage format of RGB image data in a RAM memory according to a first embodiment of the present invention. As shown in fig. 1b, the RAM memory includes at least 3 columns and n rows of memory space. Assume that a GRB image has 1000 pixels, each pixel is composed of R, G and B component data. When the FPGA collects the RGB image data, firstly caching R1 component data of a first pixel point on a memory word of a first column of a first line of the RAM, caching G1 component data on a memory word of a second column of the first line of the RAM, and caching B1 component data on a memory word of a third column of the first line of the RAM; similarly, when the data of the second pixel point is collected, the R2 component data of the second pixel point is cached in the memory word of the first column of the second line of the RAM, the G2 component data is cached in the memory word of the second column of the second line of the RAM, and the B2 component data is cached in the memory word of the third column of the second line of the RAM; and by analogy, caching the component data of the other pixel points of the RGB image data. The process of buffering the RGB image data in the RAM memory is a process of storing and fetching simultaneously, and all pixel points of the RGB image are not required to be cached in the RAM memory and are written into the DDR SDRAM memory.
Based on the R, G and the storage method and the storage format of the B component data in the RAM memory, the upper computer only needs to allocate a base address in the DDR SDRAM memory, the FPGA writes R, G and the B component data cached in the RAM memory into the DDR SDRAM memory in parallel and simultaneously based on the base address, and concretely, when a first pixel point is written into the DDR SDRAM memory, R, G of the pixel point and the B component data are written into the DDR SDRAM memory in parallel and simultaneously; similarly, the component data of other pixel points can be written into the DDR SDRAM memory simultaneously in parallel. And when the FPGA completely writes the RGB image data into the DDR SDRAM memory, the upper computer is informed. Based on the writing mode of the component data of the RGB image, the upper computer only needs to operate the DDR once, namely, the DDR bus is accessed once, and then the acquisition of each component data of the RGB image can be completed. The upper computer reads the RGB image data at one time according to the base address and stores the RGB image data locally, and then display of the corresponding RGB image is achieved at the terminal.
Fig. 1c is a schematic diagram of a storage format of RGB image data in a RAM memory according to the first embodiment of the present invention. As shown in fig. 1c, the three component data of RGB image data are cached in three different RAM memories within the chip, RAM1, RAM2, and RAM3, respectively. The first RAM memory RAM1 buffers R-score data, the second RAM memory RAM2 buffers G-component data, and the third RAM memory RAM3 buffers B-component data. Based on the storage format, the upper computer can allocate three base addresses in the DDR SDRAM to write the RGB image component data from the three memories of RAM1, RAM2 and RAM3 into the DDR SDRAM memory, and read the R, G and B component data component by component data from the memories of RAM1, RAM2 and RAM3 in a prescribed order, such as reading the R component data in the memory of RAM1, reading the G component data in the memory of RAM2, and reading the B component data in the memory of RAM 3. When R, G and the B component data are all written into the DDR SDRAM memory, the upper computer also needs to perform the DDR operation 3 to complete the synthesis of an RGB image.
Comparing the storage formats of the RGB image data in the RAM memories shown in fig. 1B and fig. 1c, it can be seen that, in the technical scheme provided in this embodiment, the R, G and B component data are cached in only one RAM memory, only one base address needs to be allocated when the component data is written into the DDR SDRAM memory, and the upper computer only needs to operate the DDR SDRAM once to complete the synthesis of the RGB image. The technical scheme of the embodiment includes that RGB image data are collected, R, G component data and B component data of the same pixel point of the RGB image data are stored in three adjacent storage words of the same line of an RAM memory; writing the R, G and B component data stored in the RAM memory to DDR SDRAM memory in parallel based on DDRSDRAM base address; the R, G and B component data written into the DDR SDRAM memory are read and corresponding image display is carried out, the frequency of DDR operation by an upper computer when RGB image data are collected and processed by the FPGA is reduced, the problem that a DDR bus is occupied by time for processing the image data in the prior art is solved, the image data processing flow is simplified, and the image data processing capacity is improved.
Example two
Fig. 2 is a flowchart of a method for processing image data according to a second embodiment of the present invention, and as shown in fig. 2, the method specifically includes:
step S210, collecting RGB image data, and respectively storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of the RAM memory.
When the image data is collected by the FPGA, the data volume is large, and the speed of processing the image data by the FPGA cannot catch up with the speed of image collection, so that the SDRAM is required to be hung externally to be used as a cache to temporarily store the data. In this embodiment, before caching the image data in the external SDRAM, the image data is cached in the on-chip RAM, and the cache format is converted. The process of caching the RGB image data into the on-chip RAM is a process of storing and fetching simultaneously. The RAM memory is an on-chip memory and is used for enabling R, G and B component data of each pixel point of GRB image data to be stored in three adjacent storage words in the same line of the same RAM memory, and writing and reading of subsequent RGB image data are facilitated.
In GRB image data, R, G and B component data are stored in memory in the form of memory words, one memory word containing 8 bits of binary bits, i.e., memory bits. The color components of the pixel points are generally represented by decimal codes or hexadecimal codes, and in the red, green and blue components, the smaller the value of each component is, the lower the brightness is, and the larger the value is, the higher the brightness is. The numerical range of the RGB component data, expressed in decimal code, is: 0 to 255; expressed in hexadecimal code, then: 00-FF; expressed in binary code, then: 00000000 to 11111111. Exemplarily, (255 ) indicates that the color of the pixel point is black, and at this time, the red component is 255, the green component is 255, and the blue component is 255; (255,255, 0) indicates that the color of the pixel point is yellow, at this time, the red component is 255, the green component is 255, and the blue component is 0. If the red, green and blue component data are converted into binary values to represent, then (11111111, 11111111, 11111111111) represents black, and (11111111111, 11111111, 00000000) represents yellow, so that it can be known that the color of a pixel can be represented by a 24-bit binary number. Regarding R, G and B component data of the same pixel point as a whole, R, G and B component data are stored in three adjacent storage words of the same row, or R, G and B component data are stored in 24 adjacent storage bits of the same row.
When R, G and B component data of the next pixel are cached, R, G and B component data of the next pixel are respectively and correspondingly stored in corresponding R, G and continuous storage words of B component data of the previous pixel, that is, R, G and B component data are respectively and correspondingly stored in continuous storage words of the same column.
Step S220, calculating the storage space occupied by the RGB image data storage, and determining the base address when the RGB image data is written into the DDR SDRAM according to the storage space of the RGB image data.
According to the RGB image data cached in the RAM memory, the storage space occupied by the RGB image data is calculated, and a proper base address is selected in the DDR SDRAM so that the DDR SDRAM memory can have enough storage space to store the RGB image data. An appropriate DDR SDRAM base address is selected for the RGB image data to store the entire RGB image, depending on the storage format of R, G and B component data cached in RAM memory.
And step S230, writing the R, G and B component data stored in the RAM memory into a DDR SDRAM memory in parallel based on the DDR SDRAM base address.
The upper computer is R, G, and the B component data is allocated with a base address in the DDR SDRAM memory. According to R, G and the storage format of the B component data in the RAM memory, the FPGA writes R, G and the B component data into a DDR SDRAM memory simultaneously in parallel, the DDR SDRAM memory is a plug-in memory and is used for storing R, G and B component data in an RGB image, and the storage space of the DDRSDRAM memory is large enough to store the RGB image data. In DDR SDRAM memories, R, G of RGB image data and B component data are stored in adjacent three memory words or adjacent 24 memory bits of the same row.
And step S240, reading the R, G and B component data written into the DDR SDRAM and performing corresponding image display.
In the DDR SDRAM memory, R, G and B component data of the same pixel point of GRB image data are stored in three adjacent memory words in the same row, and the same component of different pixel points are stored in consecutive memory words in the same column. And when the FPGA finishes writing the RGB image data, the upper computer is informed to carry out the next operation. The upper computer can finish the reading of R, G and B component data stored in the DDR SDRAM memory only by operating the DDR SDRAM memory once, and the RGB images are synthesized and displayed at the terminal.
When the embodiment collects and processes the RGB image data, firstly, the R, G and B component data of each pixel are converted and cached in the on-chip memory RAM, the upper computer can simultaneously write R, G and B component data into the DDRSDRAM memory in parallel only by allocating a base address in the DDR SDRAM memory, and after R, G and B component data are written into the DDRSDRAM memory, the upper computer only needs to read the data once to display the RGB image on the terminal, so that the problems that the DDR bus is occupied by the time when the upper computer reads the image data, the DDR bus is operated for multiple times, and the flow is complex are solved.
EXAMPLE III
Fig. 3 is a schematic structural diagram of an apparatus for processing image data according to a third embodiment of the present invention, where the apparatus may be implemented by software and/or hardware. The method can be generally integrated on a hardware system such as an FPGA (field programmable gate array), and can improve the processing capacity of image data by executing the image data processing method. As shown in fig. 3, the apparatus specifically includes: a component data caching module 310, a ddr sdram storage module 320, and an image composition module 330.
The component data caching module 310 is configured to collect RGB image data, and store R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of the RAM memory; a DDR SDRAM storage module 320 for writing the R, G and B component data stored in the RAM memory in parallel to a DDR SDRAM memory based on a DDR SDRAM base address; and the image synthesis module 330 is configured to read the R, G and B component data written in the DDR SDRAM memory and perform corresponding image display.
The technical scheme of the embodiment provides an image data processing device, after image data are collected by using an FPGA, firstly, the image data are cached in an on-chip memory RAM for R, G and B component data storage format conversion, R, G and B component data of the same pixel are stored in three adjacent storage words in the same row, R, G and B component data of different pixels are respectively stored in three continuous storage words in the same column, one-time parallel writing in a DDR SDRAM memory is realized, an upper computer can read RGB image data only by operating the DDR once, the RGB image is displayed at a terminal, the access frequency of the upper computer to the DDR is reduced, the process is simplified, and the processing capacity of the image data is improved.
On the basis of the above embodiment, the component data caching module 310 is further configured to allocate the same component data of the R, G and B component data in consecutive memory words of the same column of the RAM, that is, the same component data of different pixels are stored in consecutive memory words of the same column, so as to facilitate processing of a subsequent image. Because one component data can be represented as an 8-bit binary code, that is, one component data occupies 8-bit storage bits, that is, one pixel point can use a 24-bit secondary code, that is, the component data of one pixel point is stored in 24-bit storage bits adjacent to each other in the same row in the same RAM. The RAM memory is an on-chip memory, RGB image data are cached in the RAM memory in a process of storing and fetching at the same time, and the effect of the RAM memory is to change the component data of pixel points of the RGB image in a cache format so that the RGB image data can be written into DDR SDRAM in parallel.
On the basis of the above-described embodiment, the apparatus for image data processing includes: and the storage space calculation module is used for calculating the storage space required by the storage of the RGB image data and determining the base address when the RGB image data is written into the DDR SDRAM according to the storage space of the RGB image data.
The upper computer is R, G, the B component data are distributed with base addresses in the DDR SDRAM, the FPGA writes the RGB image data into the DDR in parallel based on the base addresses, after the RGB image data are written, the upper computer reads the RGB image data at one time based on the base addresses and the storage format of the RGB image data and stores the RGB image data locally, and the RGB image is displayed on the terminal.
The product can execute the method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
Example four
Fig. 4 is a schematic structural diagram of a computer device according to a fourth embodiment of the present invention. Fig. 4 illustrates a block diagram of an exemplary device 12 suitable for use in implementing embodiments of the present invention. The device 12 shown in fig. 4 is only an example and should not bring any limitation to the function and scope of use of the embodiments of the present invention.
As shown in FIG. 4, device 12 is in the form of a general purpose computing device. The components of device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including the system memory 28 and the processing unit 16.
The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)30 and/or cache memory 32. Device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 4, and commonly referred to as a "hard drive"). Although not shown in FIG. 4, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.
The processing unit 16 executes various functional applications and data processing by executing programs stored in the system memory 28, for example, implementing a method of image data processing provided by an embodiment of the present invention:
that is, the processing unit implements, when executing the program: collecting RGB image data, and storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of an RAM memory; writing the R, G and B component data stored in the RAM memory in parallel to a DDR SDRAM memory based on a DDR SDRAM base address; and reading the R, G and B component data written into the DDR SDRAM memory and performing corresponding image display.
EXAMPLE five
An embodiment five of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements a method for processing image data, as provided in all inventive embodiments of the present application:
that is, the program when executed by the processor implements: collecting RGB image data, and storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of an RAM memory; writing the R, G and B component data stored in the RAM memory to DDR SDRAM memory in parallel based on DDRSDRAM base address; and reading the R, G and B component data written into the DDR SDRAM memory and performing corresponding image display.
Embodiment five of the present invention provides a computer-readable storage medium that may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. A method of image data processing, comprising:
collecting RGB image data, and respectively storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of an RAM (random access memory);
writing the R, G and B component data stored in the RAM memory in parallel to DDR SDRAM memory based on a DDR SDRAM base address;
reading the R, G and B component data written into the DDR SDRAM memory based on the DDR SDRAM base address and performing corresponding image display;
before writing the R, G and B component data stored in the RAM memory in parallel into DDRSDRAM memory based on DDR SDRAM base address, further comprising:
calculating the storage space occupied by the RGB image data storage, and determining the base address of the RGB image data when the RGB image data is written into DDR SDRAM according to the storage space of the RGB image data.
2. The method of claim 1, further comprising:
and allocating the R, G and the same component data of the B component data in the corresponding same column of memory words of the RAM memory.
3. The method according to claim 2, wherein said allocating R, G and the same component data of the B component data in the same column of memory words in the RAM memory comprises:
the R, G and the same one of the B component data are allocated in consecutive memory words of the corresponding same column of the RAM memory.
4. The method according to any one of claims 1-3, wherein the RAM is an on-chip memory for circularly buffering the RGB image data;
the DDR SDRAM is an external memory and is used for storing data of R, G and B components in an RGB image.
5. An apparatus for image data processing, comprising:
the component data caching module is used for acquiring RGB image data and respectively storing R, G and B component data of the same pixel point of the RGB image data in three adjacent storage words in the same line of the RAM;
the DDR SDRAM storage module is used for writing the R, G component data and the B component data stored in the RAM memory into the DDR SDRAM memory in parallel based on a DDR SDRAM base address;
the image synthesis module is used for reading the R, G and B component data written into the DDR SDRAM memory based on the DDR SDRAM base address and performing corresponding image display;
further comprising:
and the storage space calculation module is used for calculating the storage space required by the storage of the RGB image data and determining the base address when the RGB image data is written into the DDR SDRAM according to the storage space of the RGB image data.
6. The apparatus of claim 5,
the R, G and the same one of the B component data are allocated in consecutive memory words of the corresponding same column of the RAM memory.
7. An apparatus comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1-4 when executing the program.
8. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-4.
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