CN108228492B - Multi-channel DDR interleaving control method and device - Google Patents

Abstract

The invention discloses a multi-channel DDR interleaving control method and device, wherein the method includes: receiving write data and a first write address sent by a host; and determining the first write address according to preset interleaving control configuration information The corresponding second write address and the identification information of the slave corresponding to the first write address; according to the identification information of the slave, send the write data and the second write address to the slave; receive The write feedback message sent by the slave, wherein the write feedback message is used to indicate whether the write data is successfully written; the write feedback message is sent to the host.

Description

A kind of multi-channel DDR interleaving control method and device

technical field

The present invention relates to the field of storage technology, and in particular, to a multi-channel DDR interleaving control method and device.

Background technique

Today's chips generally integrate components such as a central processing unit (Central Processor Unit, CPU), direct memory access (Direct Memory Access, DMA), bus interconnection, memory, high-speed peripherals and low-speed peripherals. With the continuous improvement of integrated circuit technology, the operating frequency and performance requirements of the chip are also getting higher and higher, and the bandwidth required by the chip is also increasing. Therefore, the conventional Double Data Rate Synchronous Dynamic Random Access Memory , DDR SDRAM) subsystem has been unable to meet the high bandwidth requirements of the system, more and more systems on chip (System On Chip, SoC) use dual (multi) channel DDR as a dynamic storage solution, compared with traditional single channel DDR It has the characteristics of high theoretical bandwidth and high transmission efficiency.

At present, the Network On Chip (NOC) product, which is widely used in data streams of multi-channel DDR storage systems, performs transmission interleaving control. This product has the characteristics of rich and configurable parameters, strong command scheduling ability, etc., but it also has high licensing costs, The disadvantage is that the command delay is large, the area is large, and the interleaving mode is fixed.

SUMMARY OF THE INVENTION

In order to solve the existing technical problems, the embodiments of the present invention provide a multi-channel DDR interleaving control method and device, which solve the problems of large delay, area, and fixed interleaving mode of the multi-channel DDR memory interleaving control device in the prior art, so as to achieve The technical effects of small delay, small area, flexible and configurable interleaving mode, and low power consumption are achieved.

In order to achieve the above-mentioned purpose, the technical scheme of the embodiment of the present invention is realized as follows:

In a first aspect, an embodiment of the present invention provides a multi-channel DDR interleaving control method, the method includes:

Receive the write data and the first write address sent by the host; wherein, the host is a bus interconnection module;

Determine the second write address corresponding to the first write address and the identification information of the slave corresponding to the first write address according to the preset interleaving control configuration information;

According to the identification information of the slave, the write data and the second write address are sent to the slave; wherein the slave is a DDR controller;

receiving a write feedback message sent by the slave, wherein the write feedback message is used to represent whether the write data is successfully written;

The write feedback message is sent to the host.

In a second aspect, an embodiment of the present invention provides a multi-channel DDR interleaving control method, the method includes:

Receive the first read address sent by the host;

Determine the second read address corresponding to the first read address and the identification information of the first slave corresponding to the first read address according to the preset interleaving control configuration information;

sending the second read address to the first slave according to the identification information of the first slave;

receiving the first read data and the first read response message sent by the first slave;

Send the first read data and the first read response message to the host.

In a third aspect, an embodiment of the present invention provides a multi-channel DDR interleaving control device, the device comprising:

a first receiving module, configured to receive the write data and the first write address sent by the host; wherein, the host is a bus interconnection module;

a first determining module, configured to determine, according to preset interleaving control configuration information, the second write address corresponding to the first write address and the identification information of the slave corresponding to the first write address;

a first sending module, configured to send the write data and the second write address to the slave according to the identification information of the slave; wherein the slave is a DDR controller;

a second receiving module, configured to receive a write feedback message sent by the slave, wherein the write feedback message is used to represent whether the write data is successfully written;

A second sending module, configured to send the write feedback message to the host.

In a fourth aspect, an embodiment of the present invention provides a multi-channel DDR interleaving control device, the device comprising:

The third receiving module is used to receive the first read address sent by the host;

a second determining module, configured to determine, according to preset interleaving control configuration information, the second read address corresponding to the first read address and the identification information of the first slave corresponding to the first read address;

a third sending module, configured to send the second read address to the first slave according to the identification information of the first slave;

a fourth receiving module, configured to receive the first read data and the first read response message sent by the first slave;

The fourth sending module is configured to send the first read data and the first read response message to the host.

In the multi-channel DDR interleaving control method and device provided by the embodiments of the present invention, by receiving the write data and the first write address sent by the host, and then according to preset interleaving control configuration information, the second write address corresponding to the first write address is determined. The write address and the identification information of the slave corresponding to the first write address, and then send the write data and the second write address to the slave according to the identification information of the slave, and receive the The write feedback message sent by the slave is finally sent to the host. Since interleaving control configuration information such as interleaving size and interleaving mode can be set in advance, the flexibility of interleaving control is increased.

Description of drawings

In the drawings, which are not necessarily to scale, like reference numerals may describe like parts in the different views. Similar reference numbers with different letter suffixes may denote different instances of similar components. The accompanying drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

1 is a schematic flowchart of an implementation of a multi-channel DDR interleaving control method according to an embodiment of the present invention;

FIG. 2 is a schematic flowchart of the implementation of a multi-channel DDR interleaving control method according to Embodiment 2 of the present invention;

3-1 is a schematic diagram of the composition and structure of a multi-channel DDR interleaving control device according to Embodiment 3 of the present invention;

FIG. 3-2 is a schematic flowchart of the implementation of the third multi-channel DDR interleaving control method according to Embodiment 3 of the present invention

FIG. 4 is a schematic diagram of the composition and structure of a four-channel DDR interleaving control device according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the composition and structure of a multi-channel DDR interleaving control apparatus according to Embodiment 5 of the present invention.

Detailed ways

The technical solutions of the present invention will be further elaborated below with reference to the accompanying drawings and specific embodiments.

Example 1

In order to solve the technical problems existing in the background art, an embodiment of the present invention provides a multi-channel DDR interleaving control method, which is applied to a multi-channel DDR. The multi-channel DDR at least includes: a processor, an interleaving controller, a host, and at least one slave. FIG. 1 is a schematic flowchart of an implementation of a multi-channel DDR interleaving control method according to an embodiment of the present invention. As shown in FIG. 1 , the method includes the following steps:

Step S101, receiving the write data and the first write address sent by the host;

Here, step S101 may be implemented by an interleaving control apparatus, and in practical applications, the interleaving control apparatus may be an interleaving controller. The host may be a bus interconnection module, that is, a bus Matrix, and currently a network adapter (Network Interface Card, NIC) 400 is commonly used.

Step S102, according to preset interleaving control configuration information, determine the second write address corresponding to the first write address and the identification information of the slave corresponding to the first write address;

Here, the processor configures some interleaving control configuration information of the interleaving controller in advance according to the actual usage of the system, such as interleaving size, non-interleaving address range, interleaving mode, and the like. The interleaving controller may determine, according to preset interleaving control configuration information, the second write address corresponding to the first write address and the identification information of the slave corresponding to the first write address. The second write address is a write address obtained by remapping the first write address according to the interleaving control configuration information, and is also a physical address of the DDR to which the write data is to be written.

Step S103, sending the write data and the second write address to the slave according to the identification information of the slave;

Here, the slave may be a DDR controller; after receiving the write data and the second write address, the slave writes the write data into the DDR memory unit according to the second write address , and send write feedback information to the interleaving controller.

Step S104, receiving the write feedback message sent by the slave;

Here, the write feedback message is used to represent whether the write data is successfully written.

Step S105, sending the write feedback message to the host.

Here, after receiving the write feedback message sent by the slave, the interleaving controller sends the write feedback message to the host.

In other embodiments of the present invention, the step S105 includes: judging whether the write feedback receiving logic module is idle;

If the write feedback receiving logic module is idle, send the write feedback message to the host.

If the write feedback logic module is not idle, after waiting for a preset time, determine whether the write feedback receiving logic module is idle;

If the write feedback receiving logic module is idle, send the write feedback message to the host.

After the step S105, the method further includes: by determining the bandwidth information of the write data channel; determining the response delay information of the write command; here, the response delay of the write command is the time from receiving the write data sent by the host. The time difference between the first write address and the sending of the write feedback message to the host; the bandwidth information of the write data channel and the response delay information of the write command are stored to detect the bandwidth information of the write data channel, and record The response delay of the write command and if there is no data or message transmission within the preset low-power timing threshold time, turn off its own control clock to reduce power consumption.

In the multi-channel DDR interleaving control method provided by the implementation of the present invention, the second write address corresponding to the first write address is determined by receiving the write data and the first write address sent by the host, and then according to preset interleaving control configuration information The identification information of the slave corresponding to the first write address, and then according to the identification information of the slave, the write data and the second write address are sent to the slave, and the slave is received. Send the write feedback message, and finally send the write feedback message to the host. Since interleaving control configuration information such as interleaving size and interleaving mode can be set in advance, the flexibility of interleaving control is increased. In addition, if there is no data or message transmission within the preset low-power timing threshold time, the control clock itself is turned off, which can reduce power consumption.

Embodiment 2

Based on the foregoing embodiments, an embodiment of the present invention further provides a multi-channel DDR interleaving control method, which is applied to an interleaving controller of a multi-channel DDR, where the multi-channel DDR at least includes: an interleaving controller, a host, and at least one slave . FIG. 2 is a schematic flowchart of an implementation of a multi-channel DDR interleaving control method according to Embodiment 2 of the present invention. As shown in FIG. 2 , the method includes the following steps:

Step S201, the interleaving controller receives the first read address sent by the host;

Step S202, the interleaving controller determines, according to preset interleaving control configuration information, the second read address corresponding to the first read address and the identification information of the first slave corresponding to the first read address;

Here, the processor configures some interleaving control configuration information of the interleaving controller in advance according to the actual usage of the system, such as interleaving size, non-interleaving address range, interleaving mode, and the like. The interleaving controller may determine, according to preset interleaving control configuration information, the second read address corresponding to the first read address and the identification information of the slave corresponding to the first read address. The second read address is the read address remapped by the first read address according to the interleaving control configuration information, that is, the physical address in the DDR where the data to be read is located.

Step S203, the interleaving controller sends the second read address to the first slave according to the identification information of the first slave;

Here, after receiving the second read address, the first slave reads out the first read data from the storage unit of the DDR according to the second read address, and combines the first read data with the first read data. A read response message is sent to the interleaving controller.

Step S204, the interleaving controller receives the first read data and the first read response message sent by the first slave;

Step S205, the interleaving controller judges whether it has received the second read data and the second read response message sent by the second slave; if yes, go to step S206, otherwise go to step S208;

Here, because the multi-channel DDR has at least one slave, when there are multiple slaves, when other slaves also send read data and read response messages to the interleaving controller at the same time (for example, the second If the slave wants to send the second read data and the second read response message to the interleaving controller), it needs to determine whether to send the first read data and the first read response message to the interleaving controller first, or whether to send the second read data and the first read response message to the interleaving controller first. Read data and a second read response message are sent to the interleaving controller.

Step S206, the interleaving controller judges whether the waiting time of the first slave is less than or equal to a preset response timeout threshold; if yes, then go to step S207, otherwise go to step S211;

Step S207, the interleaving controller determines whether the read priority of the first slave is higher than the read priority of the second slave; if yes, go to step S208, otherwise go to step S209;

Step S208, the interleaving controller sends the first read data and the first read response message to the host.

Step S209, the interleaving controller determines whether the read priority of the first slave is the same as the read priority of the second slave; if so, go to step S210, otherwise go to step S211;

Step S210, the interleaving controller judges whether the port number of the first slave is smaller than the port number of the second slave; if yes, then go to step S208, otherwise go to step S211;

Step S211, the interleaving controller sends the second read data and the second read response message to the host; and then goes to step S205.

In the embodiment of the present invention, the method further includes: determining the bandwidth information of the read data channel; determining the response delay information of the read command; here, the response delay of the read command is the first time from receiving the first data sent by the host. The time difference between reading the address and sending the first read data to the host and the first read response message, that is, from receiving the first read address sent by the host to sending the last read data to the host. time difference. The bandwidth information of the read data channel and the response delay information of the read command are stored to detect the bandwidth information of the read data channel, and the response delay of the read command is recorded.

In the present invention and other embodiments, the method further includes:

If the read data and read response message or write feedback information sent by any slave are not received, and the read address or write address or write data sent by the master is not received, the low-power timer is started to start timing;

If the low-power timer reaches the low-power timer threshold, the read data and read response message and/or write feedback message sent by any slave have not been received and the read address sent by the master has not been received. Or write address or write data, then turn off its own control clock.

In this way, if there is no read request or write request and there is no ongoing read and write operation within the preset low power consumption timing threshold time, the control clock of itself is turned off to reduce power consumption.

In the multi-channel DDR interleaving control method provided by the embodiment of the present invention, by receiving the first read address sent by the host, and then according to preset interleaving control configuration information, the second read address corresponding to the first read address and all The identification information of the first slave corresponding to the first read address, and then according to the identification information of the first slave, the second read address is sent to the first slave, and received from the first slave. the first read data and the first read response message, and send the first read data and the first read response message to the host. Since interleaving control configuration information such as interleaving size and interleaving mode can be set in advance, the flexibility of interleaving control is increased. In addition, if there is no data or message transmission within the preset low-power timing threshold time, the control clock itself is turned off, which can reduce power consumption.

Embodiment 3

Embodiments of the present invention first provide an interleaving control device for multi-channel DDR, and based on the interleaving control device, embodiments of the present invention further provide an interleaving control method for multi-channel DDR.

Figure 3-1 is a schematic structural diagram of a multi-channel DDR interleaving control device according to Embodiment 3 of the present invention. As shown in Figure 3-1, the device includes: read data, read response control 301, read address mapping control 302, and write address Mapping, writing data, writing feedback control 303, bus monitoring 304 and register configuration 305, where:

The read data and read response control 301 is used to return the read data and read responses returned by each slave to the host after making a judgment.

The read address mapping control 302 is used to map the read address sent from the master to the corresponding slave according to the interleaving configuration.

The write address mapping, write data, and write feedback control 303 is used to map the write address sent by the master to the corresponding slave according to the interleaving configuration, and send the write data to the slave of the corresponding address, and the slave receives the write feedback to the host.

The bus monitoring 304 detects the bandwidth information of the read data path, the write data path, the information (outstanding information) that multiple read and write commands are executed simultaneously, and records the respective average response delays of the read and write commands, and these information can be stored in register configurations. 105 for the processor to acquire.

The register configuration 305: Complete various configurations of interleaving control, including interleaving size, interleaving mode, non-interleaving area, read data channel timeout threshold, ignore interleaving control, low power consumption timing threshold, etc., and register bus monitoring information.

According to the above description of the composition of the multi-channel DDR control device, it can be seen that the multi-channel DDR control device provided by the embodiment of the present invention mainly has the following functions:

(1) Interleaving controller configuration: Complete various configurations of interleaving control, including interleaving size, interleaving mode, non-interleaving area, read data channel timeout threshold, ignoring interleaving control, and low-power timing threshold.

(2) Write channel control: complete write channel address mapping, write priority register, improved microcontroller bus architecture (Advanced Microcontroller Bus Architecture, AMBA), improved Advanced eXtensible Interface (Advanced eXtensible Interface, AXI) write identification (Identification, ID) register, send write data, receive write feedback.

(3) Read channel control: complete read channel address mapping, read priority register, AMBA, AXI protocol read ID register, read data, read response return control.

(4) Read data and read response return control: Return read data to the host according to the read priority from high to low. If the priority is the same, the read data is returned from low to high according to the sequence of the slave port serial number. If a slave occupies the read data If the data channel time exceeds the read data channel timeout threshold, it will respond to the read data of other slaves except the slave.

(5) Low power consumption control: If there is no read request or write request for a period of time and there is no ongoing read and write operation, the clock of the interleaving controller is automatically turned off.

(6) Bus monitoring: monitor the bandwidth information and transmission delay information of the bus.

Based on the multi-channel DDR interleaving control device, an embodiment of the present invention further provides a multi-channel DDR interleaving control method. FIG. 3-2 is a schematic diagram of the implementation flow of the multi-channel DDR interleaving control method according to the third embodiment of the present invention, as shown in FIG. 3- 2, the method includes the following steps:

Step S301, the processor configures the registers of the interleaving controller, such as the registers of the interleaving size, the registers of the interleaving mode, the registers of the non-interleaving address range, etc.;

Step S302, the host sends a write address and write data to the interleaving controller;

Step S303, the interleaving controller maps the write address to the corresponding slave according to the set interleaving size, interleaving mode, non-interleaving address range, etc., and sends write data to the slave;

Step S304, the interleaving controller receives the write feedback returned by the slave;

Step S305, the interleaving controller judges whether the write feedback receiving logic is busy;

Step S306, if the write feedback receiving logic is idle, the interleaving controller returns the write feedback to the host;

Step S307, if the write feedback receiving logic is busy, wait for idle time before returning to step S305;

Step S308, the host sends a read address to the interleaving controller;

Step S309, the interleaving controller maps the read address to the corresponding slave according to the set interleaving size, interleaving mode, non-interleaving address range, etc.;

Step S310, the interleaving controller receives the read data and the read response returned by the slave;

Step S311, the interleaving controller judges whether there are other slaves returning read data and read responses at the same time;

Step S312, if there are other slaves returning read data and read responses at the same time, the interleaving controller determines whether the waiting time of the slave is less than or equal to the response timeout threshold; if so, go to step S313, otherwise go to step S316;

Step S313, the interleaving controller judges whether the read priority of the slave is higher than that of other slaves; if yes, then go to step S314, otherwise go to step S315;

Step S314, the interleaving controller returns read data and read response to the host;

Step S315, the interleaving controller judges whether the slave has the same priority as other slaves and the slave port number is smaller than that of the other slaves; if so, go to step S314, otherwise go to step S316;

Step S316, the interleaving controller waits for other slaves to return read data and read responses to the host, and then returns to step S311.

Here, the interleaving controller may repeat steps S302-S307 to perform a write operation, and repeat steps S308-S316 to perform a read operation.

In the multi-channel DDR interleaving control method provided by the embodiment of the present invention, the processor configures the interleaving size, non-interleaving address range, interleaving mode, etc. of the interleaving controller in advance; the interleaving size may be 64 bytes (Byte, B), 128 B, 256B, 512B, 1 kilobyte (Kilo Byte, KB), 2KB, 4KB; the non-interleaving address range is a continuous address (KB alignment), it can be agreed that the address will only be mapped to a fixed slave, without interleaving memory access ; The interleaving mode is agreed to be different interleaving address mapping forms within the interleaving address range, and the bandwidth utilization rate of the interleaving mode in different application scenarios is different.

The write address data stream is sent to the corresponding slave DDR write channel according to the interleaving setting, and the write data is sent to the slave according to the mapping of the write address, and the slave side sends the write feedback to the host;

The read address data stream is sent to the corresponding slave DDR read channel according to the interleaving setting. The slave side receives the read data and feeds it back to the host in a certain order. The slave side sends the read response and read data to the host.

Among them, the write channel includes: 1, write address channel: the host sends the write address to the interleaving controller, the interleaving controller completes the address mapping and sends the mapped write address to the corresponding slave according to the interleaving configuration; 2, the write data channel: according to the After mapping the write address, send the write data to the corresponding slave; 3. Write feedback channel: the slave returns the write feedback to the host according to the write address.

The read channel includes: 1. Read address channel: the host sends the read address to the interleaving controller, and the interleaving controller completes the address mapping according to the interleaving configuration and sends the mapped read address to the corresponding slave; 2. Read data and read response channels: The slave receives the read data, and returns the read data and read response in turn according to the priority of the read data of each slave, the read data timeout timer of the slave, and the polling response control of each slave.

In this embodiment of the present invention, parameters such as the interleaving size, interleaving mode, and non-interleaving address range of the interleaving controller can be configured in advance, which increases flexibility. After completing the interleaving configuration, the host can complete the read and write interleaving access to the slave multi-channel DDR through the interleaving controller. The read and write information reaches the slave according to the rules and returns relevant information to the host. The interleaving control method and control device provided by the embodiments of the present invention have the characteristics of small delay, small area, flexible and configurable interleaving mode, and low power consumption.

Embodiment 4

An embodiment of the present invention provides a multi-channel DDR interleaving control device. FIG. 4 is a schematic diagram of the composition and structure of a multi-channel DDR interleaving control device according to an embodiment of the present invention. As shown in FIG. 4 , the control device includes: a first receiving module 401 , a first determining module 402, a first sending module 403, a second receiving module 404 and a second sending module 405, wherein:

The first receiving module 401 is used to receive the write data and the first write address sent by the host; wherein, the host is a bus interconnection module;

The first determining module 402 is configured to determine, according to preset interleaving control configuration information, the second write address corresponding to the first write address and the identification information of the slave corresponding to the first write address;

Here, the first determining module 402 further includes: a first determining unit, configured to determine the second write address corresponding to the first write address according to the preset interleaving size, non-interleaving address range, and interleaving mode of the interleaving controller The identification information of the slave corresponding to the first write address.

The first sending module 403 is configured to send the write data and the second write address to the slave according to the identification information of the slave; wherein the slave is a DDR controller;

The second receiving module 404 is configured to receive a write feedback message sent by the slave, wherein the write feedback message is used to represent whether the write data is successfully written;

The second sending module 405 is configured to send the write feedback message to the host.

Here, the second sending module 405 further includes: a first judging unit for judging whether the write feedback receiving logic module is idle; a first sending unit for sending the write feedback if the write feedback receiving logic module is idle message to the host. a second judging unit, configured to wait a preset time to determine whether the write feedback receiving logic module is idle if the write feedback logic module is not idle; a second sending unit, configured to wait for a preset time if the write feedback receiving logic module is idle; When the module is idle, the write feedback message is sent to the host.

The multi-channel DDR interleaving control device provided by the embodiment of the present invention further includes:

The third determining module is used to determine the bandwidth information of the write data path;

The fourth determination module is used to determine the response delay information of the write command; wherein, the response delay of the write command is the time from receiving the write data and the first write address sent by the host to sending the write feedback message to the host. time difference between

A first storage module, configured to store bandwidth information of the write data path and response delay information of the write command.

The first startup module is used to start low power consumption if no read data and read response message or write feedback information sent by any slave is received, and no read address or write address or write data sent by the host is received. The timer starts counting;

The first shutdown module is used for, if when the timing time of the low power consumption timer reaches the low power consumption timing threshold, the read data and the read response message and/or the write feedback message sent by any slave have not been received and also If it does not receive the read address or write address or write data sent by the host, it will turn off its own control clock.

It should be pointed out here that the descriptions of the above embodiments of the multi-channel DDR interleaving control apparatus are similar to the descriptions of the above method embodiments, and have similar beneficial effects as the method embodiments, so they are not repeated. For the technical details that are not disclosed in the embodiments of the multi-channel DDR interleaving control apparatus of the present invention, please refer to the description of the method embodiments of the present invention for understanding. In order to save space, detailed descriptions are omitted.

Embodiment 5

An embodiment of the present invention further provides a multi-channel DDR interleaving control device. FIG. 5 is a schematic structural diagram of a multi-channel DDR interleaving control device according to Embodiment 5 of the present invention. As shown in FIG. 5 , the control device 500 includes: a third receiver Module 501, second determining module 502, third sending module 503, fourth receiving module 504 and fourth sending module 505, wherein:

The third receiving module 501 is configured to receive the first read address sent by the host;

The second determining module 502 is configured to determine, according to preset interleaving control configuration information, the second read address corresponding to the first read address and the identification information of the first slave corresponding to the first read address;

The third sending module 503 is configured to send the second read address to the first slave according to the identification information of the first slave;

The fourth receiving module 504 is configured to receive the first read data and the first read response message sent by the first slave;

The fourth sending module 505 is configured to send the first read data and the first read response message to the host.

Here, the fourth sending module 505 further includes:

a third judging unit for judging whether to receive the second read data and the second read response message sent by the second slave;

The third sending unit is configured to send the first read data and the first read response message to the host if the second read data and the second read response message sent by the second slave are not received.

The fourth judgment unit is used to judge whether the waiting time of the first slave is less than or equal to a preset response timeout threshold if the second read data and the second read response message sent by the second slave are received;

a fifth judgment unit, configured to judge whether the read priority of the first slave is higher than the read priority of the second slave if the waiting time of the first slave is less than or equal to a preset response timeout threshold;

The fourth sending unit is configured to send the first read data and the first read response message to the host if the read priority of the first slave is higher than the read priority of the second slave.

The sixth judgment unit is used to judge whether the port number of the first slave is smaller than the port of the second slave if the read priority of the first slave is the same as the read priority of the second slave No;

A fifth sending unit, configured to send the first read data and the first read response message to the host if the port number of the first slave is smaller than the port number of the second slave.

a sixth sending unit, configured to send the second read data and the second read response message to the host if the read priority of the first slave is lower than the read priority of the second slave;

a seventh judgment unit, used for judging whether to receive the third read data and the third read response message sent by the third slave;

A seventh sending unit, configured to send the first read data and the first read response message to the host if the third read data and the second read response message sent by the third slave are not received.

an eighth sending unit, configured to send the second read data and the second read response message to the host if the waiting time of the first slave is greater than a preset response timeout threshold;

an eighth judgment unit, used for judging whether to receive the third read data and the third read response message sent by the third slave;

A ninth sending unit, configured to send the first read data and the first read response message to the host if the third read data and the third read response message sent by the third slave are not received.

The multi-channel DDR interleaving control device provided by the embodiment of the present invention further includes:

the fifth determination module, used for determining the bandwidth information of the read data path;

The sixth determination module is used to determine the response delay information of the read command; wherein, the response delay of the read command is from receiving the first read address sent by the host to sending the first read data and the first read data to the host. Time difference between read response messages;

The first storage module is configured to store bandwidth information of the read data path and response delay information of the read command.

The second startup module is used to start low power consumption if no read data, read response message or write feedback information sent by any slave is received, and no read address or write address or write data sent by the host is received. The timer starts counting;

The second shutdown module is configured to, if when the timing time of the low power consumption timer reaches the low power consumption timing threshold, the read data and the read response message and/or the write feedback message sent by any of the slaves are still not received, and the If it does not receive the read address or write address or write data sent by the host, it will turn off its own control clock.

It should be pointed out here that the descriptions of the above embodiments of the multi-channel DDR interleaving control apparatus are similar to the descriptions of the above method embodiments, and have similar beneficial effects as the method embodiments, so they are not repeated. For the technical details that are not disclosed in the embodiments of the multi-channel DDR interleaving control apparatus of the present invention, please refer to the description of the method embodiments of the present invention for understanding. In order to save space, detailed descriptions are omitted.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flows of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (14)

1. a kind of interleaving control method of multi-channel double rate synchronous dynamic random access memory DDR, is characterized in that, described method comprises: Receive the write data and the first write address sent by the host; According to preset interleaving control configuration information, which includes interleaving size, non-interleaving address range, and interleaving mode, determine the second write address corresponding to the first write address and the slave address corresponding to the first write address. machine identification information, wherein the second write address is a write address obtained by mapping the first write address according to the interleaving control configuration information; sending the write data and the second write address to the slave according to the identification information of the slave; receiving a write feedback message sent by the slave, wherein the write feedback message is used to represent whether the write data is successfully written; The write feedback message is sent to the host. 2. The method according to claim 1, wherein the sending the write feedback message to the host comprises: Determine whether the write feedback receiving logic module is idle; If the write feedback receiving logic module is idle, send the write feedback message to the host. 3. The method according to claim 2, wherein the method further comprises: If the write feedback receiving logic module is not idle, after waiting for a preset time, determine whether the write feedback receiving logic module is idle; If the write feedback receiving logic module is idle, send the write feedback message to the host. 4. The method according to claim 1, wherein the method further comprises: Determine the bandwidth information of the write data channel; Determine the response delay information of the write command; wherein, the response delay of the write command is the time difference from receiving the write data sent by the host and the first write address to sending the write feedback message to the host; The bandwidth information of the write data channel and the response delay information of the write command are stored. 5. An interleaving control method for multi-channel DDR, wherein the method comprises: Receive the first read address sent by the host; Determine the second read address corresponding to the first read address and the identification information of the first slave corresponding to the first read address according to the preset interleaving size, non-interleaving address range, and interleaving mode of the interleaving controller, wherein The second read address is a read address obtained by mapping the first read address according to the interleaving control configuration information; sending the second read address to the first slave according to the identification information of the first slave; receiving the first read data and the first read response message sent by the first slave; Send the first read data and the first read response message to the host. 6. The method according to claim 5, wherein the sending the first read data and the first read response message to the host comprises: Determine whether the second read data and the second read response message sent by the second slave are received; wherein, the second slave is other than the first slave; If the second read data and the second read response message sent by the second slave are not received, the first read data and the first read response message are sent to the host. 7. The method according to claim 6, characterized in that the method further comprises: If receiving the second read data and the second read response message sent by the second slave, determine whether the waiting time of the first slave is less than or equal to the preset response timeout threshold; If the waiting time of the first slave is less than or equal to the preset response timeout threshold, determine whether the read priority of the first slave is higher than the read priority of the second slave; If the read priority of the first slave is higher than the read priority of the second slave, the first read data and the first read response message are sent to the host. 8. The method according to claim 7, wherein the method further comprises: If the read priority of the first slave is the same as the read priority of the second slave, determine whether the port number of the first slave is smaller than the port number of the second slave; If the port number of the first slave is smaller than the port number of the second slave, the first read data and the first read response message are sent to the host. 9. The method according to claim 8, wherein the method further comprises: If the read priority of the first slave is lower than the read priority of the second slave, send the second read data and the second read response message to the host; Determine whether the third read data and the third read response message sent by the third slave are received, if the third read data and the third read response message sent by the third slave are not received, then the first read data and the first read response message is sent to the host. 10. The method of claim 7, wherein the method further comprises: If the waiting time of the first slave is greater than a preset response timeout threshold, send the second read data and the second read response message to the host; Determine whether the third read data and the third read response message sent by the third slave are received; wherein, the third slave is other than the first slave; If the third read data and the third read response message sent by the third slave are not received, the first read data and the first read response message are sent to the host. 11. The method according to claim 1 or 5, wherein the method further comprises: If the read data and read response message or write feedback information sent by any slave are not received, and the read address or write address sent by the master is not received, the low-power timer is started to start timing; When the count time of the low power timer reaches the low power count threshold, the read data and read response message and/or write feedback message sent by any slave have not been received and the read address sent by the master or the read address has not been received. Write the address to turn off its own control clock. 12. The method of claim 5, wherein the method further comprises: Determine the bandwidth information of the read data channel; Determine the response delay information of the read command; wherein, the response delay of the read command is the time between receiving the first read address sent by the host and sending the first read data and the first read response message to the host. Time difference; The bandwidth information of the read data channel and the response delay information of the read command are stored. 13. An apparatus for interleaving control of multi-channel DDR, wherein the apparatus comprises: a first receiving module for receiving write data and a first write address sent by a host; wherein, the host is a bus interconnect module; a first determining module, configured to determine the second write address corresponding to the first write address and the identification information of the slave corresponding to the first write address according to preset interleaving control configuration information; the interleaving control configuration information Including interleaving size, non-interleaving address range, interleaving mode; a first sending module, configured to send the write data and the second write address to the slave according to the identification information of the slave; wherein the slave is a DDR controller; a second receiving module, configured to receive a write feedback message sent by the slave, wherein the write feedback message is used to represent whether the write data is successfully written; A second sending module, configured to send the write feedback message to the host. 14. An apparatus for interleaving control of multi-channel DDR, wherein the apparatus comprises: The third receiving module is used to receive the first read address sent by the host; The second determination module is configured to determine the second read address corresponding to the first read address and the identification information of the first slave corresponding to the first read address according to preset interleaving control configuration information; the interleaving control The configuration information includes interleaving size, non-interleaving address range, and interleaving mode; a third sending module, configured to send the second read address to the first slave according to the identification information of the first slave; a fourth receiving module, configured to receive the first read data and the first read response message sent by the first slave; The fourth sending module is configured to send the first read data and the first read response message to the host.

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