CN108228497A - A kind of DMA transfer method based on sgl chained lists - Google Patents
A kind of DMA transfer method based on sgl chained lists Download PDFInfo
- Publication number
- CN108228497A CN108228497A CN201810025217.6A CN201810025217A CN108228497A CN 108228497 A CN108228497 A CN 108228497A CN 201810025217 A CN201810025217 A CN 201810025217A CN 108228497 A CN108228497 A CN 108228497A
- Authority
- CN
- China
- Prior art keywords
- sgl
- entry
- data
- address
- men
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The present invention provides a kind of DMA transfer method based on sgl chained lists, applied in CPU.The sgl entry chained lists of at least one sgl entry are configured, each sgl entry correspond to an index, and each index is directed toward a deposit address, and deposit address is continuous.Determine current DMA transfer correspond to starting sgl entry index deposit address.DMA transfer order is initiated to dma controller, so that dma controller is according to starting sgl entry index, after finding corresponding starting sgl entry from SGL MEN, start to transfer data in the second register DATA MEN according to the storage address in sgl entry.By sgl chained lists, the data of transmitting discrete physical address become single operation.Improve data transmission efficiency.
Description
Technical field
The invention belongs to technical field of data processing, and in particular to a kind of DMA transfer method based on sgl chained lists.
Background technology
DMA (Direct Memory Access, direct memory access) transmission is to replicate data from an address space
To the transmission mode of another address space.CPU initializes this transmission action, and transmission action is by dma controller in itself
To carry out and complete.Such operation does not allow processor work to delay, and can be gone processing other by scheduling again instead
Work.DMA transfer mode is critically important for high-effect embedded system algorithm and network.
During traditional dma mode transmits data, it is desirable that source physical address and target physical address must be continuous
's.But in the system having, continuous storage address is not necessarily continuously, then to be divided into using dma mode transmission data
It repeatedly completes, CPU needs repeatedly to initiate to order to DMA.For example, after transferring one piece of continuous data of physical address, CPU to
DMA initiates an interruptive command, and then, CPU is initiated to DMA for the transmission for carrying out the next piece of continuous data of physical address again
Order until completing all data, initiates CPU and initiates interruptive command to DMA again.Wherein first piece of physical address continuously counts
First address in is source physical address, second address, first ground in one piece of continuous data of physical address thus
The target physical address of location.For example, when we will establish one from the interior DMA data transfer for being stored to disk, data are stored in object
It manages in the discontinuous buffer area in address.So CPU would generally be that each buffer area in these discontinuous buffer areas does one
Secondary transmission re-initiates a command dma when transmitting every time.Or the data in these discontinuous buffer areas all
It is moved to inside the continuous buffer area of another very big physical address, then initiates command dma again, start to transmit.When us
A number DMA from disk to memory is established according to transmission and needs to move by intermediate block, data block is distributed to interior
It deposits and does not join in continuous physical address.
As it can be seen that existing DMA data transfer method, data transmission efficiency are relatively low.
Invention content
The present invention provides a kind of DMA transfer method based on sgl chained lists, to solve existing DMA data transfer method, number
According to efficiency of transmission it is relatively low the problem of.
A kind of DMA transfer method based on sgl chained lists, applied in CPU, includes the following steps：
Acquisition is transmitted data, determines described to be transmitted the size of data and all storage address；
Sgl entry chained lists are configured, the sgl entry chained lists, the sgl are stored with the first register SGL MEN
Entry chained lists include at least one sgl entry, and each sgl entry carry one piece of storage address and are continuously transmitted data
Data size information, the storage address information for being transmitted data and next sgl entry are corresponding is transmitted number
According to storage address information, wherein, each sgl entry correspond to an index, and each index is directed toward first register
In deposit address, it is described deposit address it is continuous；
Determine that the corresponding index of starting sgl entry of the corresponding sgl entry chained lists of current DMA transfer are posted first
Deposit address in storage SGL MEN；
DMA transfer order is initiated, the DMA transfer order is sent to dma controller so that the dma controller root
According to the corresponding index of the starting sgl entry, after corresponding starting sgl entry are found from the SGL MEN, start
It is transferred data in the second register DATA MEN according to the storage address in the sgl entry.
Preferably, in a kind of above-mentioned DMA transfer method based on sgl chained lists, the sgl entry chained lists maximum is supported
2048 sgl entry.
Preferably, in a kind of above-mentioned DMA transfer method based on sgl chained lists, dma controller is in sgl entry
The smallest transmission unit for being transmitted data is 512Byte.
Preferably, in a kind of above-mentioned DMA transfer method based on sgl chained lists, the initiation DMA transfer order, by institute
It states DMA transfer order and is sent to dma controller so that the dma controller is corresponding according to the starting sgl entry
Index after corresponding starting sgl entry are found from the SGL MEN, starts according to the storage address in sgl entry
Transfer data in the second register DATA MEN, in particular to,
Dma controller is according to the starting corresponding starting sgl entry index of sgl entry, being found from SGL MEN
Corresponding first piece of storage address is continuously transmitted the initial memory address of data in beginning sgl entry, according to the starting
Storage address is transmitted data by corresponding in the starting sgl entry, and second is transmitted to according to the data size information
In register DATA MEN；
When in completing to the starting sgl entry it is corresponding be transmitted data transmission after, found from SGL MEN with
The deposit address of the sgl entry index continuously corresponding second sgl entry of next index is originated, by described the
Corresponding second block address of two sgl entry is continuously transmitted data, is stored according to the continuous starting of the second block address
Address is transmitted being transmitted in the second register DATA MEN of data by corresponding in second sgl entry.
Preferably, it in a kind of above-mentioned DMA transfer method based on sgl chained lists, further includes：
By the address partition in the second register DATA MEN, and obtain the boundary address of each subregion；
Successively data are transmitted to the second register DATA MEN, and be deposited with the second register in real time described in transmission
In the address of DATA MEN；
Judge current registrar is transmitted whether deposit address of the data in the second register DATA MEN is institute
Boundary address is stated, if it is, so that the data that are transmitted for being transmitted to the second register next time are stored to the starting point of subregion
Location.
Preferably, it in a kind of above-mentioned DMA transfer method based on sgl chained lists, is at least wrapped in each sgl entry chained lists
Include one starting sgl entry index, with it is each starting sgl entry index to the deposit address of corresponding index it
Between it is discontinuous.
Preferably, in a kind of above-mentioned DMA transfer method based on sgl chained lists, the initiation DMA transfer order, by institute
State DMA transfer order and be sent to dma controller so that the dma controller according to the starting sgl entry index, from
After finding corresponding starting sgl entry in the SGL MEN, start to transmit data according to the index in sgl entry chained lists
After into the second register DATA MEN, further include：
Judge whether to receive interrupt requests, if it is, redefining the corresponding sgl entry chained lists of current DMA transfer
Starting sgl entry index；
Wherein, interrupt requests refer to that each index in the corresponding sgl entry chained lists of the current DMA transfer is corresponded to
The storage address of data is transmitted in the sgl entry of storage and/or next sgl entry are corresponding is transmitted depositing for data
Storage address is invalid address, when the second register DATA MEN can not be transferred data to according to the invalid address, dma controller
The request of pause data transmission sent out to CPU.
A kind of DMA transfer method based on sgl chained lists provided by the invention, data transmission are completed by sgl chained lists.Sgl
Chained list is stored in the first reservoir SGL MEN, which is configured by CPU, and the time used in configuration compares existing DMA transfer mistake
It is extremely short for the time of journey.Need to transmit is the discontinuous a few block number evidences of script physical address, these data storages are in chained list
In the continuous entry in deposit address in, that is to say, that the data being transmitted are in SGL MEN, each piece of continuous physical address
Data be configured in the different entry in sgl chained lists.It has been connected between these data blocks and data block with sgl chained lists
Come, because the deposit address of the corresponding index of entry in chained list is continuous, be equal to using provided by the invention
Method transmission is the continuous data in a bulk of address.
The sgl chained lists include at least one sgl entry, and each sgl entry correspond to being passed for a fast known dimensions
Transmission of data, the storage address for being transmitted data and the corresponding storage address for being transmitted data of next sgl entry,
Then cpu initiates data transfer command, tells dma controller chained list first address, first address refers to corresponding in first entry
The continuous data in plot location initial address.After this complete continuous data of block physics of DMA transfer, just do not have to send out interruption again
, but according to according to next piece be directed toward in chained list, physically contiguously the initial address of location continues to transmit.When complete this
In chained list after the corresponding data transmissions of the last one entry, initiate primary interrupt and can be completed when time DMA data transfer process.
It will be apparent that after using a kind of DMA transfer method based on sgl chained lists provided by the invention, by sgl chained lists,
It is single operation by the data transmission from discrete object reason address to the process of appropriate location.Be configured that sgl chained lists need when
Between add time using sgl chained lists transmission data compared to transmit in existing DMA transfer mode a block number according to initiate it is primary in
The disconnected mode required time is few, and efficiency is much higher.
Description of the drawings
Fig. 1 is a kind of flow diagram of the DMA transfer method based on sgl chained lists provided by the invention；
Fig. 2 is a sgl chain tableau format；
The form that Fig. 3 is an entry in sgl chained lists in Fig. 2.
Specific embodiment
The present invention provides a kind of DMA transfer method based on sgl chained lists, solves existing DMA data transfer method, number
According to efficiency of transmission it is relatively low the problem of.
Incorporated by reference to Fig. 1, the figure shows a kind of flows of the DMA transfer method based on sgl chained lists provided by the invention to show
It is intended to, applied in CPU, the full name of sgl chained lists is scatter-gather list, which is characterized in that is included the following steps：
In step S01, determine when time size of DMA transfer data and all storage address.Data to be passed from memory
It transports to for the process in disk, storage address refers to discrete, storage number to be transmitted in buffer area discrete in memory
According to address.
Then, in step S02, CPU configuration sgl entry chained lists are stored described with the first register SGL MEN
Sgl entry chained lists.First register SGL MEN can be written and read by cpu.When CPU configuration sgl chained lists need to expend
Between, it is extremely short for the time that the time used in configuration compares existing DMA transfer process.
The sgl entry chained lists include at least one sgl entry, and each sgl entry carry one piece of storage address
The continuous data size information, the storage address information for being transmitted data and next sgl for being transmitted data
The corresponding storage address informations for being transmitted data of entry, wherein, each sgl entry correspond to an index, each index
The deposit address in first register is directed toward, the deposit address is continuous.
Equally by taking the process for being transmitted to data in disk from memory as an example, need to transmit is that script physical address does not connect
Continuous a few block number evidences, the data of each discontinuous physical addresses are configured in the different entry in sgl chained lists.
As shown in Fig. 2, a sgl chained list is made of several continuous sgl entry.It is stored in each sgl entry
Data account for certain space, storage address also accounts for certain space, if Fig. 3 shows the structure of some sgl entry, these
How much space is represented in the structure of some sgl entry with bit wide.Mainly include in three parts in some sgl entry structure
Hold, Sector_count, Address and Next_entry_idx, the meaning of representative is as shown in Table 1.
The structure of table a sgl entry one by one
| Title | Bit wide | Description |
| Sector_count | 9 | The corresponding data of this entry account for how many a 512Byte； |
| Address | 24 | The storage address (512Byte alignment) of access； |
| Next_entry_idx | 11 | The index of the storage address of next transmission data； |
It is maximum in each chained list to support 2048 sgl entry.Such as Sgl_entry0--->sgl_entry1--->sgl_
entry2--->sgl_entry7---->sgl_entry90……sgl_entry2048；The deposit address of all index is to connect
Continuous.Dma controller is 512Byte to the smallest transmission unit for being transmitted data in sgl entry.
Match when CPU completion sgl chained lists and postpone, in step S03, determine the corresponding sgl entry chained lists of current DMA transfer
Starting sgl entry index, that is, determine this data transmission wherefrom proceed by.Each sgl entry
Using as starting entry, once it is determined that starting sgl entry, according to method provided by the invention, the process for transmitting data is straight
Terminate until the address of the storage in a last sgl entry.
Such as：Want the data of disposable transmission 18K, preceding 4K initial addresses are 0x0, and intermediate 13.5K initial addresses are
0x7000, last 0.5K are 0x8000, following register SGL MEN can be configured, the structure of the register is as shown in Table 2：
The structure of two register SGL MEN of table
| Register address | Value | Description |
| 0x00000000 | 0x8 | 0 data lengths of Sgl entry are 4K, initial address 0x0 |
| 0x00000001 | 0x2 | The next sgl entry index that Sgl entry 0 are directed toward is 0x01 |
| 0x00000002 | 0x7001 | 1 data lengths of Sgl entry are 13.5K, initial address 0x7000 |
| 0x00000003 | 0x04 | The next sgl entry index that Sgl entry 1 are directed toward is 0x02 |
| 0x00000004 | 0x8001 | 2 data lengths of Sgl entry are 0.5K, initial address 0x8000 |
| 0x00000005 | 0x06 | The next sgl entry index that Sgl entry 2 are directed toward is 0x03 |
| 0x00002001 | 0x00 | First sgl entry are directed toward 0 |
| 0x00002000 | 0x20 | Start DMA transfer, conveying length 18K |
In table two：The value of the first row configuration corresponds to the sector_count of table one, and 0base alignment such as with setting to 0, represents
Sector_count is 0, and it is 512byte to represent this SGL conveying length；The value of 2 second row of table configuration corresponds to table one
next_entry_index；The value of two the third line of table configuration is the Address of table one；The value of two fourth line of table configuration is next
The situation of sgl entry；Two fifth line of table, the 6th row and the situation of the third line, fourth line are corresponding respectively；The 7th row of two table 2 of table
" Firstsgl entry are directed toward 0 " refers to be directed toward Index0, the starting position of ssgl chained lists.The 8th row of table 2 starts DMA transfer,
Dma controller finds the starting index of sgl chained lists according to the starting position shown in the 7th row, is extracted successively according to starting index
Sgl link table informations.
In step S04, CPU initiates DMA transfer order, and the DMA transfer order is sent to dma controller so that
The dma controller finds corresponding starting sgl according to the starting sgl entry index from the SGL MEN
After entry, start to transfer data in the second register DATA MEN according to the storage address in sgl entry chained lists.Such as table
Shown in two, the DMA transfer order of CPU initiations carries the size information of transmission data, is conveying length 18k.Utilize the present invention
The method of offer, the process for transmitting this 18k are：Dma controller is told chained list first address.The complete one piece of physics of DMA transfer is continuous
Data after, just do not have to send out interruptions again, but according to the first address continuation of next piece be directed toward in chained list physically contiguously location
It is transmitted.After the corresponding data transmissions of the last one entry in this chained list are completed, primary interrupt is initiated.As shown in Table 2,
The sgl chained lists of the secondary DMA data transfer CPU configurations include three sgl entry, i.e. Sgl entry0,1 and of Sgl entry
Sgl entry 2.Dma controller is according to the corresponding starting sgl entry of starting sgl entry index 0, from SGL MEN
Corresponding the first storage address for being transmitted data in starting sgl entry is found, is as shown in Table 2 initial address 0 × 0, presses
Data are transmitted by corresponding in the starting sgl entry0, size is transmitted to for 4k according to first storage address 0 × 0
In two register DATA MEN.When in completing to the starting sgl entry it is corresponding be transmitted data 4k transmission after, from
It is found in SGL MEN and continuous corresponding the second storages for being transmitted data of next sgl entry of starting sgl entry
Location 0x7000 is transmitted data according to second storage address by corresponding in the starting sgl entry, and size is
13.5k is transmitted in the second register DATA MEN.After the transmission for completing above-mentioned 13.5k, sgl is found from SGL MEN
The corresponding third storage address 0x8000 for being transmitted data of entry2, according to the third storage address by the starting sgl
Corresponding in entry to be transmitted data, size is transmitted to for 0.5k in the second register DATA MEN.That is, originally simultaneously
Discontinuous, initial address is respectively three pieces of discontinuous discrete datas of 0x0,0x7000 and 0x8000, is arranged, respectively
In continuous entry0, entry1, entry2 of SGL chained lists.The data of these discontinuous addresses are together in series with sgl chained lists,
Because the deposit address of the corresponding index of entry in chained list is continuous, it is equal to and utilizes method provided by the invention
Transmission is the continuous data in a bulk of address.The process of transmission is that the storage of data is found according to the index of sgl chained lists
Address.
It will be apparent that after using a kind of DMA transfer method based on sgl chained lists provided by the invention, by sgl chained lists,
It is single operation by the process of the data transmission of physical address discrete in memory to appropriate location, in conjunction with table two,
That is the process of transmission 18k data is single operation.The time that sgl chained lists, which are configured, to be needed adds is transmitted using sgl chained lists
The time of data, which is compared, transmits the mode required time that a block number is once interrupted according to initiation in existing DMA transfer mode
Few, efficiency is much higher.It should be noted that the sgl entry chained lists include at least one sgl entry, if only
If sgl chained lists there are one sgl entry, because the storage address in the sgl entry is continuous, it is equivalent to current
DMA transfer be continuous physical address data.That is, a kind of DMA transfer based on sgl chained lists provided by the invention
Method both supported continuous data to transmit, and discrete data transmission, and the either transmission of which kind of data was also supported, based on configuration
After sgl chained lists, using sgl entry index are originated, efficiency of transmission can be effectively improved.
In the above-mentioned technical solutions, following optimization can be done, corresponding starting sgl is found from the SGL MEN
After entry, start after being transferred data in the second register DATA MEN according to the index in sgl entry chained lists, also wrap
It includes：
CPU judges whether to receive interrupt requests, if it is, redefining the corresponding sgl entry chains of current DMA transfer
The starting sgl entry index of table.Wherein, interrupt requests refer in the corresponding sgl entry chained lists of the current DMA transfer
Each index correspond to storage sgl entry in be transmitted data storage address and/or next sgl entry correspond to
The storage address for being transmitted data for invalid address, the second register DATA can not be transferred data to according to the invalid address
During MEN, the request of pause data transmission that dma controller is sent out to CPU.
By taking the data transmission procedure in table two as an example, above-mentioned optimization process is illustrated.If it is deposited in Sgl entry 1
When the initial address of storage is 0x6999, dma controller can not find the size that needs transmit according to the initial address of mistake and be
The data of 13.5k, then controller to CPU occur interrupt requests, so that CPU reconfigures sgl chained lists, redefine current DMA
The starting sgl entry index of transmission, the starting sgl entry index reaffirmed can be Sgl entry 0 or
It is to have corrected correct storage address Sgl entry 1.If Sgl entry0, then restart the data transmission mistake in table two
Journey.Technical solution after optimizing in this way, it can be ensured that use the accuracy of transmission method provided by the invention.
It is understood that need the time if a sgl chained list is configured for each DMA transfer, then transmission
The time of multiple data is to be superimposed the time of each configuration sgl chained lists.In order to further improve side provided by the invention
The efficiency of transmission of method makes following optimization to above-mentioned technical method：One can be included at least in each sgl entry chained lists to rise
Beginning sgl entry index, the deposit address of each sgl entry index are discontinuous.That is, it is transmitted several times shared one
A sgl chained lists.Transmission order individually is initiated to dma controller during each DMA, is respectively carried in each transmission order
As the starting sgl entry of secondary transmission, and the deposit address of these corresponding index of sgl entry is in same sgl chained lists
In be discontinuous.It is independent between each secondary DMA data transfer.
Based on the purpose of identical raising efficiency of transmission, following optimization is made to above-mentioned technical proposal：
By the address partition in the second register DATA MEN, and obtain the boundary address of each subregion；
Successively data are transmitted to the second register DATA MEN, and be deposited with the second register in real time described in transmission
In the address of DATA MEN；
Judge current registrar is transmitted whether deposit address of the data in the second register DATA MEN is institute
Boundary address is stated, if it is, so that the data that are transmitted for being transmitted to the second register next time are stored to the starting point of subregion
Location.The technical optimization of above-mentioned support boundary wraparound is the accuracy in order to ensure data transmission.If there is no boundary wraparound, DMA controls
Certain data may be stored to beyond the address of DATA MEM address ranges by device processed in some cases, eventually led to data and lost
It loses.For example, CPU wants to store the data of 2K, but the space of DATA MEM only has the situation of 1.5K, if not having boundary wraparound
Prioritization scheme, when according to method provided by the invention, after the data transmission of 2k to DATA MEM, if data are from DATA
Not in time, the data of 2K can not be all deposited in the space of 1.5k simultaneously, and follow-up data can cover front and continued number for the reading of MEM
According to causing loss of data.
The above is only the specific embodiment of this practicality invention, is made skilled artisans appreciate that or realizing this
Practicality invention.A variety of modifications of these embodiments will be apparent to one skilled in the art, institute herein
The General Principle of definition can in other embodiments be realized in the case of the spirit or scope for not departing from this practicality invention.
Therefore, this practicality invention is not intended to be limited to the embodiments shown herein, and is to fit to and original disclosed herein
The reason most wide range consistent with features of novelty.
Claims (7)
1. a kind of DMA transfer method based on sgl chained lists, applied in CPU, which is characterized in that include the following steps：
Determine the size of the data when time DMA transfer and all storage address；
Sgl entry chained lists are configured, the sgl entry chained lists, the sgl are stored with the first register SGL MEN
Entry chained lists include at least one sgl entry, and each sgl entry carry one piece of storage address and are continuously transmitted data
Data size information, the storage address information for being transmitted data and next sgl entry are corresponding is transmitted number
According to storage address information, wherein, each sgl entry correspond to an index, and each index is directed toward first register
In deposit address, it is described deposit address it is continuous；
Determine the corresponding index of starting sgl entry of the corresponding sgl entry chained lists of current DMA transfer in the first register
Deposit address in SGL MEN；
DMA transfer order is initiated, the DMA transfer order is sent to dma controller so that the dma controller is according to institute
State the corresponding index of starting sgl entry, after corresponding starting sgl entry are found from the SGL MEN, start according to
Storage address in the sgl entry is transferred data in the second register DATA MEN.
A kind of 2. DMA transfer method based on sgl chained lists according to claim 1, which is characterized in that the sgl
Entry chained lists maximum supports 2048 sgl entry.
A kind of 3. DMA transfer method based on sgl chained lists according to claim 1, which is characterized in that dma controller pair
The smallest transmission unit for being transmitted data in sgl entry is 512Byte.
A kind of 4. DMA transfer method based on sgl chained lists according to claim 1, which is characterized in that the initiation DMA
Transmission order, is sent to dma controller so that the dma controller is according to the starting sgl by the DMA transfer order
The corresponding index of entry after corresponding starting sgl entry are found from the SGL MEN, start according in sgl entry
Storage address transfer data in the second register DATA MEN, in particular to,
Dma controller finds starting according to the corresponding starting sgl entry index of starting sgl entry from SGL MEN
Corresponding first piece of storage address is continuously transmitted the initial memory address of data in sgl entry, is deposited according to the starting
Storage address is transmitted data by corresponding in the starting sgl entry, and being transmitted to second according to the data size information posts
In storage DATA MEN；
When in completing to the starting sgl entry it is corresponding be transmitted data transmission after, find and originate from SGL MEN
The continuous corresponding second sgl entry of next index in the deposit address of sgl entry index, by described second
Corresponding second block address of sgl entry is continuously transmitted data, according to the continuous initial memory address of the second block address
Being transmitted in the second register DATA MEN of data is transmitted by corresponding in second sgl entry.
5. a kind of DMA transfer method based on sgl chained lists according to claim 1, which is characterized in that further include：
By the address partition in the second register DATA MEN, and obtain the boundary address of each subregion；
Successively data are transmitted to the second register DATA MEN, and be deposited with the second register DATA in real time described in transmission
In the address of MEN；
Judge current registrar is transmitted whether deposit address of the data in the second register DATA MEN is the side
Limit address, if it is, so that the data that are transmitted for being transmitted to the second register next time are stored to the initial address of subregion.
A kind of 6. DMA transfer method based on sgl chained lists according to claim 1, which is characterized in that each sgl
A starting sgl entry index is included at least in entry chained lists, with each starting sgl entry index to corresponding
It is discontinuous between the deposit address of index.
A kind of 7. DMA transfer method based on sgl chained lists according to claim 1, which is characterized in that the initiation DMA
Transmission order, is sent to dma controller so that the dma controller is according to the starting sgl by the DMA transfer order
Entry index after corresponding starting sgl entry are found from the SGL MEN, start according in sgl entry chained lists
Index transfer data in the second register DATA MEN after, further include：
Judge whether to receive interrupt requests, if it is, redefining rising for the corresponding sgl entry chained lists of current DMA transfer
Beginning sgl entry index；
Wherein, interrupt requests refer to that each index in the corresponding sgl entry chained lists of the current DMA transfer corresponds to storage
Sgl entry in be transmitted the storage address of data and/or the corresponding storages for being transmitted data of next sgl entry
Location is invalid address, when the second register DATA MEN can not be transferred data to according to the invalid address, dma controller to
The request of pause data transmission that CPU is sent out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810025217.6A CN108228497A (en) | 2018-01-11 | 2018-01-11 | A kind of DMA transfer method based on sgl chained lists |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810025217.6A CN108228497A (en) | 2018-01-11 | 2018-01-11 | A kind of DMA transfer method based on sgl chained lists |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108228497A true CN108228497A (en) | 2018-06-29 |
Family
ID=62640189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810025217.6A Pending CN108228497A (en) | 2018-01-11 | 2018-01-11 | A kind of DMA transfer method based on sgl chained lists |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108228497A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109597654A (en) * | 2018-12-07 | 2019-04-09 | 湖南国科微电子股份有限公司 | Initialization of register method, the generation method and embedded system of configurations table |
| WO2021121054A1 (en) * | 2019-12-17 | 2021-06-24 | 北京忆芯科技有限公司 | Sgl processing acceleration method and storage device |
| CN114756490A (en) * | 2022-03-21 | 2022-07-15 | 奥比中光科技集团股份有限公司 | DMA data carrying method and device |
| CN115658351A (en) * | 2022-12-27 | 2023-01-31 | 北京象帝先计算技术有限公司 | 2D copying method, device, electronic equipment and computer readable storage medium |
| CN115883022A (en) * | 2023-01-06 | 2023-03-31 | 北京象帝先计算技术有限公司 | DMA (direct memory access) transmission control method and device, electronic equipment and readable storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020144027A1 (en) * | 2001-03-27 | 2002-10-03 | Schmisseur Mark A. | Multi-use data access descriptor |
| US20050033874A1 (en) * | 2003-08-05 | 2005-02-10 | Futral William T. | Direct memory access using memory descriptor list |
| CN101030183A (en) * | 2007-04-03 | 2007-09-05 | 北京中星微电子有限公司 | Direct memory access controller and method for realizing memory batch processing |
| CN101059785A (en) * | 2006-04-17 | 2007-10-24 | 中兴通讯股份有限公司 | Method for implementing two-dimensional data delivery using DMA controller |
| CN101149717A (en) * | 2007-11-16 | 2008-03-26 | 威盛电子股份有限公司 | Computer system and direct memory access transmission method |
| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
-
2018
- 2018-01-11 CN CN201810025217.6A patent/CN108228497A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020144027A1 (en) * | 2001-03-27 | 2002-10-03 | Schmisseur Mark A. | Multi-use data access descriptor |
| US20050033874A1 (en) * | 2003-08-05 | 2005-02-10 | Futral William T. | Direct memory access using memory descriptor list |
| CN101059785A (en) * | 2006-04-17 | 2007-10-24 | 中兴通讯股份有限公司 | Method for implementing two-dimensional data delivery using DMA controller |
| CN101030183A (en) * | 2007-04-03 | 2007-09-05 | 北京中星微电子有限公司 | Direct memory access controller and method for realizing memory batch processing |
| CN101149717A (en) * | 2007-11-16 | 2008-03-26 | 威盛电子股份有限公司 | Computer system and direct memory access transmission method |
| CN102314400A (en) * | 2011-09-27 | 2012-01-11 | 广东威创视讯科技股份有限公司 | Method and device for dispersing converged DMA (Direct Memory Access) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109597654A (en) * | 2018-12-07 | 2019-04-09 | 湖南国科微电子股份有限公司 | Initialization of register method, the generation method and embedded system of configurations table |
| CN109597654B (en) * | 2018-12-07 | 2022-01-11 | 湖南国科微电子股份有限公司 | Register initialization method, basic configuration table generation method and embedded system |
| WO2021121054A1 (en) * | 2019-12-17 | 2021-06-24 | 北京忆芯科技有限公司 | Sgl processing acceleration method and storage device |
| CN114756490A (en) * | 2022-03-21 | 2022-07-15 | 奥比中光科技集团股份有限公司 | DMA data carrying method and device |
| CN115658351A (en) * | 2022-12-27 | 2023-01-31 | 北京象帝先计算技术有限公司 | 2D copying method, device, electronic equipment and computer readable storage medium |
| CN115883022A (en) * | 2023-01-06 | 2023-03-31 | 北京象帝先计算技术有限公司 | DMA (direct memory access) transmission control method and device, electronic equipment and readable storage medium |
| CN115883022B (en) * | 2023-01-06 | 2023-05-12 | 北京象帝先计算技术有限公司 | DMA transfer control method, device, electronic device and readable storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108228497A (en) | A kind of DMA transfer method based on sgl chained lists | |
| CN110089040B (en) | Data transmission method and sending end equipment | |
| WO2021043060A1 (en) | Indication method and device, and storage medium | |
| US11063850B2 (en) | Slave-to-master data and out-of-sequence acknowledgements on a daisy-chained bus | |
| TWI565337B (en) | Packet data convergence protocol (pdcp) enhancements in dual-connectivity networks | |
| JP2020504584A5 (en) | ||
| JP2015019373A5 (en) | ||
| EP2852101B1 (en) | Method and device for data transmission in wireless local area network | |
| CN103914007B (en) | Method and system for program retuning | |
| US20220066702A1 (en) | Electronic device for communicating with host and operating method of the electronic device | |
| JP2007266775A5 (en) | ||
| TWI648965B (en) | Method for upgrading adapter, mobile terminal and adapter | |
| JP2011239076A5 (en) | ||
| TW201321242A (en) | Digital signal transceiver, method and electrombile system thereof | |
| CN117714401A (en) | Method and system for optimizing data flow between devices | |
| CN109189702A (en) | A kind of transmission data buffer design method of Scatter-Gather DMA | |
| JPH0567009A (en) | File transfer processing method | |
| US20210160320A1 (en) | Data transmission and network interface controller | |
| JP6299074B2 (en) | Wireless communication network system, wireless communication terminal, and wireless communication method | |
| CN107222379A (en) | A kind of method and apparatus of serial communication | |
| JP2023159308A5 (en) | ||
| CN104616407A (en) | Method for communicating POS machine with remote server, POS machine and mobile terminal | |
| CN102495814A (en) | Communication method between controllers of storage device | |
| US11188483B2 (en) | Architecture for microcontroller and method for reading data applied to microcontroller | |
| WO2018040429A1 (en) | Usb device simulation apparatus and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180629 |